JPS6130059A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS6130059A
JPS6130059A JP15059884A JP15059884A JPS6130059A JP S6130059 A JPS6130059 A JP S6130059A JP 15059884 A JP15059884 A JP 15059884A JP 15059884 A JP15059884 A JP 15059884A JP S6130059 A JPS6130059 A JP S6130059A
Authority
JP
Japan
Prior art keywords
layer
bumps
circuit boards
metal
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15059884A
Other languages
English (en)
Inventor
Masaaki Yasumoto
安本　雅昭
Hiroshi Hayama
浩 葉山
Tadayoshi Enomoto
榎本　忠儀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15059884A priority Critical patent/JPS6130059A/ja
Priority to DE19853586732 priority patent/DE3586732T2/de
Priority to EP19850108891 priority patent/EP0168815B1/en
Priority to US06/755,987 priority patent/US4612083A/en
Publication of JPS6130059A publication Critical patent/JPS6130059A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に係）、更に詳しくは、機能
が異なる半導体集積回路基板を積層して得られる多層半
導体集積回路の製造方法に関する。
〔従来技術とその問題点〕
多層半導体集積回路は、トランジスタ、ダイオード、抵
抗、容量等の機能菓子と各機能素子間を接続する金属配
線等が平面上に集積化された能動層を複数層積層した構
造を持ち、単一能動層からなる現在良く知られた二次元
半導体集積回路に比べて、集積回路の集積密度の向上や
、多機能化が期待できる。多層半導体集積回路の製造方
法として現在知られているものは、（１）第１の能動層
上に形成された絶縁膜上に、レーザビーム、電子ビーム
、あるいはストリップヒータ等を用いてアニールし再結
晶化させたポリシリコン層（ＳＯＩ構造）を形成し、（
２）このポリシリコン層上に第２の能動層を形成し、以
下、これらの工程を繰ル返すことによシ多層化する方法
である（　Ｓ、Ｋａｗａｍｕｒａ　。
ＩＥＤＭ　Ｔｅｃｈｎｉｃａｌ　ＤｉｇｅｓｔＢ、　Ｐ
Ｐ　、　３６４　、１９８３）。
しかしこの方法には、能動層を順に形成するため、製造
期間が長くなる２歩留シの低下が激しい９等の短所があ
る。更には、各能動層の表面を平担にする技術、既に形
成されている下層の能動層の素子特性を劣化させずに新
しく積層する能動層を作製する低温プロセス技術、ある
いは大面積のＳＯＩ構造を形成する技術、等新たに開発
を必要とする新技術が多い。
〔本発明の目的〕
本発明は、従来の多層半導体集積回路の製造方法の欠点
を除去できる多層半導体集積回路の製造方法を提供する
ことを目的とする。
〔発明の構成〕
本発明に依れば１表面に絶縁層が形成された半導体装置
を半導体基板上に形成し、前記絶縁層の一部分を貫通す
る金属バンプを形成して得られる半導体回路基板を２枚
準備し、一方あるいは両方の半導体回路基板の表面に該
金属バンプを十分に覆い、しかも表面がほぼ平担になる
膜厚の絶縁性樹脂接着剤層を回転塗布し、しかる後、前
記金属バンプの表面が現われるまで、該絶縁性樹脂接着
剤層を一様にエツチングし、次にとれら２枚の半導体回
路基板表面を互い対向させた状態で、両半導体回路基板
上の金属バンプが互−に一致するようにして両半導体回
路基板を接触させ、咳絶縁性樹脂接着剤層を加熱、乾燥
させることＫより、両半導体回路基板を接着させ、しか
も咳金属バンプ同志を電気的に接続させることを特徴と
する半導体装置の製造方法が得られる。
〔実施例〕
以下、図面を用いて本発明の実施例を詳細に説明する。
第１図（ａ）〜（ｆ）は本発明を用い声多層半導体集積
回路の製造方法の流れである。第１図（ａ）は。
シリコン、ガリウム砒素等の半導体や二酸化シリコン、
サファイア等の絶縁体からなる基板１０１上Ｋ、機能素
子、およびこれらを互いに接続するアルミニウム等の金
属配線からなる能動層１０２と、１０２を保護する二酸
化シリコン等の絶縁層１０３を形成した半導体回路基板
１を示したものである。この半導体回路基板１は、通常
の二次元集積回路を製造するプロセス、例えばＮＭＯＳ
プロセス、ＰＭＯＳプロセス、ＣＭＯＳプロセス、バイ
ポーラプロセス、等によシ作製される。
次に第１図中）に示すように、ｌ上の１０３の一部に開
口部を設け、この開口部に金等の金属バンプ１０４′ｆ
ｔ：形成する。第１図（ｂ）を形成する方法として、与
真喰刻法を用いてパターン化されたフォトレジスＩｆマ
スクとし、７ツ酸等の薬品を用いて二酸化シリコン等の
１０３を開口した後、真空蒸着等により１０３の膜厚よ
シ厚い、金等の金属膜を形成し、最後にフォトレジスト
を除去（リフトオツ７法と言う）し、金属バンプ１０４
ｔ−形成する方法等がある。尚、１０４は能動層１０２
と機能的に接続されている。
この後、第１図（ｅ）に示すように、絶縁層１０３、お
よび１０４上Ｋ、１０４を完全に覆い、しかも表面が殆
ど平担化される膜厚のポリイミド系樹脂等の絶縁性樹脂
接着剤をスピン塗布する。例えば。
金属バンプの高さを能動層１０２の表面から測って１．
５μｍとし、ポリイミド系樹脂の膜厚が２．５μｍ程度
になるように、スピン速度やスピン時間を選ぶと、塗布
後の表面はは埋平担になる。次に酸素プラズマ中等で絶
縁性樹脂接着剤層を表面から一様に金属バンプ１０４の
表面が現われるまでエツチングする。
この結果、第１図（ｄ）Ｋ示されているように、金属バ
ンプ１０４が露出し、それ以外の部分が平担な絶縁性樹
脂接着剤層１０５でおおわれた半導体回路基板１が得ら
れる。以上の工程を経た半導体回路基板を２枚準備し、
一方の表面を上向きに、他方の表面を下向きにし、これ
らの半導体回路基板に設けられた金属バッグの位置が元
いに一致するように目合せを行なう〔第１図（ｅ）〕。
以下の説明では、下の半導体回路基板を第１の回路基板
１５０゜上の半導体回路基板を第２の回路基板１５１と
称する。図面番号は、１５０が第１図（ｄ）の番号を。
１５１が第１図（ｄ）の番号にダッシュがついた本のを
使用する。
目合せ方法の１例として、縮少投影露光機等に用いられ
ているオフ・アクシス法がある。目合せ装置内に２か所
の目合せ場所を設ける。それぞれの目合せ場所にはチッ
プあるいはウニ／１−を固定するステージと目合せ基準
マークが設けられている。２か所の目合せ基準マークの
距離はあらかじめ決められている。まず、１５０．１５
１４’それぞれのステージに固定した後、ステージを微
動させ、それぞれの目合せ基準マークと一致させる。次
に、一方、例えば１５０が固定されているステージを目
合せ基準マーク間の距離だけ移動させ、１５０が１５１
の直下へ来るようにする。この結果、１５０と１５１は
ステージを移動させる機械的な精度内で目合せされる。
最後に、１５０と１５１の平面方向の相対位置を保った
状態で、１５０と１５１を接触、加熱し。
１０５．１０５’を乾燥させることにより、１０５と１
０５′を接着させ、第１図（ｆ）に示されている多層半
導体集積回路が実現できる。この時、金属バンプ１０４
，１０４’も接触し、１５０と１５１は、１０４゜１０
４′を介して電気的に接続される。１０５，１０５′が
ポリイミド系樹脂の場合、加熱する温度は２５０〜４０
０℃１時間は２０〜６０分である。加熱時に１５０と１
５１′の間にある一定の圧力を加えれば、１０４と１０
４″は互いに拡散溶接され、１０４，１０４’間の電気
抵抗が非常に小さくなる他、１５０と１５１′の接着力
も強化される。
第２図は、本発明の製造方法を用いて作製された２層半
導体集積回路の一例である。２０１は第１の回路基板（
以下下層と称する）２５０のシリコン等の基板、２０２
は二酸化シリコン等の絶縁膜。
２２０は、ソース、ドレイン２０３，２０５　、チャネ
ル２０４．ゲート２０６がＳＯＩ構造上に作製された下
層の薄膜トランジスタである。２０７は下層の金属配線
、２０８は、下層の絶縁層である。また、２０９は、下
層の金属バンプ、２１０は下層の絶縁性樹脂接着剤層で
ある。尚、第２の回路基板（以下、上層と称する）２５
１のうち、下層と同一素子は、下層の素子番号にダッシ
ュが付けられている。
第２図に示されているように、上下層の薄膜トランジス
タ、２２０，２２０’のソース、ドレイン２０５゜２０
５′は、金属配線、２０７，２０７’および金属バンプ
２０９，２０９’ｆｆｉ介して接続され、目的とする回
路を形成することができる。
第２図は、２層半導体集積回路について示されているが
、上下層に、それぞれ、従来方式を用いて作製されたに
層、に′層半導体集積回路を用いれば、（ｋ十に’）層
の多層集積回路も実現できる。
あるいは、第２図において、上層の絶縁膜２０２″を貫
通する垂直配線ｔ−Ｓらかじめ設けておき、本発明を用
いて上下層を積層した後、上層の基板２０１′を除去し
、再び本発明を用いて、第３の回路基板を積層する工程
を繰シ返せば３層以上の多層半導体集積回路も実現でき
る。３層積層した場合の一例を第３図に示す、３０１は
、第１の回路基板で第２図の２５０に相等する。３０２
は第２の回路基板で第２図の２５１から基板２０１′を
除去したものに相等する。３０１．３０２を構成する素
子名は、第２図のそれと等しい。新しく追加されている
部分は、絶縁［２０２’を貫通する金やアルミニウム等
からなる垂直配線３０４である。３０３は、第３の回路
基板である。３１１は基板、３０５は、絶縁膜。
３０６は薄膜トランジスタ、３０７は、金属配線。
３０８は、絶縁層、３０９は、金属バンク、３１０は、
第３の回路基板上に形成された絶縁性樹脂接着剤層であ
る。、３０６は、３０７．３０９，２０９’を介して電
気的に、２０７′と接続されるから、第１゜第２．第３
の回路基板は、機能的に接続される。
第１図の説明では、絶縁性樹脂接着剤層を第１および第
２の回路基板に形成する場合について説明したが、一方
の回路基板にのみ形成する場合であってもかまわない。
また、第２図、第３図において、各層の回路基板として
ＳＯＩ構造を示したが、これに限るものでない。全く異
なる基板、たとえばシリコン基板とＳＯ８基板、シリコ
ン基板とガリウム砒素基板でもかまわない。あるいは、
全く異なる機能、例えば、ＣＭＯ８集積回路とイメージ
センサ、信号処理用集積回路と発光、受光菓子との組み
合わせ等でもよい。また、第１の回路基板と第２の回路
基板のサイズが異なってもかまわない。例えば、ウェハ
ースケール集積回路上に複数個の小さなチップを積層す
る場合も考えられる。
〔発明の効果〕
本発明に依れば、各層の能動層は並行して同時に作製で
きるから従来の多層半導体集積回路の製造方法に比べて
製造期間が短縮できる。また、各層の能動層をあらかじ
め検査し、正常な動作をするもののみ積層すれば歩留シ
の向上が期待できる。
また、レーザアニール技術等による大面積ＳＯＩ製造技
術の開発を待たずして、バルク基板やＳＯ８基板を用い
た多層半導体集積回路が実現できるから、開発スｅ−ド
が早い、また、積層するプロセスが低温プロセスである
。絶縁性樹脂接着剤層を形成する工程で各層の回路基板
表面が平担化される１等、今までの製造方法の欠点を除
去できる。
更には、各層の回路基板の構造、製造プロセスに制限が
ないから、多機能化等、今までの製造方法では、考えら
れなかった応用も可能となる。
【図面の簡単な説明】
第１図（＆）〜（ｆ）は本発明による多層半導体集積回
路の製造方法の流れを説明するための断面図である。１
０１，１０２，１０３，１０４，１０５はそれぞれ、基
板、能動層、絶縁層、金属バンプ、絶縁性樹脂接着剤層
である。また１５０．１５１は、第１の回路基板、第２
の回路基板である。第２図、第３図は、本発明の応用例
の断面図で、それぞれ２層半導体集積回路、３層半導体
集積回路を示したものである。２５０．３０１は第１の
回路基板、２５１゜３０２は第２の回路基板、３０３は
第３の回路基板である。 第１図 第１図 第２図 第３図

Claims (1)

    【特許請求の範囲】
  1. 　表面に絶縁層が設けられた半導体装置を半導体基板上
    に形成し、前記絶縁層の一部分を貫通する金属バンプを
    形成して得られる半導体回路基板を２枚準備し、一方あ
    るいは両方の半導体回路基板の表面に該金属バンプを十
    分に覆い、しかも表面がほぼ平担になる膜厚の絶縁性樹
    脂接着剤層を回転塗布し、しかる後、前記金属バンプの
    表面が現われるまで、該絶縁性樹脂接着剤層を一様にエ
    ッチングし、次にこれら２枚の半導体回路基板表面を互
    い対向させた状態で、両半導体回路基板上の金属バンプ
    が互いに一致するようにして両半導体回路基板を接触さ
    せ、該絶縁性樹脂接着剤層を加熱、乾燥させることによ
    り、両半導体回路基板を接着させ、しかも該金属バンプ
    同志を電気的に接続させることを特徴とする半導体装置
    の製造方法。
JP15059884A 1984-07-20 1984-07-20 半導体装置の製造方法 Pending JPS6130059A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP15059884A JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法
DE19853586732 DE3586732T2 (de) 1984-07-20 1985-07-16 Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
EP19850108891 EP0168815B1 (en) 1984-07-20 1985-07-16 Process for fabricating three-dimensional semiconductor device
US06/755,987 US4612083A (en) 1984-07-20 1985-07-17 Process of fabricating three-dimensional semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15059884A JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS6130059A true JPS6130059A (ja) 1986-02-12

Family

ID=15500377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15059884A Pending JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4612083A (ja)
EP (1) EP0168815B1 (ja)
JP (1) JPS6130059A (ja)
DE (1) DE3586732T2 (ja)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272556A (ja) * 1986-05-20 1987-11-26 Fujitsu Ltd 三次元半導体集積回路装置及びその製造方法
JPH0442957A (ja) * 1990-06-06 1992-02-13 Matsushita Electron Corp 半導体集積回路装置の製造方法
JPH04132258A (ja) * 1990-09-25 1992-05-06 Nec Corp 半導体基板の接続体およびその接続方法
US5327621A (en) * 1992-03-23 1994-07-12 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Method of producing fabric reinforcing matrix for composites
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JPH11261001A (ja) * 1998-03-13 1999-09-24 Japan Science & Technology Corp ３次元半導体集積回路装置の製造方法
JP2001007472A (ja) * 1999-06-17 2001-01-12 Sony Corp 電子回路装置およびその製造方法
JP2001189419A (ja) * 1999-12-28 2001-07-10 Mitsumasa Koyanagi ３次元半導体集積回路装置の製造方法
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
JP2001250913A (ja) * 1999-12-28 2001-09-14 Mitsumasa Koyanagi ３次元半導体集積回路装置及びその製造方法
JP2002516033A (ja) * 1997-04-04 2002-05-28 グレン ジェイ リーディ 三次元構造メモリ
JP2005109498A (ja) * 2003-09-30 2005-04-21 Internatl Business Mach Corp <Ibm> 結晶方位が異なるウェハ上に構築されたデバイス層を有する３次元ｃｍｏｓ集積回路
KR100537552B1 (ko) * 2000-07-31 2005-12-16 매그나칩 반도체 유한회사 반도체 소자 및 그의 제조 방법
JP2011159889A (ja) * 2010-02-03 2011-08-18 Renesas Electronics Corp 半導体装置およびその製造方法
JP2016106420A (ja) * 2005-08-11 2016-06-16 ジプトロニクス・インコーポレイテッド ３ｄｉｃ方法および装置
WO2019186644A1 (ja) * 2018-03-26 2019-10-03 ウルトラメモリ株式会社 半導体モジュール、半導体装置、及びその製造方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
WO2022203020A1 (ja) * 2021-03-26 2022-09-29 昭和電工マテリアルズ株式会社 半導体装置の製造方法、半導体装置、集積回路要素、及び、集積回路要素の製造方法
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
WO2024029390A1 (ja) * 2022-08-01 2024-02-08 三井化学株式会社 基板積層体の製造方法及び半導体装置
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die

Families Citing this family (354)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612799B2 (ja) * 1986-03-03 1994-02-16 三菱電機株式会社 積層型半導体装置およびその製造方法
US4829018A (en) * 1986-06-27 1989-05-09 Wahlstrom Sven E Multilevel integrated circuits employing fused oxide layers
US4771013A (en) * 1986-08-01 1988-09-13 Texas Instruments Incorporated Process of making a double heterojunction 3-D I2 L bipolar transistor with a Si/Ge superlattice
US4704785A (en) * 1986-08-01 1987-11-10 Texas Instruments Incorporated Process for making a buried conductor by fusing two wafers
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US4897676A (en) * 1988-01-05 1990-01-30 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
WO1990003044A1 (en) * 1988-09-12 1990-03-22 Microflex Technology, Inc. Protected piezoelectric polymer bimorph
US5191405A (en) * 1988-12-23 1993-03-02 Matsushita Electric Industrial Co., Ltd. Three-dimensional stacked lsi
JPH02186636A (ja) * 1989-01-12 1990-07-20 Seiko Epson Corp 集積回路装置の配線法
US5055425A (en) * 1989-06-01 1991-10-08 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5162260A (en) * 1989-06-01 1992-11-10 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5072075A (en) * 1989-06-28 1991-12-10 Digital Equipment Corporation Double-sided hybrid high density circuit board and method of making same
JPH0344067A (ja) * 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US4992059A (en) * 1989-12-01 1991-02-12 Westinghouse Electric Corp. Ultra fine line cable and a method for fabricating the same
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
GB9015820D0 (en) * 1990-07-18 1990-09-05 Raychem Ltd Processing microchips
FR2666173A1 (fr) * 1990-08-21 1992-02-28 Thomson Csf Structure hybride d'interconnexion de circuits integres et procede de fabrication.
US6143582A (en) * 1990-12-31 2000-11-07 Kopin Corporation High density electronic circuit modules
US6627953B1 (en) 1990-12-31 2003-09-30 Kopin Corporation High density electronic circuit modules
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
DE69232606T2 (de) * 1991-02-25 2004-08-05 Canon K.K. Elektrischer Verbindungskörper und Herstellungsverfahren dafür
US5212115A (en) * 1991-03-04 1993-05-18 Motorola, Inc. Method for microelectronic device packaging employing capacitively coupled connections
US5244839A (en) * 1991-06-18 1993-09-14 Texas Instruments Incorporated Semiconductor hybrids and method of making same
JPH05198739A (ja) * 1991-09-10 1993-08-06 Mitsubishi Electric Corp 積層型半導体装置およびその製造方法
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5985693A (en) * 1994-09-30 1999-11-16 Elm Technology Corporation High density three-dimensional IC interconnection
US6714625B1 (en) 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US5236871A (en) * 1992-04-29 1993-08-17 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for producing a hybridization of detector array and integrated circuit for readout
US5302842A (en) * 1992-07-20 1994-04-12 Bell Communications Research, Inc. Field-effect transistor formed over gate electrode
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US5345213A (en) * 1992-10-26 1994-09-06 The United States Of America, As Represented By The Secretary Of Commerce Temperature-controlled, micromachined arrays for chemical sensor fabrication and operation
US5464966A (en) * 1992-10-26 1995-11-07 The United States Of America As Represented By The Secretary Of Commerce Micro-hotplate devices and methods for their fabrication
US5591678A (en) * 1993-01-19 1997-01-07 He Holdings, Inc. Process of manufacturing a microelectric device using a removable support substrate and etch-stop
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
WO1995009438A1 (en) 1993-09-30 1995-04-06 Kopin Corporation Three-dimensional processor using transferred thin film circuits
JPH07201864A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 突起電極形成方法
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US5675180A (en) 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5670824A (en) * 1994-12-22 1997-09-23 Pacsetter, Inc. Vertically integrated component assembly incorporating active and passive components
DE19516487C1 (de) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration mikroelektronischer Systeme
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5818748A (en) * 1995-11-21 1998-10-06 International Business Machines Corporation Chip function separation onto separate stacked chips
US5781031A (en) * 1995-11-21 1998-07-14 International Business Machines Corporation Programmable logic array
US5824571A (en) * 1995-12-20 1998-10-20 Intel Corporation Multi-layered contacting for securing integrated circuits
JP3322575B2 (ja) * 1996-07-31 2002-09-09 太陽誘電株式会社 ハイブリッドモジュールとその製造方法
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US8018058B2 (en) * 2004-06-21 2011-09-13 Besang Inc. Semiconductor memory device
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6831361B2 (en) 1997-01-24 2004-12-14 Micron Technology, Inc. Flip chip technique for chip assembly
US6221753B1 (en) * 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
US5786238A (en) * 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5923067A (en) * 1997-04-04 1999-07-13 International Business Machines Corporation 3-D CMOS-on-SOI ESD structure and method
US6097096A (en) * 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
US6342681B1 (en) * 1997-10-15 2002-01-29 Avx Corporation Surface mount coupler device
US6110760A (en) * 1998-02-12 2000-08-29 Micron Technology, Inc. Methods of forming electrically conductive interconnections and electrically interconnected substrates
JP3625646B2 (ja) 1998-03-23 2005-03-02 東レエンジニアリング株式会社 フリップチップ実装方法
US6423614B1 (en) * 1998-06-30 2002-07-23 Intel Corporation Method of delaminating a thin film using non-thermal techniques
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6242778B1 (en) 1998-09-22 2001-06-05 International Business Machines Corporation Cooling method for silicon on insulator devices
FR2784800B1 (fr) * 1998-10-20 2000-12-01 Commissariat Energie Atomique Procede de realisation de composants passifs et actifs sur un meme substrat isolant
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US6593645B2 (en) * 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
DE19954895C2 (de) * 1999-11-15 2002-02-14 Infineon Technologies Ag Anordnung zur elektrischen Verbindung zwischen Chips in einer dreidimensional ausgeführten Schaltung
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6871396B2 (en) * 2000-02-09 2005-03-29 Matsushita Electric Industrial Co., Ltd. Transfer material for wiring substrate
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP3597754B2 (ja) * 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP3440057B2 (ja) * 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US6600173B2 (en) 2000-08-30 2003-07-29 Cornell Research Foundation, Inc. Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6593534B2 (en) 2001-03-19 2003-07-15 International Business Machines Corporation Printed wiring board structure with z-axis interconnections
US6748994B2 (en) 2001-04-11 2004-06-15 Avery Dennison Corporation Label applicator, method and label therefor
GB0112674D0 (en) * 2001-05-24 2001-07-18 Avx Ltd Manufacture of solid state electronic components
US6495396B1 (en) * 2001-08-29 2002-12-17 Sun Microsystems, Inc. Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
DE10202788A1 (de) * 2002-01-25 2003-07-31 Rieter Ag Maschf Texturieranlage und Texturierdüse hierfür
JP2003332560A (ja) * 2002-05-13 2003-11-21 Semiconductor Energy Lab Co Ltd 半導体装置及びマイクロプロセッサ
US7402897B2 (en) 2002-08-08 2008-07-22 Elm Technology Corporation Vertical system integration
JP4373063B2 (ja) 2002-09-02 2009-11-25 株式会社半導体エネルギー研究所 電子回路装置
JP4094386B2 (ja) * 2002-09-02 2008-06-04 株式会社半導体エネルギー研究所 電子回路装置
JP4035034B2 (ja) * 2002-11-29 2008-01-16 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6881975B2 (en) * 2002-12-17 2005-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6809269B2 (en) * 2002-12-19 2004-10-26 Endicott Interconnect Technologies, Inc. Circuitized substrate assembly and method of making same
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
JP3981026B2 (ja) * 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
JP4574118B2 (ja) * 2003-02-12 2010-11-04 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
JP4651924B2 (ja) * 2003-09-18 2011-03-16 シャープ株式会社 薄膜半導体装置および薄膜半導体装置の製造方法
WO2005055288A2 (de) 2003-12-03 2005-06-16 Pac Tech - Packaging Technologies Gmbh Verfahren und vorrichtung zur wechselseitigen kontaktierung von zwei wafern
DE10361521A1 (de) 2003-12-03 2005-07-07 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur wechselseitigen Kontaktierung von zwei Wafern
KR101359514B1 (ko) * 2004-01-07 2014-02-10 가부시키가이샤 니콘 적층 장치 및 집적 회로 소자의 적층 방법
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7547917B2 (en) * 2005-04-06 2009-06-16 International Business Machines Corporation Inverted multilayer semiconductor device assembly
JP4123251B2 (ja) * 2005-07-07 2008-07-23 セイコーエプソン株式会社 半導体装置製造用基板、半導体装置の製造方法
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US20070145367A1 (en) * 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
US7626257B2 (en) * 2006-01-18 2009-12-01 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7354809B2 (en) * 2006-02-13 2008-04-08 Wisconsin Alumi Research Foundation Method for double-sided processing of thin film transistors
US7670927B2 (en) * 2006-05-16 2010-03-02 International Business Machines Corporation Double-sided integrated circuit chips
US8013342B2 (en) 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US7960218B2 (en) 2006-09-08 2011-06-14 Wisconsin Alumni Research Foundation Method for fabricating high-speed thin-film transistors
US7799612B2 (en) * 2007-06-25 2010-09-21 Spansion Llc Process applying die attach film to singulated die
EP2009693A1 (fr) 2007-06-29 2008-12-31 Axalto S.A. Procédé de fabrication d'un système électronique sécurisé, dispositif de sécurisation de circuit intégré et système électronique correspondants
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
US8101996B2 (en) * 2008-04-15 2012-01-24 Fairchild Semiconductor Corporation Three-dimensional semiconductor device structures and methods
US20100075481A1 (en) * 2008-07-08 2010-03-25 Xiao (Charles) Yang Method and structure of monolithically integrated ic-mems oscillator using ic foundry-compatible processes
US9595479B2 (en) 2008-07-08 2017-03-14 MCube Inc. Method and structure of three dimensional CMOS transistors with hybrid crystal orientations
US8148781B2 (en) 2008-07-28 2012-04-03 MCube Inc. Method and structures of monolithically integrated ESD suppression device
US8140297B2 (en) * 2009-01-16 2012-03-20 International Business Machines Corporation Three dimensional chip fabrication
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8148728B2 (en) 2009-10-12 2012-04-03 Monolithic 3D, Inc. Method for fabrication of a semiconductor device and structure
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US8415238B2 (en) 2010-01-14 2013-04-09 International Business Machines Corporation Three dimensional integration and methods of through silicon via creation
US8859390B2 (en) * 2010-02-05 2014-10-14 International Business Machines Corporation Structure and method for making crack stop for 3D integrated circuits
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
FR2964112B1 (fr) * 2010-08-31 2013-07-19 Commissariat Energie Atomique Traitement avant collage d'une surface mixte cu-oxyde, par un plasma contenant de l'azote et de l'hydrogene
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8563396B2 (en) * 2011-01-29 2013-10-22 International Business Machines Corporation 3D integration method using SOI substrates and structures produced thereby
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8618647B2 (en) * 2011-08-01 2013-12-31 Tessera, Inc. Packaged microelectronic elements having blind vias for heat dissipation
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US20140042152A1 (en) * 2012-08-08 2014-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Variable frequency microwave device and method for rectifying wafer warpage
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
JP6074985B2 (ja) * 2012-09-28 2017-02-08 ソニー株式会社 半導体装置、固体撮像装置、および半導体装置の製造方法
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
SG11201600043RA (en) 2013-07-05 2016-02-26 Ev Group E Thallner Gmbh Method for bonding of contact surfaces
US9202788B2 (en) * 2013-10-02 2015-12-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
US9780075B2 (en) 2014-08-11 2017-10-03 Massachusetts Institute Of Technology Interconnect structures for assembly of multi-layer semiconductor devices
CN104332455B (zh) * 2014-09-25 2017-03-08 武汉新芯集成电路制造有限公司 一种基于硅通孔的片上半导体器件结构及其制备方法
US9881904B2 (en) 2014-11-05 2018-01-30 Massachusetts Institute Of Technology Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10134972B2 (en) 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
WO2017015432A1 (en) 2015-07-23 2017-01-26 Massachusetts Institute Of Technology Superconducting integrated circuit
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
CN115942752A (zh) 2015-09-21 2023-04-07 莫诺利特斯3D有限公司 3d半导体器件和结构
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10242968B2 (en) 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
US10121754B2 (en) 2015-11-05 2018-11-06 Massachusetts Institute Of Technology Interconnect structures and methods for fabricating interconnect structures
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US10586909B2 (en) 2016-10-11 2020-03-10 Massachusetts Institute Of Technology Cryogenic electronic packages and assemblies
US10790262B2 (en) * 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
US11081392B2 (en) * 2018-09-28 2021-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for stacked semiconductor devices
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11646314B2 (en) * 2021-04-16 2023-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacture thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400868A (en) * 1980-12-29 1983-08-30 Varian Associates, Inc. Method of making a transparent and electrically conductive bond
US4552607A (en) * 1984-06-04 1985-11-12 Advanced Technology Laboratories, Inc. Method of making electrically conductive thin epoxy bond

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272556A (ja) * 1986-05-20 1987-11-26 Fujitsu Ltd 三次元半導体集積回路装置及びその製造方法
JPH0442957A (ja) * 1990-06-06 1992-02-13 Matsushita Electron Corp 半導体集積回路装置の製造方法
JPH04132258A (ja) * 1990-09-25 1992-05-06 Nec Corp 半導体基板の接続体およびその接続方法
US5327621A (en) * 1992-03-23 1994-07-12 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Method of producing fabric reinforcing matrix for composites
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
US6972249B2 (en) 1996-09-20 2005-12-06 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
US6528894B1 (en) 1996-09-20 2003-03-04 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP2002516033A (ja) * 1997-04-04 2002-05-28 グレン ジェイ リーディ 三次元構造メモリ
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US7170185B1 (en) 1997-12-08 2007-01-30 3M Innovative Properties Company Solvent assisted burnishing of pre-underfilled solder bumped wafers for flipchip bonding
JPH11261001A (ja) * 1998-03-13 1999-09-24 Japan Science & Technology Corp ３次元半導体集積回路装置の製造方法
JP2001007472A (ja) * 1999-06-17 2001-01-12 Sony Corp 電子回路装置およびその製造方法
JP2001250913A (ja) * 1999-12-28 2001-09-14 Mitsumasa Koyanagi ３次元半導体集積回路装置及びその製造方法
JP2001189419A (ja) * 1999-12-28 2001-07-10 Mitsumasa Koyanagi ３次元半導体集積回路装置の製造方法
KR100537552B1 (ko) * 2000-07-31 2005-12-16 매그나칩 반도체 유한회사 반도체 소자 및 그의 제조 방법
JP2005109498A (ja) * 2003-09-30 2005-04-21 Internatl Business Mach Corp <Ibm> 結晶方位が異なるウェハ上に構築されたデバイス層を有する３次元ｃｍｏｓ集積回路
JP2016106420A (ja) * 2005-08-11 2016-06-16 ジプトロニクス・インコーポレイテッド ３ｄｉｃ方法および装置
JP2011159889A (ja) * 2010-02-03 2011-08-18 Renesas Electronics Corp 半導体装置およびその製造方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11552041B2 (en) 2017-09-24 2023-01-10 Adeia Semiconductor Bonding Technologies Inc. Chemical mechanical polishing for hybrid bonding
WO2019186644A1 (ja) * 2018-03-26 2019-10-03 ウルトラメモリ株式会社 半導体モジュール、半導体装置、及びその製造方法
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11955445B2 (en) 2018-06-13 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Metal pads over TSV
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11756880B2 (en) 2018-10-22 2023-09-12 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
WO2022201497A1 (ja) * 2021-03-26 2022-09-29 昭和電工マテリアルズ株式会社 半導体装置の製造方法、半導体装置、集積回路要素、及び、集積回路要素の製造方法
WO2022203020A1 (ja) * 2021-03-26 2022-09-29 昭和電工マテリアルズ株式会社 半導体装置の製造方法、半導体装置、集積回路要素、及び、集積回路要素の製造方法
WO2024029390A1 (ja) * 2022-08-01 2024-02-08 三井化学株式会社 基板積層体の製造方法及び半導体装置

Also Published As

Publication number Publication date
DE3586732D1 (de) 1992-11-12
DE3586732T2 (de) 1993-04-22
US4612083A (en) 1986-09-16
EP0168815A2 (en) 1986-01-22
EP0168815B1 (en) 1992-10-07
EP0168815A3 (en) 1988-01-20

Similar Documents

Publication Publication Date Title
JPS6130059A (ja) 半導体装置の製造方法
US4939568A (en) Three-dimensional integrated circuit and manufacturing method thereof
US6566232B1 (en) Method of fabricating semiconductor device
US3679941A (en) Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator
JP3694021B2 (ja) 半導体デバイスの製造方法
US20040235234A1 (en) Semiconductor device and method of manufacturing the same
JPH08204123A (ja) ３次元集積回路の製造方法
JPH08213549A (ja) 集積回路の製造方法
US20050179057A1 (en) System semiconductor device and method of manufacturing the same
JPS6281745A (ja) ウエハ−規模のｌｓｉ半導体装置とその製造方法
JPH08213548A (ja) ３次元集積回路の製造方法
JPS5811100B2 (ja) デンキテキパツケ−ジ
US3757175A (en) Tor chips mounted on a single substrate composite integrated circuits with coplnaar connections to semiconduc
TWI475618B (zh) 晶圓級封裝半導體之方法
CN105428329A (zh) 具有ubm的封装件和形成方法
JPH10223636A (ja) 半導体集積回路装置の製造方法
JPH05267563A (ja) 半導体装置およびその製造方法
KR100475716B1 (ko) 복합 반도체 장치의 멀티 반도체 기판의 적층 구조 및 그방법
US20030171001A1 (en) Method of manufacturing semiconductor devices
JPH0472656A (ja) マルチチップ・モジュールの製造方法
JPH0541478A (ja) 半導体装置およびその製造方法
EP1906441A1 (en) Wafer with semiconductor devices and method of manufacturing the same
JPH0845935A (ja) 多層配線の形成方法
CN112201573B (zh) 多层晶圆键合方法
JPS6091660A (ja) 半導体装置の製造方法