CN103377911B - 提高化学机械平坦化工艺均匀性的方法 - Google Patents
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Abstract
本发明提供了一种提高化学机械平坦化工艺均匀性的方法,包括以下步骤:在衬底上形成特征;在特征之间形成第一介质隔离层;平坦化第一介质隔离层,直至暴露特征,使得特征之间的第一介质隔离层具有凹陷深度;在特征以及介质隔离层上形成第二介质隔离层,降低特征之间与特征顶部第二介质隔离层的高度差;平坦化第二介质隔离层,直至暴露特征。依照本发明的提高化学机械平坦化工艺均匀性的方法,在研磨特征顶部的介质隔离层之后再次形成介质隔离层,使得特征之间与特征顶部介质层高度差有效降低,并补偿了特征的凹陷,有效提高了晶圆芯片内部的均匀性。
Description
技术领域
本发明涉及一种半导体器件的制造方法,更具体地讲,涉及一种提高化学机械平坦化工艺均匀性的方法。
背景技术
随高K/金属栅工程在45纳米技术节点上的成功应用,使其成为亚30纳米以下技术节点不可缺少的关键模块化工程。高K/金属栅分为前栅(gate first)工艺和后栅(gate last)工艺。由于后栅工艺避免了离子注入高温退火对高K/金属栅功函数的负面影响,因此目前已经成为主流工艺。目前只有坚持高K/后金属栅(gate last)路线的英特尔公司在45纳米和32纳米量产上取得了成功。近年来紧随IBM产业联盟的三星,台积电,英飞凌等业界巨头也将之前开发的重点由高K/先金属栅(gate first)转向gate last工程。
gate last工艺集成中化学机械平坦化(CMP)工艺的开发被业界认为最具挑战性。常规gate last工艺中,需采用CMP工艺将衬底1上多晶硅栅(poly gate)2顶部的氧化硅隔离层4和氮化硅隔离层3磨掉,露出多晶硅栅2的顶端后停止研磨,此步CMP工艺称为打开多晶硅栅顶部的CMP,即Poly opening nitride polish CMP,简称POPCMP,如图1A和图1B所示所示。而后去除多晶硅栅,在留下的沟槽内填充进不同的金属层5,再进行一步或多步金属层的化学机械抛光,此步CMP工艺即metal gate CMP,仅留下栅内的金属,从而最终得到高K/金属栅结构,如图2A、2B所示。
第一道POP CMP包括两个步骤的CMP,一是氧化硅的CMP,一是氮化硅的CMP。这两步CMP对晶圆芯片内部研磨均匀性(withinin die uniformity)均有着很高的要求。其中,对第一步氧化硅CMP工艺的研磨均匀性控制最为关键。由于器件密度较大,且淀积氧化硅层4前存在栅高度的落差,约1000-
这导致氧化硅淀积后多晶栅顶与源漏区的氧化硅厚度落差可达1000-
甚至更多,如图1A所示。随技术节点不断缩小,在45纳米以下,常规CMP在改善晶圆芯片内部研磨均匀性方面遇到了极大挑战。除机台硬件配置进行革新外,选择合适的研磨液和研磨垫是提高芯片内研磨均匀性的有效方法。由于涉及各家公司的技术机密,目前鲜有公开的文献或专利报道。如果采用常规氧化硅CMP技术将无法有效消除这种较大的厚度落差,这种落差会随抛光过程的进行,一直遗传到氧化硅抛光结束,这会造成多晶栅之间氧化硅大的凹陷。即使下一步氮化硅CMP也很难修复,并且由于材料选择比的不同,还可能将这种氧化硅凹陷进一步放大,如图1B所示,栅间氧化硅具有第一凹陷深度H1,例如
大的氧化硅层4的凹陷直接会给metal gate CMP工艺造成巨大障碍,极大压缩该工艺的调整空间。如图2A和图2B所示,金属层5填充了栅极凹槽的同时也残留在栅极之间的氧化硅层4的凹陷处,在后续的金属栅CMP时造成器件短路。类似地,对于其他的需要平坦化处理的特征,例如鳍形结构、多栅结构、MEMS结构等等,也存在类似的问题,特征之间的介质隔离层凹陷在后续处理过程中会遗传、放大,造成特征的失效。
为此,急需一种能有效地针对POP CMP工艺提高晶圆芯片内部研磨均匀性的方法。
发明内容
因此,本发明的目的在于提出一种提高晶圆芯片内部研磨均匀性的方法,特别是有效地针对POP CMP工艺来提高后续金属栅极CMP均匀性。。
本发明提供了一种提高化学机械平坦化工艺均匀性的方法,包括以下步骤:在衬底上形成特征;在特征之间形成第一介质隔离层;平坦化第一介质隔离层,直至暴露特征,使得特征之间的第一介质隔离层具有凹陷深度;在特征以及介质隔离层上形成第二介质隔离层,至少重新填满第一次化学机械平坦化造成的介质隔离层凹陷,从而降低特征之间与特征顶部第二介质隔离层的高度差;平坦化第二介质隔离层,直至暴露特征。
第二介质隔离层与第一介质隔离层材质相同。
其中,平坦化第一介质隔离层的步骤之后、形成第二介质隔离层之前,还包括步骤:刻蚀第一介质隔离层,增大第一介质隔离层的凹陷深度。其中,采用干法刻蚀和/或湿法刻蚀来刻蚀第一介质层。
其中,方法进一步包括:在形成特征之后、形成第一介质隔离层之前,还在特征顶部以及侧壁形成特征保护层;平坦化第一介质隔离层的步骤进一步包括,平坦化第一介质隔离层直至暴露特征顶部的特征保护层;平坦化特征顶部的特征保护层,直至暴露特征。
其中,特征包括半导体材料、绝缘材料、导电材料,半导体材料包括多晶硅、非晶硅、微晶硅及其组合,绝缘材料包括氧化硅、氮化硅、氮氧化硅、高k材料及其组合,导电材料包括金属、金属合金、金属氮化物及其组合。
其中,第一介质隔离层、第二介质隔离层、特征保护层包括氧化物、氮化物、氮氧化物及其组合。
其中,采用CMP平坦化,通过CMP设备自带的终点探测***自动停止研磨,或者通过控制研磨时间停止研磨。
依照本发明的提高化学机械平坦化工艺均匀性的方法,在研磨特征顶部的介质隔离层之后再次形成介质隔离层,使得特征之间与特征顶部介质层高度差有效降低,并补偿了特征之间介质层的凹陷,有效提高了晶圆芯片内部的均匀性。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1A和图1B显示了现有技术的后栅工艺剖视图,其中CMP氧化硅层直至暴露伪栅极;
图2A和图2B显示了现有技术的后栅工艺剖视图,其中去除伪栅极之后填充金属栅极并CMP直至暴露氮化硅层;以及
图3至图5依次显示了依照本发明的方法各步骤的剖面示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了提高化学机械平坦化工艺均匀性的方法。需要指出的是,类似的附图标记表示类似的结构。
在POP CMP工艺中,例如多晶栅的特征之间产生的例如氧化硅的介质隔离层的凹陷本质是因为结构与例如源漏区的特征之间部分的高度差造成的;即生长介质隔离层后,特征顶部介质隔离层高于特征之间介质隔离层,这不利于CMP过程对特征之间介质隔离层凹陷的控制。本申请的设计思路是通过第一次CMP平坦化以及二次生长介质层,在修复介质隔离层凹陷的基础上,大幅度降低特征顶部介质隔离层与特征间介质隔离层的高度差,并进行第二次CMP平坦化,得到特征结构;此方法可有效提高晶圆芯片内部的均匀性。
首先,形成特征和特征之间的第一介质隔离层,并进行平坦化处理,例如完成现有的POP CMP工艺,特征之间的介质隔离层具有凹陷深度。提供衬底1,依照器件电学性能需要而可采用各种衬底材料,例如包括单晶硅、绝缘体上硅(SOI)、单晶锗、绝缘体上锗(GeOI)、纳米线,或者SiGe、SiC、InSb、GaAs、GaN等其他化合物半导体材料。在衬底1上形成特征2,特征2包括但不限于伪栅极、衬底材料的鳍形结构、MEMS工艺的梁结构、刻蚀工艺中的硬掩膜中间结构、外延生长的抬升结构等等。特征2的材质包括但不限于半导体材料、绝缘材料、导电材料,半导体材料例如为多晶硅、非晶硅或微晶硅以用于伪栅极或者鳍形结构,绝缘材料例如为氧化硅、氮化硅、氮氧化硅或高k材料,导电材料例如为金属、金属合金、金属氮化物以应用于金属栅极或者金属接触塞线等。优选地,特征2是用于后栅工艺的伪栅极,为多晶硅、非晶硅或微晶硅。形成特征2的方法依照其材质不同而可以选择APCVD、LPCVD、PECVD、HDPCVD、MOCVD、ALD、溅射等各种常规沉积方法。通过先沉积后光刻/刻蚀的常规方法,在特征2顶部以及侧面上以类似的常规方法沉积形成特征保护层3,特征保护层3的材质例如为氮化硅、氮氧化硅,具有较高的硬度以及较好的刻蚀选择性,并优选具有较高的应力以便于适用于向衬底施加应力以提高MOSFET等器件的沟道区载流子迁移率。在整个器件上沉积第一介质隔离层4,其材质例如为氧化硅或氮氧化硅。在介质隔离层淀积完后,使用针对氧化物的第一介质隔离层4的第一研磨液对整片进行第一化学机械平坦化处理(氧化物的CMP,oxide CMP)。当暴露出结构顶端的特征保护层3时,通过CMP设备自带的介于摩擦力或者光学的终点探测***(endpoint)自动停止研磨。然后使用针对氮化物的特征保护层3的第二研磨液对整片晶圆进行第二化学机械平坦化处理(氮化物的CMP,nitride CMP)。磨掉特征2顶部的氮化硅材质的特征保护层3,同时也相应磨掉一部分的氧化硅材质的第一介质隔离层4;此步CMP通过终点探测或研磨时间控制来完成。研磨完成之后,特征2侧面留有特征保护层3,特征2之间的第一介质隔离层4下凹而低于特征2,特征2的高度例如为
第一介质隔离层4的第一凹陷深度H1例如为
可选地,对第一介质隔离层4进行凹陷处理(oxide recess),使得特征2之间的第一介质隔离层4具有比第一凹陷深度大的第二凹陷深度H2。
有以下3种方法可以完成此步凹陷处理工艺:
(1)使用干法刻蚀(dry etch)直接对整片晶圆进行第一介质隔离层4刻蚀。在刻蚀过程中,通过使用高选择比刻蚀气体(即刻蚀特征2、特征保护层3速率慢,而刻蚀介质隔离层4速率快),以及刻蚀时间的控制,对特征2间的第一介质隔离层4进行凹陷刻蚀;对特征2间的介质隔离层4进行凹陷刻蚀后,得到结构参见图3。刻蚀气体可包括碳氟基气体(CxHyFz)、NF3、SF6、XeF2、BrF2等含氟气体,以及Cl2、Br2、HBr、HCI等其他含卤素气体,还可以包括氧气、臭氧、氮氧化物等氧化剂,通过控制混合刻蚀气体的各个组分比例可以保证高的刻蚀选择比。
(2)使用湿法刻蚀(wet etch)直接对整片晶圆进行第一介质隔离层4刻蚀。在刻蚀过程中,通过使用高选择比刻蚀化学液(即刻蚀特征2、特征保护层3速率慢,而刻蚀介质隔离层4速率快),以及刻蚀时间、温度的控制,对特征2间的介质隔离层4进行凹陷刻蚀;对特征2间的第一介质隔离层4进行凹陷刻蚀后,得到结构参见图3。针对氧化硅材质的第一介质隔离层4,刻蚀化学液可包括稀释氢氟酸(DHF,例如2.5体积%HF水溶液)、缓释刻蚀液(BOE,1∶4的NH4F与HF混合水溶液),刻蚀温度例如25℃。
(3)使用上述的干法和湿法混合刻蚀的工艺,通过控制刻蚀时间,对特征2间的第一介质隔离层4进行凹陷刻蚀;比如先干法刻蚀,在湿法刻蚀。
以上特征2间的第一介质隔离层4进行凹陷刻蚀完成后,第一介质隔离层4具有比第一凹陷深度大的第二凹陷深度H2,例如
上述凹陷刻蚀可以有效清除特征保护层3顶部的第一介质隔离层4,以便在再次生长介质隔离层时进一步增大特征顶部与特征之间的局部高度差,特征保护层3侧壁上端部分没有第一介质隔离层4而利用氧化物生长的选择特性从而使得后续再次生长第二介质隔离层4’时能得到较大的高度差,更便于CMP平坦化。自然,如果POP CMP处理之后第一介质隔离层4的第一凹陷深度本身足够大而使得特征保护层3侧壁上端部分没有第一介质隔离层4,例如基本达到或者超过上述第二凹陷深度,则可以省略上述凹陷刻蚀处理。然后,参照图4,在整个器件上再次形成第二介质隔离层4’,使得特征顶部的第二介质隔离层4’具有凸出高度。与之前形成介质隔离层4的工艺和材质类似,在特征2顶部以及特征2之间凹陷处再次沉积生长第二介质隔离层4’,最终使得特征2之间的第一介质隔离层4凹陷被完全填满并且要高出凹陷区一小部分,同时使得特征2顶部的第二介质隔离层4’具有高于特征2的高度H3,H3例如
该H3与图1A中的高度H0相比要小得多,例如仅为图1A中高度H0的1/5~1/3。再次形成的第二介质隔离层4’可以与之前的第一介质隔离层4材质相同,也可以不同而形成层叠结构。优选地,两者材料相同以节省工序、降低制造成本。第二次重新淀积介质隔离层的目的在于修补特征之间的凹陷,修补特征保护层3顶角在CMP过程中可能造成的损伤,获得较小的特征顶部与特征之间的介质厚度落差。
最后,参照图5,对第二介质隔离层4’进行再次平坦化处理。对晶圆进行CMP处理,针对氧化物材质的第二介质隔离层4’选用合适的研磨液以及研磨垫。当暴露出特征2时,通过CMP设备自带的终点探测***自动停止研磨。最后得到的结构如图5所示,衬底1上具有多个特征2,特征2的侧壁具有特征保护层3,特征2之间具有介质隔离层4/4’,其中介质隔离层4/4’的顶部与特征2的顶部基本持平,两者的高度差例如小于
虽然以上针对衬底1、特征2、特征保护层3以及介质隔离层4/4’给出了具体的材料和形成方法,但是只要满足相邻的两者之间材料不同而具有较高的刻蚀选择比,这些材料均可以互换。例如特征保护层3是氧化物,而介质隔离层4/4’是氮化物;或者特征2是氧化物,特征保护层3是氮化物,介质隔离层4/4’是氮氧化物,等等。
依照本发明的提高化学机械平坦化工艺均匀性的方法,在研磨特征顶部的介质隔离层之后再次形成介质隔离层,一方面补偿了特征之间介质层的凹陷,另一方面降低了特征顶部与特征之间介质层的高度差,在完成第二次CMP平坦化后,可有效提高了晶圆芯片内部的均匀性。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (7)
1.一种提高化学机械平坦化工艺均匀性的方法,包括步骤:
在衬底上形成特征结构;
在特征结构顶部以及侧壁形成特征保护层;
在特征结构之间形成第一介质隔离层;
平坦化第一介质隔离层,直至暴露特征结构顶部的特征保护层,平坦化特征结构顶部的特征保护层直至暴露特征结构,使得特征结构之间的第一介质隔离层具有凹陷深度;
在特征结构以及第一介质隔离层上形成第二介质隔离层,降低特征结构之间与特征结构顶部第二介质隔离层的高度差;
平坦化第二介质隔离层,直至暴露特征结构。
2.如权利要求1的方法,其中,第二介质隔离层与第一介质隔离层材质相同。
3.如权利要求1的方法,其中,平坦化第一介质隔离层的步骤之后、形成第二介质隔离层之前,还包括步骤:刻蚀第一介质隔离层,增大第一介质隔离层的凹陷深度。
4.如权利要求3的方法,其中,采用干法刻蚀和/或湿法刻蚀来刻蚀第一介质隔离层。
5.如权利要求1~4任一项的方法,其中,特征结构的材质包括半导体材料、绝缘材料、导电材料,半导体材料包括多晶硅、非晶硅、微晶硅及其组合,绝缘材料包括氧化硅、氮化硅、氮氧化硅、高k材料及其组合,导电材料包括金属、金属合金、金属氮化物及其组合。
6.如权利要求1~4任一项的方法,其中,第一介质隔离层、第二介质隔离层、特征保护层包括氧化物、氮化物、氮氧化物及其组合。
7.如权利要求1~4任一项的方法,其中,采用CMP平坦化,通过CMP设备自带的终点探测***自动停止研磨,或者通过控制研磨时间停止研磨。
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