WO2004086628A1 - エンコーダ回路及びa/d変換回路 - Google Patents
エンコーダ回路及びa/d変換回路 Download PDFInfo
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- WO2004086628A1 WO2004086628A1 PCT/JP2003/003654 JP0303654W WO2004086628A1 WO 2004086628 A1 WO2004086628 A1 WO 2004086628A1 JP 0303654 W JP0303654 W JP 0303654W WO 2004086628 A1 WO2004086628 A1 WO 2004086628A1
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- WIPO (PCT)
- Prior art keywords
- circuit
- output
- encoder
- value
- thermometer code
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0809—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of bubble errors, i.e. irregularities in thermometer codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03M7/165—Conversion to or from thermometric code
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/165—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages in which two or more residues with respect to different reference levels in a stage are used as input signals for the next stage, i.e. multi-residue type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Definitions
- the present invention generally relates to an encoder circuit used for an A / D converter and the like, and more particularly, to an encoder circuit that converts a thermometer code into a binary code.
- AZD conversion is required to have higher performance and higher accuracy. To meet these requirements, it is necessary to reduce the occurrence of errors during AZD conversion.
- the input analog potential is input to a plurality of comparison circuits, and the corresponding reference potentials are compared with the input potential by the plurality of comparison circuits.
- the reference potentials are allocated at equal intervals from a low potential to a high potential, and the output of the comparator group is the lower comparator output, such as "0 ⁇ ⁇ ⁇ ⁇ 0 0 0 1 1 1 ⁇ ⁇ ⁇ 1 Is "1", and the output from the comparator on the way from lower to higher is "0".
- a code is called a thermometer (thermometer) code.
- thermometer code For example, exclusive OR between adjacent bits of the thermometer code is used to extract "1" only at the boundary of "0" / "1".
- the detection signal can be converted into a binary code by a subsequent switch matrix amplifier.
- the difference in clock signal delay when the comparator is operated at a high frequency due to the inherent offset variation of each comparator, the difference in clock signal delay when the comparator is operated at a high frequency, the influence of signal fluctuation due to noise, etc.
- ⁇ There may be two or more “0” Z “1” boundaries that should be originally one, such as “0 0 1 0 1 1... 1”. In such a case, a simple encoder circuit that detects the boundary of "0" / "1” and encodes it cannot cope with it and generates a code far from the original correct binary code.
- thermometer code error Even if such a thermometer code error occurs, the A / D conversion error
- Patent Document 1 An encoder circuit designed so as not to become large has been proposed (Patent Document 1).
- the exclusive OR is calculated between adjacent bits of the thermometer code. Therefore, if an error code such as "0 ' ⁇ ⁇ ⁇ 0 0 1 0 1 1' ⁇ ⁇ 1 is input, The consecutive 3 bits of the exclusive OR output become “1” as the boundary of “0” / 66 1. Next, the center “1” of the multiple “1” bits is made valid as the boundary. Finally, weight the signal with switch matrices. Finally, amplify the weighted signal with an amplifier to determine "0" / "1". And error correction.
- Patent Document 2 discloses a binary search conversion method for encoding a thermometer code.
- the thermometer code is divided into two parts at the center bit, and the location of the boundary is searched for in the code divided into two parts by "0" Z "1" of the center bit.
- Patent Literature 3 and Patent Literature 4 disclose a conversion method according to a thermometer / binary conversion formula expressed by Boolean algebra.
- Figure 1 shows the output value when a 3-bit thermometer code is input to the conventional encoder circuit.
- eight patterns are shown for the three bits of the thermometer code, including all possible “0” / "1" combinations in the event of an error.
- thermometer If an erroneous thermometer is input, there are two or more "0" / "1" boundaries, so the output encoded value will differ depending on which boundary is treated as the correct boundary. For example, in case 6 shown in Figure 1, the abnormal thermometer code [0, 1, 0] should have been correctly [0, 1, 1], or [0, 0, 0]. It cannot be determined whether it should have been [1] or [0, 0, 0]. Thus, when there are two or more "0" / "1" boundaries, there can be multiple values for the correct encode value. This is shown in Fig. 1 as “a possible value for the encoder output”.
- thermometer code when there are a plurality of “possible values as encoder outputs”, the difference between the maximum value and the minimum value is shown as “distance”. Cases 1, 5, 7, and 8 are when a valid thermometer code is entered. In this case, any conventional example generates a correct encoder output.
- Cases 3 and 6 are cases where the input thermometer code is abnormal and three candidates are possible as encoder outputs.
- the “distance” at this time is 2.
- bits 2 and 3 of the thermometer code constitute an abnormal pattern.
- bits 2 and 3 of the thermometer code must be [1, 1] or [0, 1], not [1, 0], [0, 0].
- the output values of the encoders as candidates are 3, 2, and 1, respectively.
- thermometer code of Case 3 when the thermometer code of Case 3 is input, to minimize the average distance between the encoder output value and all possible output values, the possible encoder output values 3, 2, It is preferable that the output value of the encoder be 2 as the center of 1. Similarly, in case 6: ⁇ , it is preferable to set the encoder output value to 1.
- the optimum encoder output value obtained in this way is shown in FIG. 1 as “the value to be taken as the encoder output in order to minimize the conversion error”.
- Cases 2 and 4 are cases where four patterns of candidates are possible as encoder outputs, that is, “distance” is 3.
- bit 1, bit 2, and bit 3 of the thermometer code constitute an abnormal pattern.
- the thermometer code should be [1, 1, 1], [0, 1, 1], [0,. 0, 1] or [0, 0, 0].
- the output values of the encoders listed as candidates are 3, 2, 1, and 0, respectively.
- thermometer code of Case 2 when the thermometer code of Case 2 is input, the possible output values of the encoders 3, 2, and 3 are set to minimize the average distance between the encoder output value and all possible output values. It is preferable that the output value of the encoder be 2 or 1 as the median of 1 and 0. Similarly, in case 4, it is preferable to set the output value of the encoder to 2 or 1.
- FIG. 1 what is shown as “conventional example” is the output of the encoder described in Patent Document 1, and “other conventional examples” is the output of the encoder described in Patent Documents 2 to 4. Is the output of As shown in Fig. 1, in the “conventional example”, the output may be undefined "X" depending on the case. In “other conventional examples”, the encoder output is often different from the "value to be taken as the encoder output”.
- the conventional encoder circuit does not consider all possible thermometer code combinations, and therefore cannot always minimize the error of the encoder output when an error occurs.
- an object of the present invention is to provide an encoder circuit and an AZD converter capable of minimizing an error of an encoder output for all possible thermometer code combinations.
- Patent Document 1
- Patent Document 2
- thermometer code is input, and one or a plurality of encoder values corresponding to one or a plurality of boundaries between “0” and “1” in the thermometer code are distributed.
- the logical configuration is such that the center value of the range is output as an encoded value.
- the above encoder circuit outputs an encoded value corresponding to the position of the "0" / "1" boundary for a normal thermometer code, and outputs a plurality of "0" / "” s for an abnormal thermometer code.
- the logic is configured to output the center value of the distribution range of a plurality of encoded values corresponding to the position of the 1 "boundary as a normal encode value. Therefore, all possible thermometer input patterns can be accommodated, the output does not become undefined for any input pattern, and the error of the encoder output value is always minimized. can do.
- the encoder circuit is characterized in that the number of "1" (or "0") in the thermometer code is used as an encoded output.
- the A / D converter according to the present invention includes: a comparator group that outputs a thermometer code by comparing an input analog potential with a plurality of reference potentials by a plurality of comparators; and an output from the comparator group. It is characterized in that it includes the encoder circuit that encodes the thermometer code.
- FIG. 1 is a diagram showing output values when a 3-bit thermometer code is input to a conventional encoder circuit.
- FIG. 2 is a diagram showing an example of the configuration of the first embodiment of the encoder circuit according to the present invention.
- FIG. 3 is a diagram showing a truth table of input and output for the encoder circuit of the first embodiment of FIG.
- FIG. 4 is a diagram showing an example of the configuration of a second embodiment of the encoder circuit according to the present invention.
- FIG. 5 is a diagram showing a truth table of input and output for the encoder circuit of the second embodiment of FIG.
- FIG. 6 is a diagram showing a first embodiment of the AZD conversion circuit according to the present invention.
- FIG. 7 is a diagram illustrating a second embodiment of the A / D conversion circuit according to the present invention.
- FIG. 8 is a diagram showing a third embodiment of the AZD conversion circuit according to the present invention.
- FIG. 9 is a diagram showing a truth table of an encoder circuit in which extrapolation based on the principle of the present invention is considered.
- the encoder circuit outputs an encoded value corresponding to the position of the "0" Z “1" boundary of the thermometer code output from the comparator group and the like, and "0" / If there are multiple "1" boundaries, the logic circuit is designed so that the center value of the distribution range of multiple encoder values corresponding to the positions of those boundaries is the normal encoder value. It is.
- FIG. 2 is a diagram showing an example of the configuration of the first embodiment of the encoder circuit according to the present invention.
- the encoder circuit 10 in FIG. 2 is a circuit that converts a 3-bit thermometer code into a binary value and outputs the binary value.
- the input thermometer code is 3 bits.
- the present invention is not limited to the number of bits of the input thermometer code. It may be composed of any number of bits.
- the encoder circuit 10 in Fig. 2 is an EXNOR (output inversion of the EX OR circuit) circuit 11, an AND circuit 12 and 13, a NOR circuit 14, an OR circuit 15 and 16 and an Inverter 17 is included.
- Input signals THM1 to THM3 correspond to bits 1 to 3 of the input thermometer code.
- Outputs DO and D1 are encoder outputs obtained by converting thermometer codes into binary codes.
- a circuit has been implemented. Note that the encoder circuit 10 of FIG. 2 is configured to output the larger central value when there are two central values. This need not be the larger center value, but may be configured to output the smaller center value. There is no reason why one of the larger or smaller forces is preferable to the other.
- FIG. 3 is a diagram showing an input / output truth table for the encoder circuit 10 of the first embodiment of FIG.
- the truth table in Figure 3 shows all eight "0" / "1" combinations for the three bits that make up the input thermometer code.
- the boundary of "0" / "1” exists at the position of bit 1 and the position of bit 3.
- the two encoder outputs corresponding to the position of the two "0" / "1" boundaries are 1 and 3. Therefore, the output of the encoder circuit 10 is 2 as the center value of the distribution range [1-3] of these two encoder outputs.
- the boundary of “0” Z “1” exists at the position of bit 0 and the position of bit 3.
- the determination that the position of bit 0 is a boundary is based on the idea that virtual bit 0 below bit 1 of “0” is “1”. This makes it consistent with setting the position of bit 0 as a boundary when the pattern is all zeros [0, 0, 0].
- the determination that the position of bit 3 is a boundary is based on the idea that virtual bit 4 above bit 3 which is "1" is "0”. This is consistent with setting the position of bit 3 as the boundary when the pattern is all "1" [1, 1, 1].
- the two encoder outputs corresponding to the positions of the above two “0” / “1” boundaries are 0 and 3.
- the center value of the distribution range [0-3] of these two encoder outputs is 1 or 2, but in this example, the larger center value is selected and the output of the encoder circuit 10 is set to 2.
- the boundary of “0” / “1” exists at the position of bit 0 and the position of bit 3.
- the two encoder outputs corresponding to the positions of the two “0” Z “1” boundaries are 0 and 3. Therefore, the center value of the distribution range [0-3] of these two encoder outputs is 1 or 2. In this example, the larger center value is selected and the output of the encoder circuit 10 is set to 2.
- the logic circuit that outputs the center value of the distribution range of the corresponding encode value for one or more “0” Z “1” boundaries as a normal encode code value is provided. It is realized with a simple configuration.
- This encoder circuit is a conventional circuit With the configuration, even if the thermometer / binary conversion error (encoder output error) is large, the error can be minimized.
- FIG. 4 is a diagram showing an example of the configuration of a second embodiment of the encoder circuit according to the present invention.
- the force indicated when the input thermometer code is 3 bits Any number of bits may be used as long as the thermometer code is composed of a plurality of bits.
- FIG. 5 is a diagram showing a truth table of input and output for the encoder circuit 1OA of the second embodiment of FIG.
- the truth table in Fig. 5 shows the value of counting the number of "1" in the thermometer code.
- the number of "1” in the thermometer code satisfies the condition of "value to be taken as encoder output to minimize conversion error".
- the encoder circuit 1 OA in FIG. 4 is logically designed to output the number of “1” s of the thermometer code, and thereby, one or more “0” / “1” boundary corresponding encoders are output. It implements a logic circuit that outputs the center value of the value distribution range as a normal encoder value.
- thermometer code coincides with the center value of the distribution range.
- the "0" and “1" of the thermometer code are moved to the left and right, respectively, so that the "0" / "1" boundary is virtually reduced to one. It means that it is stipulated.
- the encoder value can be determined as one output value.
- thermometer codes "1" is calculated.
- the logic circuit as the power is realized with a simple configuration. This encoder circuit can minimize the error even if the thermometer / pinary conversion error (encoder output error) is large in the conventional circuit configuration.
- FIG. 6 is a diagram showing a first embodiment of the A / D conversion circuit according to the present invention.
- the A / D conversion circuit 30 in FIG. 6 includes an encoder circuit 10 and a comparator group 31. Although the encoder circuit 10 is shown in FIG. 2, an encoder circuit 10A shown in FIG. 4 may be used instead.
- the comparator group 31 includes comparators 41 to 43. The comparators 41 to 43 receive the input analog potential V IN and also receive the corresponding reference potentials VR F1 to VRF 3 respectively. Each of the comparators 41 to 43 compares the input analog potential V IN with a corresponding reference potential, and outputs the comparison result as thermometer codes THM 1 to THM 3.
- the encoder circuit 10 encodes the thermometer codes THM1 to THM3 supplied from the comparator group 31 and outputs them as binary codes D0 and D1. At this time, the encoder circuit 10 is configured to output the center value of the distribution range of the encode value corresponding to one or a plurality of “0” / “1” boundaries as a normal encode value. It is possible to minimize the error of the thermometer code output encoder value. That is, even if there is a factor that causes an abnormality in the thermometer code such as signal fluctuation due to offset noise of the comparators 41 to 43, it is possible to obtain the AZD conversion result so as to minimize the error. it can.
- FIG. 7 is a diagram showing a second embodiment of the A / D conversion circuit according to the present invention.
- the A / D conversion circuit 50 in Fig. 7 is a sample-and-hold circuit 51 and 59, a switch circuit 52, an interpolation circuit 53, a switch control circuit 54, a comparator group 55, and an encoder circuit 56. , A comparator group 57, and an encoder circuit 58.
- the sample and hold circuit 51 includes individual sample and hold circuits 61 to 63 that sample the input voltage at a predetermined timing and then hold the sampled voltage.
- the switch circuit 52 includes switches 64 to 67 controlled by the switch control circuit 54.
- the interpolation circuit 53 includes differential amplifiers 68 and 69 for amplifying the sample voltage selected by the switch circuit 52, and a resistance ladder for capturing the same voltage.
- the comparator groups 55 and 57 may have the same configuration as the comparator group 31, and the encoder circuit 5 6 and 58 have the same configuration as the encoder circuit 10 or 1 OA.
- the A / D conversion section composed of the comparator group 5 5 and the encoder circuit 56 outputs the upper 2 bits DO 1 and DO 2 of the result of A / D conversion of the input analog potential VIN, and the comparator group 5 7
- the AZD conversion section composed of the encoder circuit 58 outputs the lower two bits DO 3 and D 04 of the AZD conversion result.
- the sample-and-hold circuit 51 samples and holds the reference potentials VRF1 to VRF3 and the input analog potential VIN.
- the magnitudes of the held reference potentials VRF1 to VRF3 and the input analog potential VIN are compared by the comparator group 55, and the higher-order binary signal DO is obtained by using the encoder circuit 56 of the present invention capable of error correction. Get 1 and ⁇ DO 2.
- the switch control circuit 54 controls the switch group of the switch circuit 52.
- the sample and hold circuit 59 samples the hold voltage of the sample and hold circuit 51 while a control signal from the comparator group 55 to the switch control circuit 54 is generated.
- the sample-and-hold circuit 59 By configuring the sample-and-hold circuit 59 to output the hold signal «] £ at the timing when the signal of the switch control circuit 54 is output, the two lines corresponding to the“ 0 ”/“ 1 ”boundary are output.
- the analog signal is transmitted from the sample and hold circuit 51 to the sampling circuit 53.
- VIN force S is located between VRF1 and VRF2
- switches 64 and 65 are controlled to connect VRF1 and VIN to differential amplifier 68
- VRF Switches 66 and 67 are controlled to connect 2 and VIN to differential amplifier 69.
- the capture circuit 53 amplifies the selected two sets of analog signals and then divides the voltage into four equal parts. To obtain the lower 2 bits (four gradations) as in the above example, the space between VRF1 and VRF2 is divided into four equal parts. The divided voltage is supplied to the comparator group 57, and the comparison operation is performed.
- the thermometer code indicating the comparison result is encoded using the error-correctable encoder circuit 58 of the present invention, thereby obtaining lower binary signals DO 3 and DO 4.
- FIG. 8 is a diagram showing a third embodiment of the AZD conversion circuit according to the present invention. 8, the same elements as those of FIG. 7 are referred to by the same numerals, and a description thereof will be omitted.
- the A / D conversion circuit 70 in FIG. 8 is composed of sump / hold circuits 71 and 77, Switch circuit 72, switch control circuit 74, comparator group 55, encoder circuit 56, comparator group 75, and encoder circuit 76.
- the sample and hold circuit 71 includes individual sample and hold circuits 81 to 85 that sample the input voltage at a predetermined timing and then hold the sampled voltage.
- the switch circuit 72 includes switches 91 to 98 controlled by the switch control circuit 74.
- the interpolation circuit 73 includes differential amplifiers 101 to 104 for amplifying the sample voltage selected by the switch circuit 72 and a resistance ladder for interpolating and extrapolating the same voltage. The output between each differential amplifier is divided by a 4 R resistor.
- each circuit for the A / D conversion circuit 70 in FIG. 8 to generate the binary code is basically the same as the operation of each circuit in the A / D conversion circuit 50 in FIG.
- the eighth A / D conversion circuit 70 even if an abnormal thermometer code is generated and erroneous upper bits DO1 and DO2 are generated, a correct encode output can be obtained. It is configured as follows.
- the interpolation / extrapolation circuit 73 is provided with an extrapolation function
- the encoder circuit 76 is configured in consideration of extrapolation.
- VRF 1 ⁇ VIN ⁇ VRF2, and that VIN is in the vicinity of VRF2.
- the sign of the output voltage of the sample-and-hold circuit 71 and the comparison result of the comparator group 55 are
- Vs4, Vs3, Vs2, Vsl, VsO One, one,-, ten, +
- thermometer code of the comparator group 55 becomes 001.
- the encoder output of the encoder circuit 56 is 1 when represented by a decimal number, and is 0 1 when represented by a binary number (DO 1, D 0 2).
- the switch control circuit 74 controls the switch circuit 72, and the input to the interpolation / extrapolation circuit 73 is as follows.
- the switch control circuit 74 sets the input Vi2 and Vi3 of the two differential amplifiers 102 and 103 in the center in the normal operation to match the plus and minus boundaries.
- the switch circuit 72 is controlled. In this example ⁇ , between VRF 2 and VRF 1, assuming that VIN is near VRF 2,
- Vc24, Vc23, Vc22, Vc21, Vc20 (one, +, +, +)
- FIG. 9 is a diagram showing a truth table of the encoder circuit 76 taking into account extraneous detection based on the principle of the present invention.
- the case of the above example corresponds to case 2, and the output of encoder circuit 76 is 3 when expressed in decimal number, and is 01 1 when expressed in binary number.
- 0100 + 0011 0111 is obtained as the output of the multi-stage A / D converter »70.
- thermometer code is normally obtained.
- thermometer code is above.
- Vs4, Vs3, Vs2, Vsl, VsO (one,-,-, ten, +)
- thermometer code of the comparator group 55 is 101 instead of 001.
- the encode output of the encoder circuit 56 is 2 when represented by a decimal number, and is 10 when represented by a binary number (DOl, D02).
- the switch control circuit 74 controls the switch circuit 72, and the input to the interpolation / trapping circuit 73 is as follows.
- Vc24, Vc23, Vc22, Vc21, Vc20 (one, one, one, one)
- ⁇ in the above example corresponds to case 10, and
- the output of path 76 is "1-1" in decimal notation, and 11 1 (binary 11) in binary notation.
- the error can be corrected by the extrapolation function in the multi-stage A / D converter 70.
- the reason that the error correction can be performed using the extrapolation circuit that can detect ⁇ 1 is that the encoder circuit according to this effort is used to minimize the thermometer Z binary conversion error (within ⁇ 1).
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2003/003654 WO2004086628A1 (ja) | 2003-03-25 | 2003-03-25 | エンコーダ回路及びa/d変換回路 |
JP2004544173A JPWO2004086628A1 (ja) | 2003-03-25 | 2003-03-25 | エンコーダ回路及びa/d変換回路 |
EP03712939A EP1610465A4 (en) | 2003-03-25 | 2003-03-25 | CODING SWITCHING AND A / D SWITCHING |
US11/057,753 US7271757B2 (en) | 2003-03-25 | 2005-02-15 | Encoder circuit and A/D conversion circuit |
US11/889,777 US7456774B2 (en) | 2003-03-25 | 2007-08-16 | Encoder circuit and A/D conversion circuit |
Applications Claiming Priority (1)
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PCT/JP2003/003654 WO2004086628A1 (ja) | 2003-03-25 | 2003-03-25 | エンコーダ回路及びa/d変換回路 |
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US11/057,753 Continuation US7271757B2 (en) | 2003-03-25 | 2005-02-15 | Encoder circuit and A/D conversion circuit |
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EP (1) | EP1610465A4 (ja) |
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US7929637B2 (en) * | 2004-06-04 | 2011-04-19 | Texas Instruments Incorporated | Method and apparatus for digital amplitude and phase modulation |
US8411793B2 (en) | 2004-08-27 | 2013-04-02 | Texas Instruments Incorporated | Digital amplitude modulation |
JP4842989B2 (ja) * | 2008-03-28 | 2011-12-21 | 株式会社アドバンテスト | プライオリティエンコーダならびにそれを利用した時間デジタル変換器、試験装置 |
US8779952B1 (en) | 2012-04-12 | 2014-07-15 | Pmc-Sierra Us, Inc. | Background calibration of threshold errors in analog to digital converters |
US8810442B1 (en) * | 2013-02-14 | 2014-08-19 | Pmc-Sierra Us, Inc. | Background calibration of aperture center errors in analog to digital converters |
US10411917B2 (en) * | 2017-12-04 | 2019-09-10 | Credo Technology Group Limited | Linear feedback equalization |
JP7119982B2 (ja) * | 2018-12-21 | 2022-08-17 | 株式会社デンソー | A/d変換回路 |
US10848166B1 (en) | 2019-12-06 | 2020-11-24 | Analog Devices International Unlimited Company | Dual mode data converter |
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2003
- 2003-03-25 JP JP2004544173A patent/JPWO2004086628A1/ja active Pending
- 2003-03-25 WO PCT/JP2003/003654 patent/WO2004086628A1/ja active Application Filing
- 2003-03-25 EP EP03712939A patent/EP1610465A4/en not_active Withdrawn
-
2005
- 2005-02-15 US US11/057,753 patent/US7271757B2/en not_active Expired - Fee Related
-
2007
- 2007-08-16 US US11/889,777 patent/US7456774B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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US20050134495A1 (en) | 2005-06-23 |
US7456774B2 (en) | 2008-11-25 |
JPWO2004086628A1 (ja) | 2006-06-29 |
US7271757B2 (en) | 2007-09-18 |
US20070285301A1 (en) | 2007-12-13 |
EP1610465A1 (en) | 2005-12-28 |
EP1610465A4 (en) | 2006-04-05 |
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