TWI258182B - High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improve breakdown voltage - Google Patents

High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improve breakdown voltage Download PDF

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TWI258182B
TWI258182B TW094140955A TW94140955A TWI258182B TW I258182 B TWI258182 B TW I258182B TW 094140955 A TW094140955 A TW 094140955A TW 94140955 A TW94140955 A TW 94140955A TW I258182 B TWI258182 B TW I258182B
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layer
stop layer
region
semiconductor device
gate
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TW094140955A
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TW200618064A (en
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Chung-I Chen
Hsin Kuan
Zhi-Cheng Chen
Rann-Shyan Yeh
Chi-Hsuen Chang
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Taiwan Semiconductor Mfg
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1258182 九、發明說明： 【發明所屬之技術領域】 本發明有關於一 有蝕刻停止層之高電 崩潰電壓。 種應用在高電壓之電晶體元件， i電日日體元件，其中韻刻停止層 而特別有關於一種具 可預防漏電流及改善 【先别技術】
管理件可在錄領域中，包括··液晶顯轉之鶴η、電源 二 電源供應斋，非揮發性記憶體、通訊電路以及控制雷跋。盆由 ’ Γ顯:r_c需要在蝴或中等電:下以驅動相關 4電路’而以南糕來驅動液晶顯示器。由於單_ 瓜而5，大部分金氧半導體電晶體中會在閘極與源極△及極區域之間 口入絶緣層’來降低通道中的垂直電場。也可將絕緣層下的漂移區域(_ 哪⑽)與·及跡區域，輯輕微雜，提供_必要的電麵度。上 籲述兩種方法可增加源極及汲極區域中的接面崩潰電屢，因此可使金氧半導 體電晶體在高電麈下(例如電壓大於5V)也可正常運作。DM〇s(d〇ubie cUd drain MOS)為一種高電壓電晶體，依其電流路徑方向可歸類為 VDMOSherticalDMOS)電晶體及 LDMOSdateralDMOS)電晶體。參照美國 專利U. S. Pat Ν0· 6468870，揭露一種具有層間介電層之ldm〇s電晶體的 製造方法。 傳統上，源極及汲極區域電性連接至層間介電層中的導電接觸窗，且 在電路結構上通常會形成—侧停止層，使後續接職細製程中不會傷 害到電路結構。U.s· Pat NO· 6630398揭露一種具有氮氧化矽蝕刻停止層之 無邊界接觸窗。U.S· Pat. NO· 6235653 及 U.S. Pat· NO. 6316348 揭露一種矽 0503-A30922TWF 5 1258182 -莫耳百分比介於約58%至62%之富矽氮氧化石夕薄膜，這種富矽之氮氧化石夕 薄膜不足以在高電壓元件應用中當作緩衝絕緣，因為富矽之氮氧化矽薄膜 會在漏電流處引發額外的漏電流。額外的漏電流路徑會在閘極至源極間引 發大量漏電流，而降低閘極氧化物的崩潰電壓。晶片可靠度測試顯示，具 有富石夕氮氧化石夕薄膜之高電壓金氧半導體電晶體無法通過G〇l(gate oxide integrating)測試，且會引發時依性汲極電流。 【發明内容】 有鑑於此，本發明的目的就在於提供一高電壓電晶體元件，具有電阻 率超過10ohm-cm之蝕刻停止層，可預防漏電流及改善崩潰電壓。 為達成上述目的，本發明提供一種高電壓電晶體元件，其製造方法包 括·提供-半導體基底；在—高電壓元件區域上形成_閘極結構；在高電 件區域及半導體基底上形成至少—擴散區域，且側面地排列於閑極結 構的側壁；在閘極結構及擴散區域上形成一侧停止層，其中侧停止層 之電阻率大於10〇hm-cm;在該鍅刻停止層上形成一層間介電層，其中至少 -接，窗穿過層間介電層及_停止層域出擴散區域。侧停止層選擇 ^ 自除富石夕但氧化石夕外的所有介電材料。 本發明之高電壓電晶體元件包括： 於一午等體基底之 r甲]極結構立々、丁守菔巷 问電塵讀區域上；至少一擴散區域，形成在該高電壓元件區域中，且 側面地鄰祕該閘極結構的側壁；—爛停止層，置麟 散區域之上，其愤侧停止層的電阻率大於胸以及_^間= 層’置於該侧壯狀上，且具枝少—接贿，料 該侧停止層。 "丨电層汉 為了讓本發明之上述和其他目的 特舉一較佳實施例，並配合所附圖示 特徵、和優點能更明顯易懂 作詳細說明如下： ，下文
0503-A30922TWF 6 1258182 f實施方式j 高賴電晶體元件，具有層間介電層及餘 介電薄縣當賴刻停止層，配置在層 /大於1销的南電阻 製程中形成接觸窗，高電阻率之__可=二=電屢元件 ?體元件中之閘極在_下運作時所產生的： γU酿”極至祕_相電翁㈣魅，並改, 知步驟大抵相同，因此本發明之高電塵 交又1 及中等籠元賴軸容。 轉“也與目祕糕元件製程 =書巾「侧停讀」是指軸麵卩錢之上並與其上之材料不 从具有減上之材料慢的被侧速率，作驗刻製程停止之指示。 在本發明部分實補巾，侧停止層為氮切⑽y)之單層結構，直中X =為原子組成_，在此皆是指SiN。不f命名法，依形成_薄膜的沈 魏程及參數薄膜實質上的成分可能為為氫。本發明其他實施例中，钱刻 停止層為-複合材料層，包括氧切及氮鱗(删)。本發㈣—實施例中， 餘刻停止層為-非富狀氮氧切層，在此是指非f ♦秘具，其中X、丫、 z為原子組成比例，在此是指非富石夕Si〇N。此外，氯也可為薄膜之組成。 如本發明說明書中所述’非富石夕是指Si〇N是指石夕原子莫耳百分比小於約 柳。例如，在本發明-實施例中非富石夕別⑽薄膜之石夕、氧及氮原子組成 比例約12 : 21 : 42 ’相較之下，傳統之高電壓元件中，非富石夕沿⑽薄膜 之矽、氧及氮原子組成比例約158 : 72 : 144。 本發明中，「南電廢電晶體元件」是指一操作電壓大於5V之M〇S電 晶體，一般在10V至80V之間。本發明可應用至多種工業，包括但不限於 南電壓應用之積體電路製造、微電子製造，光電製造，例如··液晶顯示器 0503-A30922TWF 7 1258182 之驅動IC、電源官理7〇件，電源供應器、非揮發性記憶體、通訊電路以及 控:電路。制岐，本發明提供_電壓在，至之液晶顯示器最佳 化南電壓MQS電晶體。本發明可制淺溝槽絕緣(STIM局部石夕氧化 (LOCOS)絕緣技術來製造非對稱型高刪電晶體或對稱型高電壓 MOS電曰曰體’其中问電壓购8電晶體依電流路徑方向包括譲⑺電晶體、 LDMOS電晶體以及VDMOS電晶體。 在本發明實施例中，侧停止層為一單層氮化石夕層，在另一實施例中， 蝕刻停止層為-複合層，包括一氧化石夕層及一氮化石夕層。在另一實施例 中蝕^Ητ止層為-非备含石夕之氮氧化石夕層，在此非富含石夕之氮氧化石夕是 指矽莫耳百分比低於55%。 第1圖顯示本發明一較佳實施例之非對稱型舰⑶元件，包括一半導 體基底10，較佳為- P型半導體，包括一 p型井12及一 n型井Μ，形成 在高龍元件區域中的主動區HV。半導體基底1G包括但不限树 '絕緣 層上石夕層(SOI)、絕緣層切鍺或上述之組合。形成p輕適合的推雜物包 括卿)及BF2，摻雜量約在6·0χ，至9 〇χ奶⑽細2之間。形成㈣ 井適合之摻雜物包括石申(As)、銻(Sb)以及磷(p)，其摻雜量約在6 〇χ ι〇12至 9版10 i〇ns/cm之間。在半導體基底1〇中佈植臨界電屢調整離子，形成 f界電壓調整區15。淺溝槽絕緣結構10a及議形成在半導體基底ι〇中來 定義高電壓元件主動區HV。-額外的淺溝槽絕緣結構18形成在部分主動 己中乂溝槽絶緣結構18較佳形成在]型井中並靠近沒極。 接著以習知技術形成-閘極結構’包括一閘極介電層2〇及一閑極層 22，其中有部分閘極結構形成在主動區上，部分形成在淺溝槽絕緣結構^ 之上。閘極介電層20例如是氧化石夕、氮氧化石夕、氮化石夕、高介電常數^材 料(例如k大於4)、過渡金躲化物及稀土金魏絲，可㈣知沈積技術 =成’例如.熱氧化製程及化學氣相沈積。閘極介電層2〇之厚度可視高電 壓轉技術之所需作調整。閘極層22之材料可為多晶@、非晶㈣、推雜 8
0503-A30922TWF C8 1258182 -之多晶⑪、多晶補、金屬或上述之組合，_層22之製造方法可為 氣相沈積、濺鍍或熱成長製程。 之後以輕摻雜製程在半導縣底1G巾形成—輕摻雜祕區⑽吻， 較佳為-形成在P型井中的㈣。輕摻_極區24之邊緣大抵順著閑極处 構之侧壁排列。輕摻雜製程可在能量約i至100Kev下進行，推雜量^ X妒至W 。接著赠叙嶋，附式，沿賴極的 側壁形成介電間隙壁26。介電間隙壁26的材料例如是氮化石夕、氧化石夕、氮 氧化石夕、氮化石夕及氧化石夕之間隔層或上述之組合。接著以介電間隙壁％為 遮罩’以-重摻雜製程分別在P型井及N型井中形成矿區，用來當作源極 區28及錄區3〇。源·及汲極區的邊界分別大抵順著介賴隙壁側壁的 外部排列。汲極區30形成在淺溝槽絕緣18及收之間的n型井中，並與 閘極結構間分隔出-段距離。重摻雜製程可在能量約丨至1眶^ > 摻雜量約⑽炉至L0x 10Wcm2。接著利用耐火金屬，例如：二’ 鶴、鈦、錄在閘極層22、源極區28及没極區3〇上選擇性形成—金屬石夕化 物，以降低電阻。 在半導體基底H)上沈積-侧停止層34，該侧停止層％材料選擇 自除富含石夕之氮氧化石夕之外任何介電材料。其中較特別的是，蝴亭止層 34為-電醇超㈣。化顿之高電_膜，可達職之絕緣效果以阻止 ^高電壓刊壯超過W)_魅麟關電親道。在本發明實施例 ，侧停止層34為氮化销，可_不_沈積技術進攸積，例如： «化學餘沈積、《加強辦氣相沈積。更具體絲，氮切層可藉 由S1H4、顺3、沉1此或N2之混合，例如在壓力約2〇〇mT〇iT至4_丁⑽ 之間’溫度約300至800t：下沈積約1〇〇埃至麵埃。 本發明另-實施例中，射彳停止層34包括—氧鮮層及—氮化石夕層。 =石夕層可_各種沈積技術，例如··熱氧化法、健化學氣相沈積、電 衆加強化學氣相沈積。更具體來說，氧化石夕層藉由_及N2〇兩種反應物
0503-A30922TWF 1258182 “…以《加強化學氣相沈積法沈積，另外也可糊低壓化學氣相沈 在脈度約7GG至95G°C之間沈積厚度1G至丨_埃。在本發明另—實施例中， 利用一複合侧停止層，例如··氧化魏鮮或氮切/氧切之雙層結 構’而其中氧切層及氮切層厚度之選制視實際介電需，細作適當調 整0 ° *在本us @關中，蝴停止層34為非富秒之氮氧切層，盆石夕 之莫耳百分比低於55%，可利用各種沈積技術形成，例如：低壓化學氣相
沈積、電漿加強化學氣相沈積。在一實際應用上，利用叫〇、細4、版或 nh3、n2之混合以賴加強化學氣相沈積在温度約至6崎之間，次藉 厚度約100至1000埃。 〜積 將-層間介電層36沈積在钱刻停止層34上，再以一化學機械研 程_>)進龍光。層間介電層包括但不限於：二氧化石夕、未接雜石夕酸鹽玻 璃(USG)、氟石夕玻璃(FSG)、氟化四乙基正石夕酸鹽_沉）、含石夕倍半氧烧 (HSQ)以及低介電常數材料(介電常數低於4)。層間介電層％ 3000至8000埃之間。 序厌，习隹 形成層間介電層之後，接著在層間介電層中形成複數個接觸窗弘，並 ，滿導電材料4〇以電性連接至源涵域28及汲極區域3G。接觸窗可利用 2統之微雜顺術完成’例如：在層間介電層上形成_細層，將接觸 窗圖案轉換至光阻層形成-接觸窗圖案之遮罩，進行一非等向曰性侧製 ，，將未遮蔽部分之層間介電層移除。例如，#層間介電層為未推雜石夕玻 璃或鼠魏鱗，_製料糊侧氣體包括·· 咖約10至施cm、C〇㈣至5()咖及&。隱 接著再以另-侧製程將侧停止層未遮蔽的部分移除且不傷宝到層 間介電層36及金屬魏物層32。此侧製程為—非等向性蝴，_侧
二體’例如·’ 〇2、c2f6、QFs、舰及He，在勤約1〇至獅龜蝕 刻K)至卿i此即在層齡騎36中完成接_8，並露祕臟 0503-A30922TWF 10 1258182 -極區域28、30上的金屬矽化物層32。 ♦第2圖顯示本發明實施例之非對稱型pM〇s元件之截面圖，相較於 對雛NMOS元件，形成在高電壓區域之主動區域上的非龍^生⑽， 更包括-置於N型井14及P型井12之下的N型埋層⑽训，其參 雜祕區24為-形成在N型井14中的⑼、源極區28為一形成在^ 井中的P+區、汲極區30為一形成在P型井12中的p+區。 <第3圖顯示本發明實施例之隔離型應⑽元件之截面目，相較於非 無型NMOS το件，形成在高電壓區域之主動區取上的隔離型刪⑶元件 更匕括置於P型井12及N型井14之下的n型埋層(NBL)ll，盆中、为技 區28包括一矿區施及一 P+區29b。 极 ，第4圖顯示本發明實施例之對稱型龐〇s元件之截面目，相較於非對 私型NMOS το件，形成在高電壓區域之主動區取±的對翻舰〇s元件 .包括兩個破Ρ型井12分開之Ν型井14a及14b，以及兩淺溝槽絕緣結構收 及18b、，分別形成在分開的N型井⑷及_中。靠近源極的間極結構置 於部分淺溝槽絕緣結構l8a及N型井14a的鄰近部分上。靠近沒極的閑極 結構置於部分淺溝槽絕緣18b&N型井14b鄰近的部分上。 • /帛5 ®顯示本發明實施例之對稱型PMOS元件之截關，相較於非對 稱型PMOStg件，形成在高電壓區域之主動區取上的對翻pM〇s元件 f括兩淺溝槽絕緣結構1如及18b，分別形成在分開的p型井❿及中。 靠近源極的閘極結構，置於部分淺溝槽絕緣結構版及p型井❿的鄰近 部分上。靠近汲極的閘極結構，置於部分淺溝槽絕緣娜及p型井既鄰 近的部分上。 第6圖顯示本發明實施例之非對稱型DDDM〇s電晶體之截面圖，相較 於非對稱型LDM0S電晶體，非對稱型DDDM〇s電晶體包括兩場氧化區 17a及17b t成在半導體基底中，用來定義高電壓元件區之主動區服。 昜氧化區17a及17b可以習知LOCOS絕緣技術來形成σ擴散延伸區31鄰
0503-A30922TWF 11 1258182 ’ $於靠近沒極區的間極結構，並環繞汲極區3〇以建構出雙擴散汲極區。擴 散延伸區31具有相對較大的面積及較輕微之捧雜量，而沒極區具有相對較 小的區域及相對較重的摻雜量。作為之基底，擴散延伸區域Μ為摻 雜里約6·0χ 1〇至9·〇χ 1〇i2i〇ns/cm2的ν型區域，而汲極區3〇及源極區 28為摻雜i約5·〇χ 1〇13至1〇i6i〇ns/cm2的區域。作為刚電晶 體之基底，擴散延伸區31為一掺雜量約6 〇χ 1〇!2至9 〇χ的⑽/^的p 型區域’而没極30及源極區28為摻雜量約5·0χ 1013至l.〇x 10i6i〇ns/cm2 的P+區域。 籲帛7圖顯示本發明實施例之對稱型DDDMOS t晶體之截面圖，相較於 非對稱型DDDMOS電晶體，對翻DDDM〇S電晶體包括兩_之擴散延 伸I 31a及31b，η於兩場氧化區i7a及17b之間。擴散延伸區31a鄰近於 靠近源極端的閘極結構，並環繞源極區28形成一雙擴散源極區。另一對稱 •的擴散延伸區31b，鄰近於靠近汲極區之閘極結構並環繞汲極區3〇，形成 一雙擴散汲極區。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與 φ 潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為本發明實施例中非對稱型_〇3元件之截面圖。 第2圖為本發明實施例中非對稱型PMOS元件之截面圖。 第3圖為本發明實施例中隔離型NMOS元件之截面圖。 第4圖為本發明實施例中隔離型PM〇s元件之截面圖。 第5圖為本發明實施例中對稱型PM〇S元件之截面圖。 第6圖為本發明實施例中非對稱型DDDMQS電晶體之截面圖。 第7圖為本發明實施例中對稱型DDDMOS電晶體之截面爵。
0503-A30922TWF 12 (β 1258182 【主要元件符號說明】 半導體基底〜10 ; N 型井〜14、14a、14b、14c ; 淺溝槽絕緣結構〜16a、16b ; 淺溝槽絕緣結構〜18、18a、18b ; 閘極〜22 ; 介電間隙壁〜26 ; 矿區〜29a ; >及極區^30， 金屬碎化物層〜32 ; 層間介電層〜36 ; 金屬材料〜40。 P型井〜12 ; 臨界電壓調整區〜15 ; 場氧化區〜17a、17b ; 閘極介電層〜20 ; 輕掺雜没極區〜24 ; 源極區〜28， P+區〜29b ; 擴散延伸區〜31、31a、31b ; #刻停止層〜34 ; 接觸窗〜38 ;
0503-A30922TWF 13

Claims (1)

  1. 〇9mt
    郭摩3修正本 修正日期·· 95.5.10 十、申請專利範圍： 1·一種半導體元件，包括： 一閘極結構’置於—半導體基底之—高電壓元件區域上； 極結::：酬’形成在該高電壓元件區域申’且橫向地鄰近™ 一_停止層，置於該閘極結構及該擴散區域之上，其中該_停止 層的電阻率大於10ohm-cm ;以及 ▲ -層間介電層，置於該細停止層之上，且具有至少—接觸窗， 5亥層間介電層及該蝕刻停止層。 2_如申請專利範圍第丨項所述之半導體元件，其中該侧停止層選擇自 除矽莫耳百分比超過55%之氮氧化矽外的所有介電材料。 3·如申請專利細第丨項所述之轉體树，其中該侧停止層為一氮 化梦層。 尸4.如申請專利範圍第！項所述之半導體元件，其中紐刻停止層包括一 氧化矽層及一氮化矽層。 5·如申請專利範圍第i項所述之半導體元件，其中舰刻停止層為一石夕 莫耳百分比低於55%之氮氧化矽層。 6.如申請專利範圍第i項所述之半導體元件，其中更包括_金屬石夕化物 層’置於該擴散區域之上，其中接觸窗穿過該層間介電層及該爛停止層， 以露出該金屬矽化物層。 曰 、7.如申請專利細f !項所述之半導體元件，其中更包括兩絕緣區，形 成在該半導體基底中，來定義該高電壓元件區域。 8. 如申請專織E第1項所述之半導體元件，其巾該閘極結構包括.一 閘極介電層’置於該半導體基底之上；以及1極，置於·極介電層之 上。 9. 如申請專利範圍第8項所述之半導體元件，其中該閘極結構包括：一 14 0503-A30922TWF1 1258182 m 〜 介電間隙壁，形成在該閘極介電層及該閘極的侧壁上；以及其中該擴散區 域大抵對位於該介電間隙壁的侧壁外圍排列。 10·如申請專利範圍帛1項所述之半導體元件，其中該接觸窗填滿一導 電材料以電性連接至該擴散區域。 、 11.如申請專利範圍第！項所述之半導體元件，其中該半導體元件為一 操作電壓超過5V之高電壓電晶體。 …
    12·—種半導體元件之製造方法，包括下列步驟： &供一半導體基底，具有一高電壓元件區域； 形成一閘極結構於該高電壓元件區域上； 其中該擴散區域橫向地 在该南電壓元件區域中形成至少一擴散區域 鄰近於該閘極結構的側壁； 層，其中該钱刻停止層 在該閘極結構及該擴散區域上形成一钱刻停止 之電阻率大於10ohm-cm ; 在該钱刻停止層上形成一層間介電層；以及 在該層間介電層中形成至，接職，穿過該_介電層及該餘刻停 其中該蝕刻 電材料。 13. 如申請專利範圍第12項所述之半導體元件之製造方法， 停止層選擇自除石夕莫耳百分比超過％%之氮氧化石夕外的所有介 14. 如申請翻綱第12項所述之半導體元件之製造 停止層為-氮切層。 ，、中该蝕刻 ，其中該蝕刻 ’其中該餘刻 ^ 15.如申請專利範圍第12項所述之半導體元件之製造方法 停止層包括一氧化矽層及一氮化矽層。 16·如申請專利範圍第12項所述之半導體元件之製造方法 停止層為一矽莫耳百分比低於55%之氮氧化矽層。 0503-A30922TWF1 15 1258182 - 18.如申請專利範圍第17項所述之半導體元件之製造方法，其中該接觸 窗穿過該層間介電層及該钱刻停止層，以露出該擴散區域。 ， 19.如申請專利範圍第12項所述之半導體元件之製造方法，其中更包 括：在該半導體基底上形成兩絕緣區域，來定義該高電壓元件區域。 20.如申請專利範圍第12項所述之半導體元件之製造方法，其中更包 括：將該接觸窗填滿一導電材料，以電性連接至該擴散區域。
    0503-A30922TWF1 16
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