JP4331690B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4331690B2 JP4331690B2 JP2004571319A JP2004571319A JP4331690B2 JP 4331690 B2 JP4331690 B2 JP 4331690B2 JP 2004571319 A JP2004571319 A JP 2004571319A JP 2004571319 A JP2004571319 A JP 2004571319A JP 4331690 B2 JP4331690 B2 JP 4331690B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- region
- gate electrode
- depth
- acceleration energy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000012535 impurity Substances 0.000 claims description 84
- 238000005468 ion implantation Methods 0.000 claims description 63
- 230000001133 acceleration Effects 0.000 claims description 56
- 150000002500 ions Chemical class 0.000 claims description 43
- 238000009826 distribution Methods 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 238000005280 amorphization Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000013078 crystal Substances 0.000 description 13
- 230000008859 change Effects 0.000 description 12
- 230000035515 penetration Effects 0.000 description 12
- 230000002159 abnormal effect Effects 0.000 description 11
- 230000007423 decrease Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 230000005465 channeling Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000013074 reference sample Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- -1 Phosphorus ions Chemical class 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XQMTUIZTZJXUFM-UHFFFAOYSA-N tetraethoxy silicate Chemical compound CCOO[Si](OOCC)(OOCC)OOCC XQMTUIZTZJXUFM-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004335 scaling law Methods 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本発明の他の目的は、高さを制限したゲート電極にイオン注入される不純物のゲート絶縁膜突き抜けを抑制しつつ、ソース/ドレイン領域の接合面を深く形成することが可能な半導体装置の製造方法を提供することである。
本発明のさらに他の目的は、閾値変動が少なく、ソース/ドレイン領域の寄生容量を小さく、リーク電流を小さくすることのできる半導体装置の製造方法を提供することである。
本発明の1観点によれば、
(a)第1導電型の第1の深さのウェルと、前記ウェル内の第1の深さより浅い第1導電型の第2の深さの閾値調整領域とを有する半導体基板を準備する工程と、
(b)前記半導体基板上にゲート絶縁膜を介して、多結晶シリコン層からなるゲート電極を形成する工程と、
(c)前記ゲート電極を形成した後、前記半導体基板に浅い低抵抗領域を実現する第1のドーズ量、第1の加速エネルギで、第2導電型の不純物をイオン注入し、前記ゲート電極両側の半導体基板内にエクステンション領域を形成する工程と、
(d)前記エクステンション領域を形成した後、前記ゲート電極の側壁上に、サイドウォールスペーサを形成する工程と、
(e)前記サイドウォールスペーサを形成した後、前記第1の加速エネルギより高い第2の加速エネルギと、第2のドーズ量で、第2導電型の不純物をイオン注入し、前記第2の深さより深い第3の深さの接合を形成するソース/ドレイン領域を形成する工程と、
(f)前記ソース/ドレイン領域を形成する工程を行った後、前記半導体基板にイオンを注入し、前記ゲート電極の上層と前記ソース/ドレイン領域の上層をアモルファス化する工程と、
(g)前記アモルファス化する工程を行った後、第3の加速エネルギ、前記第2のドーズ量より高い第3のドーズ量で、第2導電型の不純物をイオン注入し、前記ソース/ドレイン領域内に高濃度領域を形成すると同時に、前記ゲート電極の多結晶シリコン層に高濃度領域を形成する工程と、
(h)前記高濃度領域を形成した後、イオン注入した不純物を活性化する工程と、
を含み、
前記工程(a)は、前記半導体基板の深さ方向に2つのピークとその間の第1の極小値を有する第1導電型不純物の濃度分布を形成し、前記工程(e)は、前記第1の極小値からその2倍の濃度までの深さに接合を形成する工程であり、
前記工程(e)は、前記ゲート電極下のチャネル領域の閾値を実質的に変更しない条件で行なう工程である半導体装置の製造方法
が提供される。
本発明の他の観点によれば、
前記工程(a)において準備する半導体基板が、第2導電型の第4の深さの他のウェルと、前記他のウェル内の第4の深さより浅い第5の深さの、第2導電型の閾値調整領域とを有し、前記工程(b)が前記他のウェル上にもゲート絶縁膜を介して多結晶シリコン層からなる他のゲート電極を形成し、
(c1)前記ゲート電極を形成した後、かつ前記サイドウォールスペーサを形成する前に、前記他のウェルに浅い低抵抗領域を実現する第4のドーズ量、前記他のゲート電極下の絶縁膜を突き抜けない第4の加速エネルギで、第1導電型の不純物をイオン注入し、前記他のゲート電極両側の他のウェル内にエクステンション領域を形成する工程と、
(e1)前記サイドウォールスペーサを形成した後、かつ前記アモルファス化する工程の前に、第5のドーズ量、前記第4の加速エネルギより高い第5の加速エネルギで、第1導電型の不純物をイオン注入し、前記他のウェル内に前記第4の深さより浅く、前記第5の深さより深い第6の深さの接合を形成する他のソース/ドレイン領域を形成する工程と、
(g1)前記アモルファス化する工程を行った後、第6の加速エネルギ、前記第5のドーズ量より高い第6のドーズ量で、第1導電型の不純物をイオン注入し、前記他のソース/ドレイン領域内に高濃度領域を形成すると同時に前記他のゲート電極の多結晶シリコン層に高濃度領域を形成する工程と、
をさらに含み、前記工程(d)は、前記他のゲート電極の側壁上にもサイドウォールスペーサを形成し、前記工程(f)は、前記他のゲート電極の上層、前記他のウェルの上層もアモルファス化し、前記工程(h)は、前記他のウェルの不純物も活性化し、
前記工程(a)は、前記他のウェル内に、前記半導体基板の深さ方向に2つのピークとその間の第2の極小値を有する第2導電型不純物の濃度分布を形成し、前記工程(e1)は、前記他のウェル内に、前記第2の極小値からその2倍の濃度までの深さに接合を形成する工程であり、
前記工程(e1)は、前記他のゲート電極下のチャネル領域の閾値を実質的に変更しない条件で行なう工程である上記に記載の半導体装置の製造方法
が提供される。
FIG.2A〜2Cは、FIG.1A〜1Lに示した工程で作成した半導体装置の特性を説明するためのグラフである。
FIG.3A、3Bは、イオン注入におけるパラメータ選択の基準を説明するためのグラフである。
FIGs.4A、4Bは、従来技術による短チャネルMOSトランジスタの構成を説明するための概略断面図である。
FIGs.5A、5Bは、単結晶シリコンと多結晶シリコンに対するイオン注入の特性を説明するためのグラフである。
これは、pn接合がウエルの深い位置から次第に不純物濃度分布の極小点Min(w)に近づいていることを示す。図においては、ドーズ量1×1013cm−2近傍で容量Cjは極小値を示す。
Claims (7)
- (a)第1導電型の第1の深さのウェルと、前記ウェル内の第1の深さより浅い第1導電型の第2の深さの閾値調整領域とを有する半導体基板を準備する工程と、
(b)前記半導体基板上にゲート絶縁膜を介して、多結晶シリコン層からなるゲート電極を形成する工程と、
(c)前記ゲート電極を形成した後、前記半導体基板に浅い低抵抗領域を実現する第1のドーズ量、第1の加速エネルギで、第2導電型の不純物をイオン注入し、前記ゲート電極両側の半導体基板内にエクステンション領域を形成する工程と、
(d)前記エクステンション領域を形成した後、前記ゲート電極の側壁上に、サイドウォールスペーサを形成する工程と、
(e)前記サイドウォールスペーサを形成した後、前記第1の加速エネルギより高い第2の加速エネルギと、第2のドーズ量で、第2導電型の不純物をイオン注入し、前記第2の深さより深い第3の深さの接合を形成するソース/ドレイン領域を形成する工程と、
(f)前記ソース/ドレイン領域を形成する工程を行った後、前記半導体基板にイオンを注入し、前記ゲート電極の上層と前記ソース/ドレイン領域の上層をアモルファス化する工程と、
(g)前記アモルファス化する工程を行った後、第3の加速エネルギ、前記第2のドーズ量より高い第3のドーズ量で、第2導電型の不純物をイオン注入し、前記ソース/ドレイン領域内に高濃度領域を形成すると同時に、前記ゲート電極の多結晶シリコン層に高濃度領域を形成する工程と、
(h)前記高濃度領域を形成した後、イオン注入した不純物を活性化する工程と、
を含み、
前記工程(a)は、前記半導体基板の深さ方向に2つのピークとその間の第1の極小値を有する第1導電型不純物の濃度分布を形成し、前記工程(e)は、前記第1の極小値からその2倍の濃度までの深さに接合を形成する工程であり、
前記工程(e)は、前記ゲート電極下のチャネル領域の閾値を実質的に変更しない条件で行なう工程である半導体装置の製造方法。 - 前記第3の加速エネルギは、前記第2の加速エネルギより低い請求項1記載の半導体装置の製造方法。
- 前記工程(f)で用いる原子がGeである請求項1記載の半導体装置の製造方法。
- 前記第2導電型の不純物がBであり、前記第1の加速エネルギは、0.3eV〜0.5eVの範囲である請求項1記載の半導体装置の製造方法。
- 前記第2導電型の不純物がBであり、前記第2の加速エネルギは、6eV〜10eVの範囲であり、前記第2のドーズ量は1x1012cm−2〜1x1014cm−2の範囲である請求項1記載の半導体装置の製造方法。
- 前記第2導電型の不純物がBであり、前記第3の加速エネルギは、2keV〜5keVの範囲、前記第3のドーズ量は、1x1015cm−2〜8x1015cm−2の範囲である請求項1記載の半導体装置の製造方法。
- 前記工程(a)において準備する半導体基板が、第2導電型の第4の深さの他のウェルと、前記他のウェル内の第4の深さより浅い第5の深さの、第2導電型の閾値調整領域とを有し、前記工程(b)が前記他のウェル上にもゲート絶縁膜を介して多結晶シリコン層からなる他のゲート電極を形成し、
(c1)前記ゲート電極を形成した後、かつ前記サイドウォールスペーサを形成する前に、前記他のウェルに浅い低抵抗領域を実現する第4のドーズ量、前記他のゲート電極下の絶縁膜を突き抜けない第4の加速エネルギで、第1導電型の不純物をイオン注入し、前記他のゲート電極両側の他のウェル内にエクステンション領域を形成する工程と、
(e1)前記サイドウォールスペーサを形成した後、かつ前記アモルファス化する工程の前に、第5のドーズ量、前記第4の加速エネルギより高い第5の加速エネルギで、第1導電型の不純物をイオン注入し、前記他のウェル内に前記第4の深さより浅く、前記第5の深さより深い第6の深さの接合を形成する他のソース/ドレイン領域を形成する工程と、
(g1)前記アモルファス化する工程を行った後、第6の加速エネルギ、前記第5のドーズ量より高い第6のドーズ量で、第1導電型の不純物をイオン注入し、前記他のソース/ドレイン領域内に高濃度領域を形成すると同時に前記他のゲート電極の多結晶シリコン層に高濃度領域を形成する工程と、
をさらに含み、前記工程(d)は、前記他のゲート電極の側壁上にもサイドウォールスペーサを形成し、前記工程(f)は、前記他のゲート電極の上層、前記他のウェルの上層もアモルファス化し、前記工程(h)は、前記他のウェルの不純物も活性化し、
前記工程(a)は、前記他のウェル内に、前記半導体基板の深さ方向に2つのピークとその間の第2の極小値を有する第2導電型不純物の濃度分布を形成し、前記工程(e1)は、前記他のウェル内に、前記第2の極小値からその2倍の濃度までの深さに接合を形成する工程であり、
前記工程(e1)は、前記他のゲート電極下のチャネル領域の閾値を実質的に変更しない条件で行なう工程である請求項1記載の半導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/005560 WO2004097942A1 (ja) | 2003-04-30 | 2003-04-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2004097942A1 JPWO2004097942A1 (ja) | 2006-07-13 |
JP4331690B2 true JP4331690B2 (ja) | 2009-09-16 |
Family
ID=33398148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004571319A Expired - Fee Related JP4331690B2 (ja) | 2003-04-30 | 2003-04-30 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7135393B2 (ja) |
JP (1) | JP4331690B2 (ja) |
WO (1) | WO2004097942A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3975099B2 (ja) * | 2002-03-26 | 2007-09-12 | 富士通株式会社 | 半導体装置の製造方法 |
US7952118B2 (en) * | 2003-11-12 | 2011-05-31 | Samsung Electronics Co., Ltd. | Semiconductor device having different metal gate structures |
TWI270180B (en) * | 2004-06-21 | 2007-01-01 | Powerchip Semiconductor Corp | Flash memory cell and manufacturing method thereof |
JP4890773B2 (ja) * | 2005-03-07 | 2012-03-07 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP4241856B2 (ja) * | 2006-06-29 | 2009-03-18 | 三洋電機株式会社 | 半導体装置および半導体装置の製造方法 |
US7651915B2 (en) | 2006-10-12 | 2010-01-26 | Infineon Technologies Ag | Strained semiconductor device and method of making same |
JP4299866B2 (ja) * | 2007-03-02 | 2009-07-22 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US7759207B2 (en) * | 2007-03-21 | 2010-07-20 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system employing stress memorization transfer |
KR100877673B1 (ko) * | 2007-06-26 | 2009-01-08 | 주식회사 동부하이텍 | 반도체 소자 제조방법 |
KR100865556B1 (ko) * | 2007-06-29 | 2008-10-28 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
US10553494B2 (en) * | 2016-11-29 | 2020-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Breakdown resistant semiconductor apparatus and method of making same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62120082A (ja) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH04283966A (ja) * | 1991-03-12 | 1992-10-08 | Nippon Steel Corp | Mos型半導体装置の製造方法 |
JP3714995B2 (ja) | 1995-07-05 | 2005-11-09 | シャープ株式会社 | 半導体装置 |
JPH09260649A (ja) * | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3871376B2 (ja) | 1996-07-08 | 2007-01-24 | 松下電器産業株式会社 | Mis半導体装置の製造方法 |
JPH11186188A (ja) * | 1997-12-19 | 1999-07-09 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
US5976923A (en) * | 1998-12-08 | 1999-11-02 | United Microelectronics Corp. | Method for fabricating a high-voltage semiconductor device |
JP4068746B2 (ja) * | 1998-12-25 | 2008-03-26 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6894353B2 (en) * | 2002-07-31 | 2005-05-17 | Freescale Semiconductor, Inc. | Capped dual metal gate transistors for CMOS process and method for making the same |
AU2003236078A1 (en) * | 2003-04-10 | 2004-11-04 | Fujitsu Limited | Semiconductor device and its manufacturing method |
JP2005005406A (ja) * | 2003-06-10 | 2005-01-06 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
US7301185B2 (en) * | 2004-11-29 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage |
-
2003
- 2003-04-30 JP JP2004571319A patent/JP4331690B2/ja not_active Expired - Fee Related
- 2003-04-30 WO PCT/JP2003/005560 patent/WO2004097942A1/ja active Application Filing
-
2005
- 2005-05-02 US US11/118,370 patent/US7135393B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20050191831A1 (en) | 2005-09-01 |
US7135393B2 (en) | 2006-11-14 |
JPWO2004097942A1 (ja) | 2006-07-13 |
WO2004097942A1 (ja) | 2004-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6551871B2 (en) | Process of manufacturing a dual gate CMOS transistor | |
JP3523151B2 (ja) | Mosトランジスタの製造方法 | |
US5985726A (en) | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET | |
JP5283827B2 (ja) | 半導体装置の製造方法 | |
US7344985B2 (en) | Nickel alloy silicide including indium and a method of manufacture therefor | |
US7211516B2 (en) | Nickel silicide including indium and a method of manufacture therefor | |
US7135393B2 (en) | Semiconductor device manufacture method capable of supressing gate impurity penetration into channel | |
US6184097B1 (en) | Process for forming ultra-shallow source/drain extensions | |
US5933741A (en) | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors | |
US6355955B1 (en) | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation | |
US8044470B2 (en) | Semiconductor device and method of fabricating the same | |
US8084338B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2007005575A (ja) | 半導体装置およびその製造方法 | |
US20130026565A1 (en) | Low rdson resistance ldmos | |
US10446645B2 (en) | Semiconductor device and method of manufacturing the same | |
TW200414321A (en) | Method for fabricating semiconductor device | |
CN110098146B (zh) | 半导体器件及其形成方法 | |
US20060189085A1 (en) | Method of forming dual polysilicon gate of semiconductor device | |
JP2006156954A (ja) | 半導体装置の製造方法 | |
JP2004253778A (ja) | 半導体装置及びその製造方法 | |
JP3946910B2 (ja) | 半導体装置の製造方法 | |
JP5499804B2 (ja) | 半導体装置の製造方法 | |
KR20050008884A (ko) | 엔모스 트랜지스터의 제조 방법 | |
JP2002094053A (ja) | 半導体装置の製造方法 | |
KR20130103061A (ko) | 반도체 장치 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090120 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090318 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090428 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090519 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090616 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090618 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4331690 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120626 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120626 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120626 Year of fee payment: 3 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120626 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120626 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130626 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140626 Year of fee payment: 5 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |