TW367613B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
TW367613B
TW367613B TW086115333A TW86115333A TW367613B TW 367613 B TW367613 B TW 367613B TW 086115333 A TW086115333 A TW 086115333A TW 86115333 A TW86115333 A TW 86115333A TW 367613 B TW367613 B TW 367613B
Authority
TW
Taiwan
Prior art keywords
circuit
delay
input buffer
buffer circuit
semiconductor integrated
Prior art date
Application number
TW086115333A
Other languages
English (en)
Inventor
Youji Idei
Masakazu Aoki
Hiromasa Noda
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Application granted granted Critical
Publication of TW367613B publication Critical patent/TW367613B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Semiconductor Memories (AREA)
TW086115333A 1996-11-11 1997-10-17 Semiconductor integrated circuit device TW367613B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31422596A JP3607439B2 (ja) 1996-11-11 1996-11-11 半導体集積回路装置

Publications (1)

Publication Number Publication Date
TW367613B true TW367613B (en) 1999-08-21

Family

ID=18050798

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115333A TW367613B (en) 1996-11-11 1997-10-17 Semiconductor integrated circuit device

Country Status (4)

Country Link
US (2) US5955905A (zh)
JP (1) JP3607439B2 (zh)
KR (1) KR100499817B1 (zh)
TW (1) TW367613B (zh)

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US9488530B2 (en) * 2013-10-23 2016-11-08 National Kaohsiung First University Of Science And Technology Time-domain temperature sensing system with a digital output and method thereof
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Also Published As

Publication number Publication date
US5955905A (en) 1999-09-21
JPH10144074A (ja) 1998-05-29
KR19980042247A (ko) 1998-08-17
KR100499817B1 (ko) 2005-11-03
JP3607439B2 (ja) 2005-01-05
US6128248A (en) 2000-10-03

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MM4A Annulment or lapse of patent due to non-payment of fees