KR860003551A - 기 억 회 로 - Google Patents

기 억 회 로 Download PDF

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Publication number
KR860003551A
KR860003551A KR1019850007172A KR850007172A KR860003551A KR 860003551 A KR860003551 A KR 860003551A KR 1019850007172 A KR1019850007172 A KR 1019850007172A KR 850007172 A KR850007172 A KR 850007172A KR 860003551 A KR860003551 A KR 860003551A
Authority
KR
South Korea
Prior art keywords
data
memory
memory device
stored
stores
Prior art date
Application number
KR1019850007172A
Other languages
English (en)
Other versions
KR910000365B1 (ko
Inventor
고오이찌 기무라 (외 4)
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59208266A external-priority patent/JPS6187194A/ja
Priority claimed from JP60105850A external-priority patent/JPS61264453A/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌 세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR860003551A publication Critical patent/KR860003551A/ko
Application granted granted Critical
Publication of KR910000365B1 publication Critical patent/KR910000365B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Image Processing (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음

Description

기 억 회 로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제15도는 본원 발명의 일실시예를 설명하기 위한 도면.
제16도는 본원 발명의 상세한 동작논리를 설명하기 위한 도면.
제17도는 본원 발명의 일실시예를 나타낸 회로도.

Claims (1)

  1. 테이터의 판독, 기입과 보존이 임의로 이루어지는 기억소자에 있어서, 외부로부터의 제1의 데이터와 이기억소자내의 제2의 데이터에 따라서 이 제1의 데이터를 기억소자에 기억시키는 통상적인 기입모우드와, 이 제1의 데이터와 이 제2의 데이터의 논리연산결과의 데이터를 이 기억소자에 기억시키는 논리연산보우드와, 이 제1의 데이터와 이 제2의 데이터의 산술연산결과의 데이터를 이 기억소자에 기억시키는 산술연산모우드를 취할 수 있는 제어회로를 설치한 것을 특징으로 하는 기억회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019850007172A 1984-10-05 1985-09-28 기억회로 KR910000365B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP84-208266 1984-10-05
JP59208266A JPS6187194A (ja) 1984-10-05 1984-10-05 記憶回路
JP85-105850 1985-05-20
JP60105850A JPS61264453A (ja) 1985-05-20 1985-05-20 記憶回路

Publications (2)

Publication Number Publication Date
KR860003551A true KR860003551A (ko) 1986-05-26
KR910000365B1 KR910000365B1 (ko) 1991-01-24

Family

ID=26446079

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850007172A KR910000365B1 (ko) 1984-10-05 1985-09-28 기억회로

Country Status (3)

Country Link
US (2) US4868781A (ko)
KR (1) KR910000365B1 (ko)
CN (1) CN1006586B (ko)

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US6028795A (en) * 1985-09-24 2000-02-22 Hitachi, Ltd. One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation
US5450342A (en) * 1984-10-05 1995-09-12 Hitachi, Ltd. Memory device
US5923591A (en) * 1985-09-24 1999-07-13 Hitachi, Ltd. Memory circuit
US5448519A (en) * 1984-10-05 1995-09-05 Hitachi, Ltd. Memory device
US5631980A (en) * 1985-03-20 1997-05-20 Canon Kabushiki Kaisha Image processing apparatus for processing image data representative of an image in accordance with the type of processing designated by a designating means
US5265234A (en) * 1985-05-20 1993-11-23 Hitachi, Ltd. Integrated memory circuit and function unit with selective storage of logic functions
JPH01163803A (ja) * 1987-12-21 1989-06-28 Fanuc Ltd 組合せ形状定義方式
US5274364A (en) * 1989-01-09 1993-12-28 Industrial Technology Research Institute Window clipping method and device
US5276781A (en) * 1989-07-12 1994-01-04 Ricoh Company, Ltd. Laser printer controller flexible frame buffer architecture which allows hardware assisted memory erase
GB2266037B (en) * 1992-03-13 1996-02-14 Quantel Ltd An electronic video processing system
CA2093448C (en) * 1992-07-17 1999-03-09 Albert D. Edgar Expert system for image enhancement
JPH06130937A (ja) * 1992-10-21 1994-05-13 Mitsubishi Electric Corp 画面表示装置
JPH06282643A (ja) * 1993-03-29 1994-10-07 Matsushita Electric Ind Co Ltd 画像合成効果装置
JP3496100B2 (ja) * 1994-12-09 2004-02-09 株式会社ルネサステクノロジ 画面表示回路
US8850137B2 (en) * 2010-10-11 2014-09-30 Cisco Technology, Inc. Memory subsystem for counter-based and other applications

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US3546680A (en) * 1968-05-01 1970-12-08 Massachusetts Inst Technology Parallel storage control system
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US3984670A (en) * 1975-03-26 1976-10-05 Fairchild Camera And Instrument Corporation Expandable digital arithmetic logic register stack
JPS5220735A (en) * 1975-08-08 1977-02-16 Hitachi Ltd Microprogram controlled computer system
US4099231A (en) * 1975-10-01 1978-07-04 Digital Equipment Corporation Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
JPS5339A (en) * 1976-06-24 1978-01-05 Mitsubishi Electric Corp Trouble detector for calculator structure
US4080651A (en) * 1977-02-17 1978-03-21 Xerox Corporation Memory control processor
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
US4302809A (en) * 1978-06-29 1981-11-24 Burroughs Corporation External data store memory device
JPS56140390A (en) * 1980-04-04 1981-11-02 Nippon Electric Co Picture memory
US4317114A (en) * 1980-05-12 1982-02-23 Cromemco Inc. Composite display device for combining image data and method
JPS6020755B2 (ja) * 1980-12-26 1985-05-23 松下電器産業株式会社 画面表示装置
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4438493A (en) * 1981-07-06 1984-03-20 Honeywell Information Systems Inc. Multiwork memory data storage and addressing technique and apparatus
JPS58139241A (ja) * 1982-02-10 1983-08-18 Toshiba Corp 画像メモリアクセス方式
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Also Published As

Publication number Publication date
US4868781A (en) 1989-09-19
US5592649A (en) 1997-01-07
KR910000365B1 (ko) 1991-01-24
CN85107929A (zh) 1986-06-10
CN1006586B (zh) 1990-01-24

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