KR870000705A - 반도체 기억 장치 - Google Patents

반도체 기억 장치 Download PDF

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Publication number
KR870000705A
KR870000705A KR1019850009271A KR850009271A KR870000705A KR 870000705 A KR870000705 A KR 870000705A KR 1019850009271 A KR1019850009271 A KR 1019850009271A KR 850009271 A KR850009271 A KR 850009271A KR 870000705 A KR870000705 A KR 870000705A
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KR
South Korea
Prior art keywords
data
memory device
address
semiconductor memory
signal
Prior art date
Application number
KR1019850009271A
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English (en)
Other versions
KR910000618B1 (ko
Inventor
가즈오 고바야시
다께시 나까야마
야스시 데라다
Original Assignee
시기 모리야
미쓰비시 뎅기 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 시기 모리야, 미쓰비시 뎅기 가부시끼 가이샤 filed Critical 시기 모리야
Publication of KR870000705A publication Critical patent/KR870000705A/ko
Application granted granted Critical
Publication of KR910000618B1 publication Critical patent/KR910000618B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음.

Description

반도체 기억 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일 실시예인 반도체 기억장치의 구성을 나타내는 블럭도.
제2도는 본 발명의 일 실시예인 반도체 기억장치의 데이터 기입동작을 나타낸 플로우챠트.
제4도는 반도체 기억장치에 있어서의 제어신호의 타이밍을 나타낸 파형도.
* 도면의 주요부분에 대한 부호의 설명
12 : 컴패레이터 13 : 기입/소거 제어회로
14 : 입력 데이터 검출회로 15 : 제2의 컬럼 어드레스 래치
16 : 제2의 데이터 래치

Claims (5)

  1. 어드레스 신호에 의한 선택된 기억소자에로 데이터를 기입하는 기능을 적게하는 일도 있을 수 있는 반도체 기억장치로서 기입될 데이터가 미리 정해진 값을 포함하는지 아니하는 지를 검출하는 데이터 검출수단과 상기 데이터 검출수단으로 부터의 검출신호에 응답하여 상기 미리 정해진 값을 포함한 데이터의 어드레스를 래치하는 어드레스 래치 수단과 상기 데이터 검출수단에서의 검출신호에 응답하여 상기 미리 정해진 값을 포함한 데이터를 래치하는 데이터 래치 수단과 상기 어드레스 래치 수단의 동작을 제어하는 신호를 발생하는 제어신호 발생수단과 상기 제어신호 발생수단에서의 제어신호에 응답하여 상기 어드레스 래치 수단에 래치된 어드레스가 지정하는 기억소자가 기억하는 데이터를 판독하는 데이터 판독 수단과 상기 데이터 판독 수단에서의 데이터와 상기 데이터 래치 수단으로 부터의 래치 데이터를 받아서 비교하는 비교 수단과를 갖추고 어드레스 신호에 의한 선택된 기억 소자에의 데이터의 기입의 확인을 확실히 행해지도록 한 반도체 기억장치.
  2. 제1항에 있어서 상기 기억소자는 진기적으로 기입/소거 가능한 프로그래머블 판독 전용의 기억 소자이며 상기 미리 정해진 값은 상기 전기적 기입/소거 가능한 프로그래머블한 판독 전용의 기억소자의 데이터 소거상태를 나타내는 값을 가지는 반도체 기억장치.
  3. 제1항 또는 제2항에 있어서 상기 어드레스 래치 수단이 래치하는 어드레스는 컬럼 어드레스로 되어있는 반도체 기억장치. .
  4. 제1, 2 또는 제3항에 어느 것에 기재된 반도체 기억장치에 있어서 상기 제어신호는 상기 기억소자에의 외부의 데이터의 기입을 제어하는 Ready/Busy 신호의 반전신호로 되어 있는 반도체 기억장치.
  5. 제1,2,3 또는 제4항의 어느 것에 기재의 반도체 장치에 있어서 상기 반도체 기억장치는 메이지 모드동작이 가능한 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850009271A 1985-06-21 1985-12-10 반도체기억장치 KR910000618B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP136538 1982-08-05
JP13653885A JPH0713879B2 (ja) 1985-06-21 1985-06-21 半導体記憶装置
JP60-136538 1985-06-21

Publications (2)

Publication Number Publication Date
KR870000705A true KR870000705A (ko) 1987-02-20
KR910000618B1 KR910000618B1 (ko) 1991-01-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850009271A KR910000618B1 (ko) 1985-06-21 1985-12-10 반도체기억장치

Country Status (3)

Country Link
US (1) US4811294A (ko)
JP (1) JPH0713879B2 (ko)
KR (1) KR910000618B1 (ko)

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Publication number Publication date
KR910000618B1 (ko) 1991-01-28
JPH0713879B2 (ja) 1995-02-15
US4811294A (en) 1989-03-07
JPS61294565A (ja) 1986-12-25

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