KR890004333A - 반도체 메모리 장치 - Google Patents

반도체 메모리 장치 Download PDF

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Publication number
KR890004333A
KR890004333A KR1019880009940A KR880009940A KR890004333A KR 890004333 A KR890004333 A KR 890004333A KR 1019880009940 A KR1019880009940 A KR 1019880009940A KR 880009940 A KR880009940 A KR 880009940A KR 890004333 A KR890004333 A KR 890004333A
Authority
KR
South Korea
Prior art keywords
memory device
semiconductor memory
column
inactivated
activated
Prior art date
Application number
KR1019880009940A
Other languages
English (en)
Other versions
KR910003389B1 (ko
Inventor
다카유키 오오타니
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890004333A publication Critical patent/KR890004333A/ko
Application granted granted Critical
Publication of KR910003389B1 publication Critical patent/KR910003389B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 메모리 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 따른 SRAM의 일부를 나타낸 회로도, 제 2
도는 제 1 도에 도시된 실시예의 변형례를 나타낸 회로도.

Claims (1)

  1. 스태틱 RAM에 설치된 메모리셀 어레이의 각 칼럼에 접속되어 있는 비트선 부하회로에 대해, 그것에 접속되어 있는 칼럼의 기입동작시와 컬럼선택시에만 비활성화하고 그 이외의 때에는 활성화하도록 제어하게끔 구성된 것을 특징으로 하는 반도체메모리장치.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019880009940A 1987-08-13 1988-08-04 반도체 메모리장치 KR910003389B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-202389 1987-08-13
JP62202389A JPS6446288A (en) 1987-08-13 1987-08-13 Semiconductor memory device
JP202389 1987-08-13

Publications (2)

Publication Number Publication Date
KR890004333A true KR890004333A (ko) 1989-04-21
KR910003389B1 KR910003389B1 (ko) 1991-05-28

Family

ID=16456684

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880009940A KR910003389B1 (ko) 1987-08-13 1988-08-04 반도체 메모리장치

Country Status (5)

Country Link
US (1) US4933905A (ko)
EP (1) EP0303971B1 (ko)
JP (1) JPS6446288A (ko)
KR (1) KR910003389B1 (ko)
DE (1) DE3868457D1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
US5155703A (en) * 1990-07-06 1992-10-13 Motorola, Inc. Bicmos bit line load for a memory with improved reliability
KR100208142B1 (ko) * 1990-09-26 1999-07-15 가나이 쓰도무 반도체 메모리
JPH04360095A (ja) * 1991-06-06 1992-12-14 Nec Corp 半導体記憶回路
US5226007A (en) * 1991-08-14 1993-07-06 Vlsi Technology, Inc. Automatic shutoff for memory load device during write operation
JP3057836B2 (ja) * 1991-08-19 2000-07-04 日本電気株式会社 半導体記憶装置
JP2762826B2 (ja) * 1992-03-09 1998-06-04 日本電気株式会社 半導体メモリ
JP2780621B2 (ja) * 1993-12-27 1998-07-30 日本電気株式会社 半導体記憶装置
US5471188A (en) * 1994-10-07 1995-11-28 International Business Machines Corporation Fast comparator circuit
JP3449676B2 (ja) * 1996-10-03 2003-09-22 シャープ株式会社 半導体記憶装置のビット線プリチャージ回路
KR100298030B1 (ko) * 1998-03-27 2001-10-25 다니구찌 이찌로오, 기타오카 다카시 저전원전압하에서고속으로동작하는스태틱형반도체기억장치
US8588004B2 (en) 2012-04-12 2013-11-19 Lsi Corporation Memory device having multi-port memory cell with expandable port configuration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195356A (en) * 1978-11-16 1980-03-25 Electronic Memories And Magnetics Corporation Sense line termination circuit for semiconductor memory systems
US4202045A (en) * 1979-03-05 1980-05-06 Motorola, Inc. Write circuit for a read/write memory
JPS5847792B2 (ja) * 1979-07-26 1983-10-25 富士通株式会社 ビット線制御回路
JPS592997B2 (ja) * 1980-05-22 1984-01-21 富士通株式会社 スタテイツクメモリ
JPS6027114B2 (ja) * 1980-07-24 1985-06-27 日本電気株式会社 メモリ装置
JPH0770222B2 (ja) * 1984-06-04 1995-07-31 株式会社日立製作所 Ｍｏｓスタテイツク型ｒａｍ
JPS6154096A (ja) * 1984-08-24 1986-03-18 Hitachi Ltd 半導体記憶装置
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
JPS61237290A (ja) * 1985-04-12 1986-10-22 Sony Corp ビツト線駆動回路
JPS63166090A (ja) * 1986-12-26 1988-07-09 Toshiba Corp スタティック型メモリ
US4802129A (en) * 1987-12-03 1989-01-31 Motorola, Inc. RAM with dual precharge circuit and write recovery circuitry

Also Published As

Publication number Publication date
EP0303971A3 (en) 1989-08-23
EP0303971B1 (en) 1992-02-19
KR910003389B1 (ko) 1991-05-28
US4933905A (en) 1990-06-12
EP0303971A2 (en) 1989-02-22
JPS6446288A (en) 1989-02-20
DE3868457D1 (de) 1992-03-26

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