JPWO2017099096A1 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 181
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000009825 accumulation Methods 0.000 claims description 33
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 238000000605 extraction Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Abstract
Description
特許文献1 特開2012−190938号公報
Claims (16)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面側に設けられた第2導電型のベース領域と、
前記半導体基板のおもて面から前記ベース領域を貫通して設けられた第1トレンチ部と、
前記半導体基板のおもて面側において前記ベース領域の一部に設けられ、前記ベース領域よりも不純物濃度の高い第2導電型のコンタクト領域と
を備え、
前記第1トレンチ部は、前記半導体基板のおもて面において分岐部を有し、
前記分岐部は、前記半導体基板のおもて面において前記コンタクト領域に囲まれて設けられる半導体装置。 - 前記第1トレンチ部は、前記半導体基板のおもて面において1以上の動作領域をそれぞれ囲むように形成され、
前記半導体装置は、前記半導体基板のおもて面において前記動作領域内に形成され、前記第1トレンチ部とは分離した第2トレンチ部を更に備える
を有する請求項1に記載の半導体装置。 - 前記第1トレンチ部はゲート電極に接続されたゲートトレンチ部であり、前記第2トレンチ部はエミッタ電極に接続されたダミートレンチ部である
請求項2に記載の半導体装置。 - 前記ダミートレンチ部が形成された前記動作領域内には、第1導電型のエミッタ領域が形成されている
請求項3に記載の半導体装置。 - 前記半導体基板のおもて面の上方に形成された層間絶縁膜を更に備え、
前記層間絶縁膜は、前記動作領域と対向する位置に、前記エミッタ領域および前記コンタクト領域の少なくとも一部分を露出させるコンタクトホールを有する
請求項4に記載の半導体装置。 - 前記ゲートトレンチ部は、前記半導体基板のおもて面において1以上の引抜領域をそれぞれ囲むように形成され、
それぞれの前記引抜領域には、前記エミッタ領域が形成されていない
請求項4または5に記載の半導体装置。 - 前記引抜領域は、前記ゲートトレンチ部を介して前記動作領域と隣接して配置されている
請求項6に記載の半導体装置。 - 2つの前記引抜領域が、前記動作領域の両側に配置されている
請求項7に記載の半導体装置。 - 前記半導体基板のおもて面において、前記分岐部から前記エミッタ領域までの距離は、前記分岐部から前記コンタクト領域までの距離よりも大きい
請求項4から8のいずれか一項に記載の半導体装置。 - 前記ゲートトレンチ部は、前記ダミートレンチ部に向かって突出する突出部を有する
請求項3から9のいずれか一項に記載の半導体装置。 - 前記ゲートトレンチ部は、
前記半導体基板のおもて面から前記ベース領域を貫通して設けられたゲートトレンチの内壁に形成された絶縁膜と、
前記絶縁膜で内壁が覆われた前記ゲートトレンチの内部に形成されたゲート導電部と、
前記絶縁膜で内壁が覆われた前記ゲートトレンチの内部において、前記ゲート導電部よりも前記ゲートトレンチの底部側に形成され、前記ゲート導電部と絶縁されている底部側導電部と
を有する請求項3から10のいずれか一項に記載の半導体装置。 - 前記ダミートレンチ部は、
前記半導体基板のおもて面から前記ベース領域を貫通して設けられたダミートレンチの内壁に形成された絶縁膜と、
前記絶縁膜で内壁が覆われた前記ダミートレンチの内部に形成されたダミー導電部と
を有し、
前記底部側導電部は、前記半導体基板の内部において前記ダミー導電部と接続されている
請求項11に記載の半導体装置。 - 前記底部側導電部は、前記分岐部において下方に突出した突出領域を有する
請求項11または12に記載の半導体装置。 - 前記第1トレンチ部は、前記半導体基板のおもて面から前記ベース領域を貫通して設けられたトレンチの内壁に形成された絶縁膜を有し、
前記第1トレンチ部の前記分岐部の底部における前記絶縁膜の厚みは、前記第1トレンチ部の前記分岐部以外の底部における前記絶縁膜の厚みよりも厚い
請求項1から10のいずれか一項に記載の半導体装置。 - 前記半導体基板において前記ベース領域の下方に形成された蓄積領域を更に備え、
前記第1トレンチ部は、前記蓄積領域を貫通して設けられる
請求項1から14のいずれか一項に記載の半導体装置。 - 前記分岐部を囲んで、前記蓄積領域に、前記第1トレンチ部に接する位置の前記蓄積領域の深さ方向の厚みが、隣り合う前記第1トレンチ部から前記半導体基板のおもて面と平行な方向に最も離れた位置の前記蓄積領域の厚みよりも薄い周辺領域が設けられている
請求項15に記載の半導体装置。
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JP2015242474 | 2015-12-11 | ||
JP2015242474 | 2015-12-11 | ||
JP2016158920 | 2016-08-12 | ||
JP2016158920 | 2016-08-12 | ||
PCT/JP2016/086285 WO2017099096A1 (ja) | 2015-12-11 | 2016-12-06 | 半導体装置 |
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JPWO2017099096A1 true JPWO2017099096A1 (ja) | 2018-03-29 |
JP6451869B2 JP6451869B2 (ja) | 2019-01-16 |
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DE102016125879B3 (de) * | 2016-12-29 | 2018-06-21 | Infineon Technologies Ag | Halbleitervorrichtung mit einer IGBT-Region und einer nicht schaltbaren Diodenregion |
DE102018100237B4 (de) * | 2018-01-08 | 2022-07-21 | Infineon Technologies Austria Ag | Leistungshalbleiterbauelement mit dU/dt Steuerbarkeit und Verfahren zum Herstellen eines Leistungshalbleiterbauelements |
DE112019000095T5 (de) | 2018-03-15 | 2020-09-24 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
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