JP7438080B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7438080B2 JP7438080B2 JP2020182505A JP2020182505A JP7438080B2 JP 7438080 B2 JP7438080 B2 JP 7438080B2 JP 2020182505 A JP2020182505 A JP 2020182505A JP 2020182505 A JP2020182505 A JP 2020182505A JP 7438080 B2 JP7438080 B2 JP 7438080B2
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Description
<構成>
図1は、本実施の形態1に係る半導体装置の構成を示す断面図である。以下、半導体装置が、IGBTである半導体素子100を含む構成について主に説明する。
次に本実施の形態1に係る半導体素子の製造方法の一例について説明する。まず、n-型ドリフト層9を有する半導体基板を準備する。半導体基板には、例えば、FZ(Floating Zone)法で作製されたFZウエハ、または、MCZ(Magnetic applied CZochralki)法で作製されたMCZウエハなどの、n型不純物を含むn型ウエハが用いられてもよい。
次に、本実施の形態1に係る半導体素子100のターンオン損失及びオン電圧について説明する前に、それに関連する内容について説明する。
本実施の形態1では、上段アクティブ部13の下端が、n型キャリア蓄積層6の下端よりも下方に位置するように構成されている。このような構成によれば、上段アクティブ部13がn型キャリア蓄積層6の下部と対向することによりCGC/CGEを大きくできるので、ターンオン損失を低減することができる。また、n型キャリア蓄積層6の下部のうちトレンチ7の側面と接する部分に蓄積層が形成されるので、キャリア蓄積効果を高めることができ、オン電圧を低減できる。
実施の形態1では、2段ゲートA/Dのうちの上段アクティブ部13の深さLaは、p型ベース層5の深さLbの1.5倍以上であったが、これに限ったものではない。例えば、上段アクティブ部13の深さLaは、p型ベース層5の深さLbの2倍以上であってもよい。
<構成>
図10は、本実施の形態2に係る半導体装置の構成を示す断面図である。なお、図10以降の断面図では、ゲート電極15及びその配線などの図示を適宜省略することもある。
まず、実施の形態1で説明した図2(a)の工程を行う。次に、図11(a)に示すように、トレンチ7を形成した後、酸素を含む雰囲気中で半導体基板を加熱してトレンチ7の内壁及び半導体基板の上面に比較的厚いゲート酸化膜8を形成する。
実施の形態1のように上段アクティブ部13が深くまで配設された構成では、下段ダミー部14を形成する時のポリシリコンのエッチングを比較的長く行う必要がある。このため、図2(c)及び図3(a)に示されるように、ポリシリコン14aのエッチング時にゲート酸化膜8が薄いと、半導体基板の上面上のゲート酸化膜8がエッチングで消失して、n+型ソース層4がエッチングされることがある。これに対して本実施の形態2では、図11(b)で示されるように、ポリシリコンのエッチング時においてゲート酸化膜8が厚いので、半導体基板の上面及びn+型ソース層4へのエッチングを抑制することができる。
これまでの説明では、トレンチには2段ゲートA/Dのみが配設されたが、これに限ったものではない。
以上のような1段ゲートAを挿入した構成では、CGC/CGEをさらに大きくできるので、ターンオン損失をさらに低減することができる。また、ダイナミックアバランシェにより発生したホットキャリアの注入を、1段ゲートAの厚い第4絶縁膜22によって抑制できるため、ゲート特性の劣化を抑制できる。
図14は、本変形例2に係る半導体装置の構成を示す断面図である。
図15は、本変形例3に係る半導体装置の構成を示す断面図である。
図16は、本実施の形態3に係る半導体装置の構成を示す断面図である。
図17は、本実施の形態4に係る半導体装置の構成を示す断面図である。
実施の形態4では、p型ボトム層32の厚さ及び幅は比較的小さかったが、これに限ったものではない。図18に示されるように、隣り合ったp型ボトム層32同士が接続される程度に、p型ボトム層32の厚さ及び幅は大きくてもよい。このような構成によれば、p型ボトム層32によって、より広い範囲で電圧を維持できるため、電界をさらに低減できる。このため、ダイナミックアバランシェの発生がさらに抑制され、ゲート特性の劣化を抑制できる。
実施の形態1~4の上段アクティブ部13は、RC-IGBTのゲートに用いられてもよい。すなわち、実施の形態1~4の半導体素子100はRC-IGBTであってもよい。以下、RC-IGBTの構成について簡単に説明する。
実施の形態1~4の上段アクティブ部13は、MOSFET(Metal Oxcide Semiconductor Field Effect Transistor)のゲートに用いられてもよい。すなわち、実施の形態1~4の半導体素子100はMOSFETであってもよい。
実施の形態1~4では、半導体基板などに用いられる半導体について記載しなかったが、この半導体は、珪素であってもよいし、ワイドバンドギャップ半導体であってもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、酸化ガリウムまたはダイヤモンドを含む。このような構成によれば、半導体装置の耐圧を高めることができる。
Claims (11)
- エミッタ電極及びゲート電極が設けられた半導体基板と、
前記半導体基板の上面側に配設された第1導電型のキャリア蓄積層と、
前記キャリア蓄積層の前記上面側に配設された第2導電型のベース層と、
前記ベース層の前記上面側に配設された第1導電型のソース層と、
前記ソース層、前記ベース層、及び、前記キャリア蓄積層を貫通するトレンチの上部の内壁に沿う第1絶縁膜上に配設され、前記ゲート電極と接続された上段ポリシリコンである上段アクティブ部と、
前記トレンチの下部の内壁に沿う第2絶縁膜上に配設され、前記上段アクティブ部との間に第3絶縁膜が配設された下段ポリシリコンと
を備え、
前記下段ポリシリコンは、
前記エミッタ電極と接続された下段ダミー部、前記ゲート電極と接続された下段アクティブ部、及び、電気的にフローティングされた下段フローティング部のいずれかであり、
前記上段アクティブ部の下端が、前記キャリア蓄積層の下端よりも下方に位置し、
前記上段アクティブ部の深さが、前記ベース層の深さの1.5倍以上である、半導体装置。 - エミッタ電極及びゲート電極が設けられた半導体基板と、
前記半導体基板の上面側に配設された第1導電型のキャリア蓄積層と、
前記キャリア蓄積層の前記上面側に配設された第2導電型のベース層と、
前記ベース層の前記上面側に配設された第1導電型のソース層と、
前記ソース層、前記ベース層、及び、前記キャリア蓄積層を貫通するトレンチの上部の内壁に沿う第1絶縁膜上に配設され、前記ゲート電極と接続された上段ポリシリコンである上段アクティブ部と、
前記トレンチの下部の内壁に沿う第2絶縁膜上に配設され、前記上段アクティブ部との間に第3絶縁膜が配設された下段ポリシリコンと
を備え、
前記下段ポリシリコンは、
前記エミッタ電極と接続された下段ダミー部、前記ゲート電極と接続された下段アクティブ部、及び、電気的にフローティングされた下段フローティング部のいずれかであり、
前記上段アクティブ部の下端が、前記キャリア蓄積層の下端よりも下方に位置し、
前記キャリア蓄積層の前記上面側に配設され、電気的にフローティングされた第2導電型の半導体層と、
前記半導体層、及び、前記キャリア蓄積層を貫通するトレンチの上部から下部までの内壁に沿う第4絶縁膜上に配設され、前記ゲート電極と接続されたポリシリコンであるアクティブ部と
をさらに備える、半導体装置。 - エミッタ電極及びゲート電極が設けられた半導体基板と、
前記半導体基板の上面側に配設された第1導電型のキャリア蓄積層と、
前記キャリア蓄積層の前記上面側に配設された第2導電型のベース層と、
前記ベース層の前記上面側に配設された第1導電型のソース層と、
前記ソース層、前記ベース層、及び、前記キャリア蓄積層を貫通するトレンチの上部の内壁に沿う第1絶縁膜上に配設され、前記ゲート電極と接続された上段ポリシリコンである上段アクティブ部と、
前記トレンチの下部の内壁に沿う第2絶縁膜上に配設され、前記上段アクティブ部との間に第3絶縁膜が配設された下段ポリシリコンと
を備え、
前記下段ポリシリコンは、
前記ゲート電極と接続された下段アクティブ部であり、
前記上段アクティブ部の下端が、前記キャリア蓄積層の下端よりも下方に位置する、半導体装置。 - 請求項1に記載の半導体装置であって、
前記上段アクティブ部の深さが、前記ベース層の深さの2倍以上である、半導体装置。 - 請求項1から請求項3のうちのいずれか1項に記載の半導体装置であって、
前記第2絶縁膜の厚みは、前記第1絶縁膜の厚みよりも厚い、半導体装置。 - 請求項1または請求項3に記載の半導体装置であって、
前記ソース層、前記ベース層、及び、前記キャリア蓄積層を貫通するトレンチの上部から下部までの内壁に沿う第4絶縁膜上に配設され、前記ゲート電極と接続されたポリシリコンであるアクティブ部、または、前記エミッタ電極と接続されたポリシリコンであるダミー部をさらに備え、
前記第4絶縁膜の厚みは、前記第1絶縁膜の厚みよりも厚い、半導体装置。 - 請求項1から請求項3のうちのいずれか1項に記載の半導体装置であって、
前記半導体基板のうち前記トレンチの底部に配設された第2導電型のボトム層をさらに備える、半導体装置。 - 請求項7に記載の半導体装置であって、
前記ボトム層は前記第1絶縁膜に接することなく前記第2絶縁膜に接する、半導体装置。 - 請求項1から請求項8のうちのいずれか1項に記載の半導体装置であって、
前記上段アクティブ部は、RC-IGBTのゲートに用いられる、半導体装置。 - 請求項1から請求項8のうちのいずれか1項に記載の半導体装置であって、
前記上段アクティブ部は、MOSFETのゲートに用いられる、半導体装置。 - 請求項1から請求項10のうちのいずれか1項に記載の半導体装置であって、
前記半導体基板は、ワイドバンドギャップ半導体を含む、半導体装置。
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