CN114975577A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN114975577A
CN114975577A CN202110195555.6A CN202110195555A CN114975577A CN 114975577 A CN114975577 A CN 114975577A CN 202110195555 A CN202110195555 A CN 202110195555A CN 114975577 A CN114975577 A CN 114975577A
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龚轶
刘伟
刘磊
王睿
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202110195555.6A priority Critical patent/CN114975577A/zh
Priority to KR1020237001214A priority patent/KR20230023013A/ko
Priority to PCT/CN2021/131693 priority patent/WO2022174641A1/zh
Priority to US18/016,767 priority patent/US20240038877A1/en
Priority to JP2023501196A priority patent/JP2023532376A/ja
Publication of CN114975577A publication Critical patent/CN114975577A/zh
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Abstract

本发明公开了一种半导体器件，包括：半导体衬底；位于所述半导体衬底顶部的p型体区，所述p型体区与发射极金属层接触；所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；所述第一区域内的所述p型体区内设有第一p型体区接触区，所述发射极金属层与所述第一p型体区接触区接触并形成欧姆接触；所述第二区域内的所述p型体区与所述发射极金属层未形成欧姆接触。本发明可以改善半导体器件在应用时产生的电压震荡、电流震荡和EMI问题。

Description

半导体器件
技术领域
本发明属于半导体器件技术领域，特别是涉及一种功率半导体器件。
背景技术
现有技术的功率半导体器件通常通过降低器件的米勒电容来提高开关速度以减少开关损耗，但是开关速度过快会导致大的电压震荡和电流震荡，这使得功率半导体器件在应用时的EMI问题严重。
发明内容
有鉴于此，本发明的目的是提供一种半导体器件，以降低半导体器件在应用时产生的EMI问题。
为达到本发明的上述目的，本发明提供了一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底底部交替间隔设置的n型集电极区和p型集电极区；
位于所述导体衬底内且位于所述n型集电极区和所述p型集电极区之上的n型漂移区；
位于所述半导体衬底顶部的p型体区，所述p型体区与发射极金属层接触；
所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；
所述第一区域内的所述p型体区内设有第一p型体区接触区，所述发射极金属层与所述第一p型体区接触区接触并形成欧姆接触；
所述第二区域内的所述p型体区与所述发射极金属层未形成欧姆接触。
可选的，所述第一区域的形状包括多边形、圆形或者椭圆形中的至少一种。
可选的，所述第二区域内的所述p型体区内设有第二p型体区接触区，所述第二p型体区接触区的掺杂浓度小于所述第一p型体区接触区的掺杂浓度。
可选的，所述发射极金属层与所述第二p型体区接触区接触但未形成欧姆接触。
可选的，还包括位于所述p型体区内的n型发射极区，所述n型发射极区与所述发射极金属层接触。
可选的，还包括位于所述半导体衬底内的n型场截止区，所述n型场截止区位于所述n型集电极区和所述p型集电极区之上且位于所述n型漂移区下方。
可选的，还包括栅极结构，所述栅极结构包括栅介质层和栅极。
可选的，所述栅极结构为平面栅结构或者为沟槽栅结构。
本发明提出的半导体器件，第一区域的p型体区内设置第一p型体区接触区，第一p型体区接触区与发射极金属层形成欧姆接触，即第一区域内的p型体区与发射极金属层形成欧姆接触，第二区域内的p型体区与发射极金属层没有形成欧姆接触，没有形成欧姆接触的p型体区的电势不固定导致阈值电压Vth会变化，而且距离形成欧姆接触的p型体区越远的未形成欧姆接触的p型体区的阈值电压Vth与形成欧姆接触的p型体区的阈值电压Vth差异越大，由此本发明的半导体器件具有缓变的阈值电压Vth，在开启和关断时，电流和电压不容易突变，从而可以以降低半导体器件在应用时产生的EMI问题。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的半导体器件的第一个实施例的俯视示意图；
图2是图1所示结构沿AA方向的剖面示意图；
图3是本发明提供的半导体器件的第二个实施例的俯视示意图。
具体实施方式
以下将结合本发明实施例中的附图，完整地描述本发明的技术方案。应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在。
本领域的技术人员应该理解，功率半导体器件芯片包括元胞区和终端区，其中，元胞区为电流工作区，终端区用于提高元胞区中最边缘的元胞的耐压，本发明实施例中所述的半导体器件指的是功率半导体器件芯片中的元胞区。
图1是本发明提供的半导体器件的第一个实施例的俯视示意图，图2是图1所示结构沿AA方向的剖面示意图。如图1和图2所示，本发明的半导体器件包括半导体衬底10，半导体衬底10通常为硅衬底，位于半导体衬底10底部且交替间隔设置的n型集电极区11和p型集电极区13，位于n型集电极区11和p型集电极区13之上的n型漂移区12。位于半导体衬底10顶部的p型体区20，p型体区20与n型漂移区12形成pn结结构。半导体器件芯片的元胞区包括若干个p型体区，图1和图2中仅示例性的展示出了6个p型体区20。位于p型体区20内的n型发射极区21，p型体区20和n型发射极区21均与发射极金属层17接触。
可选的，在半导体衬底内10还可以设置n型场截止区，n型场截止区位于n型集电极区11和p型集电极区13之上且位于n型漂移区12下方，n型场截止区为现有技术的常规选择，本发明实施例中不再具体展示。
如图1所示，在半导体衬底10的上表面的俯视面上，半导体衬底10包括至少一个第一区域51，本发明对第一区域51的数量和形状不做具体限定，图1中仅示例性的示出了一个第一区域51且第一区域51为圆形结构，将第一区域51外的区域定义为第二区域。
位于第一区域51内的p型体区20内设有第一p型体区接触区22，发射极金属层17与第一p型体区接触区22接触并形成欧姆接触。由于第一p型体区接触区22的掺杂浓度大于p型体区20的掺杂浓度，因此第一p型体区接触区22提高了p型体区20与发射极金属层17相接触处的掺杂浓度，使得第一区域51内的p型体区20与发射极金属层17形成欧姆接触。
第二区域内的p型体区20由于掺杂浓度较低，因此第二区域内的p型体区20与发射极金属层17接触后未形成欧姆接触。可选的，也可以在此第二区域内的p型体区20内形成第二p型体区接触区，但是第二p型体区的掺杂浓度低于第一p型体区接触区22的掺杂浓度，使得第二p型体区接触区与发射极金属层17接触后也不能形成欧姆接触，或者使得第二p型体区接触区与发射极金属层17接触后形成的欧姆接触电阻较大。
如图2所示，本发明的半导体器件还包括栅极结构，栅极结构包括栅介质层14和栅极15，栅极结构通过层间绝缘层16与发射极金属层17隔离。图2中，本发明的半导体器件的栅极结构为平面栅结构，可选的，本发明的半导体器件的栅极结构也可以为沟槽栅结构，该结构为现有技术的常规选择，本发明实施例中不再具体展示。
本发明的半导体器件，第一区域51内的p型体区20通过第一p型体区接触区22与发射极金属层17形成欧姆接触，第二区域内的p型体区20与发射极金属层17没有形成欧姆接触，没有形成欧姆接触的p型体区20的电势不固定导致阈值电压Vth会变化，而且距离形成欧姆接触的p型体区20越远的未形成欧姆接触的p型体区20的阈值电压Vth与形成欧姆接触的p型体区的阈值电压Vth差异越大，即在第二区域中，靠近第一区域一侧的P型体区与第一区域中的P型体区的阈值电压差小于远离第一区域一侧的P型体区与第一区域中的P型体区的阈值电压差，由此本发明的半导体器件具有缓变的阈值电压Vth，在开启和关断时，电流和电压不容易突变，从而可以以降低半导体器件在应用时产生的电压震荡和电流震荡以及EMI问题。同时也可改善器件的反向恢复特性。
图3是本发明提供的半导体器件的第二个实施例的俯视示意图，在图3中，半导体衬底10包括6个第一区域51，第一区域51为长方形，可选的，第一区域51可以为三角形、正方形、正多边形、长方形、平行四边形、梯形、圆形、椭圆形等规则图形，也可以为不规则图形，本发明实施例对第一区域51的形状不进行限定，第一区域51的俯视形状只需为封装图形即可，例如由直线和/或曲线依次首尾连接形成的封闭图形即可。
进一步的，在图1和图3所示的俯视示意图中，均以第二区域包围第一区域为例进行说明，需要说明的是，本发明实施例对第一区域以及第二区域的相对位置关系不进行限定，可以如图1和图3所示，也可以是第一区域包围第二区域，还可以是第一区域和第二区域沿某一与半导体衬底所在平面平行的方向依次设置。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (8)

1.半导体器件，其特征在于，包括：
半导体衬底；
位于所述半导体衬底底部交替间隔设置的n型集电极区和p型集电极区；
位于所述导体衬底内且位于所述n型集电极区和所述p型集电极区之上的n型漂移区；
位于所述半导体衬底顶部的p型体区，所述p型体区与发射极金属层接触；
所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；
所述第一区域内的所述p型体区内设有第一p型体区接触区，所述发射极金属层与所述第一p型体区接触区接触并形成欧姆接触；
所述第二区域内的所述p型体区与所述发射极金属层未形成欧姆接触。
2.如权利要求1所述的半导体器件，其特征在于，所述第一区域的形状包括多边形、圆形或者椭圆形中的至少一种。
3.如权利要求1所述的半导体器件，其特征在于，所述第二区域内的所述p型体区内设有第二p型体区接触区，所述第二p型体区接触区的掺杂浓度小于所述第一p型体区接触区的掺杂浓度。
4.如权利要求3所述的半导体器件，其特征在于，所述发射极金属层与所述第二p型体区接触区接触但未形成欧姆接触。
5.如权利要求1所述的半导体器件，其特征在于，还包括位于所述p型体区内的n型发射极区，所述n型发射极区与所述发射极金属层接触。
6.如权利要求1所述的半导体器件，其特征在于，还包括位于所述半导体衬底内的n型场截止区，所述n型场截止区位于所述n型集电极区和所述p型集电极区之上且位于所述n型漂移区下方。
7.如权利要求1所述的半导体器件，其特征在于，还包括栅极结构，所述栅极结构包括栅介质层和栅极。
8.如权利要求7所述的半导体器件，其特征在于，所述栅极结构为平面栅结构或者为沟槽栅结构。
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