JPS6243155A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPS6243155A JPS6243155A JP60181692A JP18169285A JPS6243155A JP S6243155 A JPS6243155 A JP S6243155A JP 60181692 A JP60181692 A JP 60181692A JP 18169285 A JP18169285 A JP 18169285A JP S6243155 A JPS6243155 A JP S6243155A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- glass
- expansion coefficient
- substrate
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路パッケージに係わり、特に、基板に
熱伝導性がよく、半導体素子の熱膨張係数に近似した炭
化ケイ素質セラミックスを用いた集積回路パッケージに
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit package, and in particular, the present invention relates to an integrated circuit package, and in particular, an integrated circuit package using silicon carbide ceramics, which has good thermal conductivity and has a coefficient of thermal expansion close to that of a semiconductor element, as a substrate. Relating to integrated circuit packages.
セラミックス質絶縁基板、キャップ及び封止ガラスによ
って気密に囲われた小室内に、半導体素子並びに外部か
ら導入されたリード端部と両者を電気的に接続した接合
部とを収容した構造からなる集積回路パッケージは、今
日広く実用に供せられている。An integrated circuit that has a structure in which a semiconductor element, lead ends introduced from the outside, and a joint that electrically connects the two are housed in a small chamber hermetically surrounded by a ceramic insulating substrate, a cap, and a sealing glass. Packages are in widespread use today.
そのようなパッケージを用いた際の難点として半導体素
子に生じた熱の放熱特性が挽めて悪いということである
。このことは半導体素子の大容叶化、高集積化及び小型
化を図るうえで大きな障害となっている。従って、集積
回路パッケージにおいて、半導体素子を接着する絶縁基
板には、電気絶縁性とともに優れた熱伝導性を有するこ
とが要求される。また、シリコンを用いた集積回路を接
着するために、基板用材料としては、熱膨張係数がシリ
コンに近似することが望まれる。A drawback of using such a package is that the heat dissipation characteristics of the heat generated in the semiconductor element are poor. This is a major obstacle in achieving larger capacity, higher integration, and smaller size of semiconductor devices. Therefore, in an integrated circuit package, an insulating substrate to which a semiconductor element is bonded is required to have excellent thermal conductivity as well as electrical insulation. Further, in order to bond an integrated circuit using silicon, it is desirable that the substrate material have a thermal expansion coefficient similar to that of silicon.
このような要求を満足する材料として、炭化ケイ素質セ
ラミックスがある。それを絶縁基板として、熱放散性の
良好な集積回路パッケージの製作を可能にした（特開昭
５９−１３４８５２．特開昭６Ｏ−６６８４３） ）。Silicon carbide ceramics are a material that satisfies these requirements. By using it as an insulating substrate, it became possible to manufacture an integrated circuit package with good heat dissipation (Japanese Patent Laid-Open Nos. 59-134852 and 60-66843).
しかし、前記炭化ケイ素質基板の適用に関する検討の進
行に伴い、炭化ケイ素質基板に半導体素子を搭載し、半
導体素子に電気的リード端部を接続し、これら、半導体
素子とリード接続部をキャップと封止ガラスによりパッ
ケージをつくり、ガラスを貫通して電気的リードを外部
に取り出す集積回路パッケージを作製したところ、封止
ガラス部、特にリード端子周辺のガラスに亀裂を生ずる
という問題を生じた。そして、この場合、半導体素子が
入った小室内と外気とがつながるため、外気中に含まれ
る水分が小室内に入り、動作不良につながる恐れがある
。However, with the progress of studies regarding the application of silicon carbide substrates, semiconductor elements are mounted on silicon carbide substrates, electrical lead ends are connected to the semiconductor elements, and these semiconductor elements and lead connection parts are connected with caps. When an integrated circuit package was manufactured in which a package was made of sealing glass and electrical leads were taken out to the outside by passing through the glass, a problem occurred in that the sealing glass part, especially the glass around the lead terminals, cracked. In this case, since the small chamber containing the semiconductor element is connected to the outside air, moisture contained in the outside air may enter the small chamber, leading to malfunction.
上記した封止ガラスに生ずる亀裂は、リード材料の熱膨
張率が大きいことに起因する熱応力によるものと考えら
れる。The cracks that occur in the sealing glass described above are considered to be caused by thermal stress caused by the large coefficient of thermal expansion of the lead material.
そして、前記封止ガラス部のクランク防止手段として一
般的に考えられるのは、封止ガラスと熱膨張係数が合致
したリード材料を用いることであるが、本発明者等の研
究によれば、炭化ケイ素質セラミックスを基板として用
いる本発明の対象となるパッケージの場合には、リード
材料の熱膨張係数をガラスの熱膨張係数のそれと合致さ
せても、前記クラックの防止には何等有効ではないこと
が確認された。Generally speaking, as a means to prevent the sealing glass from cranking, it is possible to use a lead material whose coefficient of thermal expansion matches that of the sealing glass, but according to research by the present inventors, carbonization In the case of a package subject to the present invention that uses silicon ceramic as a substrate, even if the coefficient of thermal expansion of the lead material matches that of glass, it is not effective at all to prevent the above-mentioned cracks. confirmed.
そこで、本発明者等はさらに研究を進めた結果、リード
材料の熱膨張係数をガラスの熱膨張係数を基準にして設
定するのではなく、前記基板の熱膨張係数を基準として
これとほぼ同等かまたはそれ以下とすることにより、き
わめて有効に前記封止ガラス部のクラックが防止される
ことを突き止め、この新規な知見にもとづいて本発明を
完成するに到ったものである。Therefore, as a result of further research, the present inventors decided to set the thermal expansion coefficient of the lead material not based on the thermal expansion coefficient of glass, but to set it almost equal to the thermal expansion coefficient of the substrate. It has been found that cracks in the sealing glass portion can be extremely effectively prevented by setting the temperature to be 1.5 or less, and based on this new knowledge, the present invention has been completed.
本発明は上記知見に基づき、リード材料の熱膨張係数を
限定することにより、一層高い安定性と信幀性を有する
集積回路パッケージを提供するものであって、その特徴
は炭化ケイ素質基板、キャップ及び封止ガラスによって
気密に囲われた小室内に、該基板上に載置された半導体
素子と該室外から封止ガラスを貫通して導入されたリー
ドからなる集積回路パッケージにおいて、リード材料の
熱膨張係数を基板の熱膨張係数とほぼ同等かまたはそれ
以下、さらに具体的には、４０Ｘ１０−７／℃以下に限
定とすることにある。Based on the above findings, the present invention provides an integrated circuit package having even higher stability and reliability by limiting the thermal expansion coefficient of the lead material. In an integrated circuit package consisting of a semiconductor element mounted on the substrate and a lead introduced from outside through the sealing glass into a small chamber hermetically enclosed by sealing glass, the heat of the lead material is removed. The purpose is to limit the expansion coefficient to approximately the same as or less than the thermal expansion coefficient of the substrate, more specifically to 40×10 −7 /° C. or less.
ここで、本発明で用いられる基板材料は実質的に炭化ケ
イ素からなるセラミックス基板である。特に、ベリリウ
ム及びベリリウム化合物のうちから選ばれた少なくとも
１種をヘリリウム量にして０．０５〜５重量％を含む炭
化ケイ素セラミックスが適する。その熱膨張係数は３５
〜４０×１０−７／℃である。キャップに用いる材料は
ムライト質セラミックス、炭化ケイ素質セラミックス、
ジルコン質セラミックス、窒化ケイ素質セラミックスな
どが使われ、その熱膨張係数は３５〜５０ Ｘ １０−
’／ ’Ｃを有する材料に限定される。また、封止ガラ
スとしては、熱膨張係数が４５〜５５ＸＩＯ−’／”Ｃ
に限定され、しかも、封止温度が４７０℃以下に限定さ
れた低融点ガラスである。封止温度が限定される理由は
、基板の上に接合された半導体素子が、封止作業温度が
４７０℃以上の高温になると、半導体の電極に用いられ
ているＡＩ等が半導体のＰｎ接合部に拡散し、劣化をお
こすためである。このように低温で接着作業ができ、熱
膨張係数が炭化ケイ素質セラミノクスに近似したガラス
はない。このため、低融点の硼ケイ酸鉛系ガラスに負の
熱膨張係数をもつチタン酸鉛またはβ−ユークリプタイ
ト等のフィラーをガラスに混合して、熱膨張係数を小さ
くしている。しかし、これらワイヤを多量に入れるとガ
ラスの流動性が悪くなるためガラスの熱膨張係数は４５
〜５５×１０−’／”ｃに限定される。Here, the substrate material used in the present invention is a ceramic substrate consisting essentially of silicon carbide. In particular, silicon carbide ceramics containing at least one selected from beryllium and beryllium compounds in an amount of 0.05 to 5% by weight of helium are suitable. Its coefficient of thermal expansion is 35
~40x10-7/°C. The materials used for the cap are mullite ceramics, silicon carbide ceramics,
Zircon ceramics, silicon nitride ceramics, etc. are used, and their coefficient of thermal expansion is 35 to 50 x 10-
Limited to materials with '/'C. In addition, as sealing glass, the coefficient of thermal expansion is 45 to 55XIO-'/"C
It is a low melting point glass whose sealing temperature is limited to 470°C or less. The reason why the sealing temperature is limited is that when the sealing operation temperature of a semiconductor element bonded on a substrate reaches a high temperature of 470°C or higher, the AI used for the electrodes of the semiconductor will break down at the Pn junction of the semiconductor. This is because it spreads and causes deterioration. There is no glass that can be bonded at such low temperatures and has a thermal expansion coefficient similar to that of silicon carbide ceraminox. For this reason, a filler such as lead titanate or β-eucryptite, which has a negative coefficient of thermal expansion, is mixed with lead borosilicate glass having a low melting point to reduce the coefficient of thermal expansion. However, if a large amount of these wires are added, the fluidity of the glass will deteriorate, so the coefficient of thermal expansion of the glass will be 45.
~55×10−′/”c.
上記に示すような材料を組み合わせて第１図に示すよう
な炭化ケイ素質セラミックスを基板として用い熱処理に
よりガラスでパンケージを作製する際に、上記のように
この封止ガラス部、特にリード端子周辺のガラスにクラ
ンクが入りやすいものであるが、前述のように本発明に
おいては、リード材料の熱膨張係数を基板の熱膨張係数
とほぼ同等またはそれ以下の４０Ｘ１０−’／℃以下に
することにより、封止ガラスに貫通したクランクを生じ
ない信顛性の優れたパッケージを作製することが可能と
なるものである。そして、このようなりランク防止の効
果は、リード材料の熱膨張係数を前記のように限定する
ことにより、封止ガラス中に封入されたリード材料が、
本来基板より大きい熱膨張係数を有するる封止ガラスの
それを基板の熱膨張係数に近づける作用をするからであ
ると考えられる。When creating a glass pancage by heat treatment using silicon carbide ceramics as a substrate as shown in Figure 1 by combining the materials shown above, the sealing glass part, especially around the lead terminals, is Although it is easy for a crank to enter glass, as mentioned above, in the present invention, by setting the thermal expansion coefficient of the lead material to 40X10-'/°C or less, which is approximately equal to or lower than the thermal expansion coefficient of the substrate, This makes it possible to produce a highly reliable package that does not cause a crank to penetrate through the sealing glass. The effect of preventing this rank is achieved by limiting the thermal expansion coefficient of the lead material as described above, so that the lead material encapsulated in the sealing glass
This is thought to be due to the effect of bringing the thermal expansion coefficient of the sealing glass, which originally has a larger coefficient of thermal expansion than the substrate, closer to that of the substrate.
このようなリード材料としてはコバール（Ｎｉ−Ｃｏ−
Ｆｅ合金）がある。特にＮｉ２８．５〜３０．０． Ｃ
ｏ １２．５〜１４． ＣＯ，０２以下、 Ｓｉ Ｏ，
２以下、 Ｍｎ Ｏ，８以下、残りＦｅ （ｗｔ％）の
組成のコバールが適する。Kovar (Ni-Co-
(Fe alloy). Especially Ni28.5~30.0. C
o 12.5-14. CO,02 or less, SiO,
Kovar having a composition of 2 or less, Mn 2 O, 8 or less, and the remainder Fe (wt%) is suitable.
第１図に本発明の集積回路パッケージの断面を例示する
。同図において炭化ケイ素質セラミックスからなる基板
４の一方の面４ａ上の中央部に半導体素子１が金属ソル
ダ層７によって接着され、同面上に封止ガラス層６によ
って接着された複数個のリード片３の一端３ａと該素子
１との間はボンディングワイヤ２によって電気的に接続
されている。リード片３の他端３ｂは、基板４の周縁か
ら外方に延びている。素子１、ボンディングワイヤ２及
びリード片３の端部３ａは絶縁基板４とキャップ５とに
よって囲われ、該キャップ５と基板４及びリード片３と
の間隙は封止ガラス層６を介して気密に封着されている
。FIG. 1 illustrates a cross section of an integrated circuit package of the present invention. In the figure, a semiconductor element 1 is bonded to the center of one surface 4a of a substrate 4 made of silicon carbide ceramics with a metal solder layer 7, and a plurality of leads bonded to the same surface with a sealing glass layer 6. One end 3a of the piece 3 and the element 1 are electrically connected by a bonding wire 2. The other end 3b of the lead piece 3 extends outward from the periphery of the substrate 4. The end portions 3a of the element 1, bonding wire 2, and lead piece 3 are surrounded by an insulating substrate 4 and a cap 5, and the gaps between the cap 5, the substrate 4, and the lead piece 3 are made airtight through a sealing glass layer 6. It is sealed.
上記パッケージの構造において、キャップ材料、ガラス
材料及びリード材料をかえて、パッケージを作製した。Packages were produced by changing the cap material, glass material, and lead material in the above package structure.
基板材料は熱膨張係数が３５〜４０ Ｘ １０−’／
’Ｃをもつ炭化ケイ素質セラミックスである。特に、ベ
リリウムを０．０５〜５重量％を含む、抵抗率１０”Ω
・ｃｍ以上の電気絶縁性と、熱伝導率０．２〜０．７ｃ
ａｌ！／ｃ１１・ｓ・℃の特性を持つ、炭化ケイ素質セ
ラミックスが有効である。The substrate material has a thermal expansion coefficient of 35 to 40 x 10-'/
It is a silicon carbide ceramic with 'C. In particular, it contains 0.05-5% by weight of beryllium and has a resistivity of 10”Ω.
・Electrical insulation of cm or more and thermal conductivity of 0.2 to 0.7c
Al! Silicon carbide ceramics having a property of /c11·s·°C are effective.
このパッケージは以下の方法で作製される。This package is produced by the following method.
まず、炭化ケイ素基板の上に、半導体素子を接合するた
めのＡｕペーストを印刷、焼成して、基板上に金属ソル
ダ層７を形成する。次に、炭化ケイ素基板上に封止ガラ
ス６を印刷し、焼成して、ガラスを基板につける。リー
ド片３を封止ガラス層６の上面に設置し、ガラスの軟化
温度以上、例えば４５０〜４８０℃に加熱して、リード
片を接着する。半導体素子１を基板上の金属ソルダ層７
に設置し、３５０〜４５０℃に加熱することにより金属
ソルダ層７を形成して、半導体素子を接着する。半導体
素子とリード片端子とをワイヤ２により電気的に接続す
る。次に、封止ガラス６が付いたキャップ材５を載せ、
４４５〜４６０℃で加熱して、封止ガラスで封着する。First, an Au paste for bonding a semiconductor element is printed and fired on a silicon carbide substrate to form a metal solder layer 7 on the substrate. Next, sealing glass 6 is printed on the silicon carbide substrate and fired to attach the glass to the substrate. The lead piece 3 is placed on the upper surface of the sealing glass layer 6, and heated to a temperature higher than the softening temperature of the glass, for example, 450 to 480°C, to bond the lead piece. A semiconductor element 1 is placed on a metal solder layer 7 on a substrate.
The metal solder layer 7 is formed by placing the metal solder layer 7 on the metal solder layer 7 and bonding the semiconductor element by heating it to 350 to 450°C. The semiconductor element and the lead piece terminals are electrically connected by wires 2. Next, the cap material 5 with the sealing glass 6 is placed on it,
It is heated at 445 to 460°C and sealed with sealing glass.
これにより集積回路パッケージが作製される。封止後及
び−５５〜１５０℃の冷熱サイクル２０回を試験後、ヘ
リウムリークテストにより、リーク量を測定し、パッケ
ージの良品、不良品を判定した。This produces an integrated circuit package. After sealing and after testing 20 times of cooling and heating cycles at -55 to 150°C, the amount of leakage was measured by a helium leak test to determine whether the package was good or defective.
第１表に、各種材料の組み合わせとパッケージの良品、
不良品との判定結果を示す。Table 1 shows the combinations of various materials and the products with good packaging.
Indicates the determination result that the product is defective.
（本頁以下余白）
第１表
熱膨張係数が４１ Ｘ ｔｏ−’／ ’Ｃ１４３ＸｌＯ
−７／℃のリード材料を用いた＆ｌ ２．６．１１及び
１２のパッケージはいずれもヘリウムリーク不良をおこ
している。本発明の熱膨張係数が３９Ｘ１０−’／℃以
下のリード材料を用いたパッケージはいずれもヘリウム
リーク不良がなく、良好である。(Margins below this page) Table 1 Thermal expansion coefficient is 41 X to-'/'C143XlO
Both the &l 2.6.11 and 12 packages using -7/°C lead material had helium leak defects. All packages using the lead material of the present invention having a coefficient of thermal expansion of 39x10-'/°C or less have no helium leak defects and are in good condition.
尚、キャップ材にアルミナ材料を用いたパッケージは、
リード材料が低熱膨張係数であってもガラスにクラック
を生ずる。In addition, packages using alumina material for the cap material,
Even if the lead material has a low coefficient of thermal expansion, it will cause cracks in the glass.
第２表も第１表と同様に構成材料をかえて作製したパン
ケージのヘリウムリークテストによる良品、不良品をみ
たものである。Similarly to Table 1, Table 2 shows the results of the helium leak test of pancages manufactured using different constituent materials, and shows the good and defective products.
（本頁以下余白）
第２表
キャップ材にアルミナを用いたパッケージはいずれも封
止ガラスにクラックが発生し、不良品である（隘２０．
３６）。リード材に熱膨張係数３８Ｘ１０−７／℃以下
、ガラス材に５３Ｘ１０−７／”Ｃを、キャップ材にム
ライト、ジルコンを用いたパッケージはヘリウムリーク
不良がない（１１ｈ２３．２４．２５．３３．３４．３
５）。しかし、熱膨張係数が４１×１０−７／℃以上の
リード材料、熱膨張係数が５６×１０−７／℃のガラス
材を用いたパッケージはことごとくヘリウムリーク不良
をおこす、 （！ｌ＆１Ｌ２１．２２．２６．２７．２
８．２９．３０．３１及び３２）。(Margins below this page) Table 2 All packages that use alumina for the cap material have cracks in the sealing glass and are defective (see 20.
36). Packages that use a thermal expansion coefficient of 38X10-7/"C or less for the lead material, 53X10-7/"C for the glass material, and mullite or zircon for the cap material have no helium leak defects (11h23.24.25.33.34 .3
5). However, all packages using lead materials with a thermal expansion coefficient of 41 x 10-7/℃ or higher or glass materials with a thermal expansion coefficient of 56 x 10-7/℃ cause helium leak failure (!l&1L21.22. 26.27.2
8.29.30.31 and 32).
以上により、炭化ケイ素質セラミックスを基板に用い熱
膨張係数４５〜５５Ｘ１０−’／”Ｃの封止ガラス材を
用い、熱膨張係数３５〜５０×１０−’／℃のキャップ
材を用い、熱膨張係数４０×１０−’／’ｃ以下のリー
ドフレーム材を用いることにより、封止ガラスにクラッ
クのない、信頼性の高い集積回路パッケージが得られる
ことがわかる。As described above, using silicon carbide ceramics as a substrate, using a sealing glass material with a thermal expansion coefficient of 45 to 55 x 10-'/"C, and using a cap material with a thermal expansion coefficient of 35 to 50 x 10-'/"C, thermal expansion It can be seen that by using a lead frame material with a coefficient of 40x10-'/'c or less, a highly reliable integrated circuit package with no cracks in the sealing glass can be obtained.
第２図は炭化ケイ素質セラミックスの高熱伝導性を活か
すために、基板面に冷却フィンを接着した例である。こ
れは、半導体素子と基板表面との間の熱抵抗が７．７℃
／Ｗの特性が得られた。Figure 2 shows an example in which cooling fins are bonded to the substrate surface to take advantage of the high thermal conductivity of silicon carbide ceramics. This means that the thermal resistance between the semiconductor element and the substrate surface is 7.7°C.
/W characteristics were obtained.
第３図は１枚の炭化ケイ素質セラミックスの上に、半導
体素子を多数個付けた例である。炭化ケイ素基板の上に
シリコン配線基板を接合し、その上に半導体素子を接合
したパッケージである。この場合にもリード材料には低
熱膨張係数の材料が要求される。FIG. 3 shows an example in which a large number of semiconductor elements are attached on a single sheet of silicon carbide ceramic. This is a package in which a silicon wiring board is bonded to a silicon carbide substrate, and a semiconductor element is bonded to the silicon wiring board. In this case as well, the lead material is required to have a low coefficient of thermal expansion.
第４図は炭化ケイ素質セラミックス基板の上に、Ｃｕ導
体と絶縁材料との配線板を作製し、その上に半導体素子
を接合したパッケージである。FIG. 4 shows a package in which a wiring board of a Cu conductor and an insulating material is fabricated on a silicon carbide ceramic substrate, and a semiconductor element is bonded thereon.
このパッケージにおいてもリード材料には低熱膨張係数
の材料が要求される。In this package as well, the lead material is required to have a low coefficient of thermal expansion.
（発明の効果〕
以上説明したように、本発明によれば、炭化ケイ素質セ
ラミックスを基板に用いた集積回路パッケージにおいて
、所定の冷熱サイクルテストにさらしても封止ガラスに
亀裂が生じないものが得られるという顕著な効果を奏す
るものである。(Effects of the Invention) As explained above, according to the present invention, an integrated circuit package using silicon carbide ceramics as a substrate can be used in which the sealing glass does not crack even when subjected to a predetermined thermal cycle test. This has the remarkable effect of being obtained.
第１図〜第４図は、それぞれ本発明の集積回路パッケー
ジの異なる実施例の断面図である。
１−半導体素子、２−ボンディングワイヤ、３−リード
片、４一基板（Ｓｉｃ）、５ キャップ、６−封止ガラ
ス層、７−金属ソルダ層、シリコン配線基板、９−＝冷
却フィン、１０−接着剤、１１−フランジ、１２−・−
はんだ、１３−配線。
代理人 弁理士 平 木 祐 輔
第１図
第２図
第３図1 to 4 are cross-sectional views of different embodiments of integrated circuit packages of the present invention. 1-Semiconductor element, 2-Bonding wire, 3-Lead piece, 4-Substrate (SIC), 5-Cap, 6-Sealing glass layer, 7-Metal solder layer, Silicon wiring board, 9-=Cooling fin, 10- Adhesive, 11-flange, 12-・-
Solder, 13-Wiring. Agent Patent Attorney Yusuke Hiraki Figure 1 Figure 2 Figure 3
Claims (3)
に囲まれたケース内に、該絶縁基板に搭載された半導体
素子と、該ケース内部に導入された電気的リードの端部
と、該半導体素子及び該電気的リードの端部を接続する
接続部とが収納されている集積回路パッケージにおいて
、該絶縁基板は熱膨張係数が３５〜４０×１０＾−＾７
／℃である炭化ケイ素質セラミックスから成り、該キャ
ップは熱膨張係数が３５〜５０×１０＾−＾７／℃であ
るセラミックスから成り、該封止ガラスは熱膨張係数４
５〜５５×１０＾−＾７／℃のガラスから成り、該電気
的リードは熱膨張係数が４０×１０＾−＾７／℃以下で
ある合金からなることを特徴とする集積回路パッケージ
。(1) A semiconductor element mounted on the insulating substrate, an end of an electrical lead introduced into the case, and the semiconductor element in a case airtightly surrounded by an insulating substrate, a cap, and a sealing glass. and a connection portion for connecting the ends of the electrical leads, the insulating substrate has a coefficient of thermal expansion of 35 to 40×10^-^7.
/℃, the cap is made of ceramics with a thermal expansion coefficient of 35 to 50 x 10^-^7/℃, and the sealing glass has a thermal expansion coefficient of 4.
An integrated circuit package comprising glass having a thermal expansion coefficient of 5 to 55 x 10^-^7/°C, wherein the electrical leads are made of an alloy having a coefficient of thermal expansion of 40 x 10^-^7/°C or less.
る低融点ガラスであることを特徴とする特許請求の範囲
第１項記載の集積回路パッケージ。(2) The integrated circuit package according to claim 1, wherein the sealing glass is a low melting point glass whose sealing operation temperature is 470° C. or lower.
とを特徴とする特許請求の範囲第１項記載の集積回路パ
ッケージ。(3) The integrated circuit package according to claim 1, wherein the electrical leads are made of a Ni-Co-Fe alloy.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60181692A JPS6243155A (en) | 1985-08-21 | 1985-08-21 | Integrated circuit package |
| US06/890,533 US4729010A (en) | 1985-08-05 | 1986-07-30 | Integrated circuit package with low-thermal expansion lead pieces |
| DE8686305894T DE3672709D1 (en) | 1985-08-05 | 1986-07-31 | INTEGRATED CIRCUIT PACK. |
| EP86305894A EP0211618B1 (en) | 1985-08-05 | 1986-07-31 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60181692A JPS6243155A (en) | 1985-08-21 | 1985-08-21 | Integrated circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6243155A true JPS6243155A (en) | 1987-02-25 |
| JPH0337308B2 JPH0337308B2 (en) | 1991-06-05 |
Family
ID=16105199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60181692A Granted JPS6243155A (en) | 1985-08-05 | 1985-08-21 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6243155A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02251166A (en) * | 1989-03-24 | 1990-10-08 | Matsushita Electric Works Ltd | Semiconductor package for surface mounting |
| JPH03167858A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167850A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167859A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167852A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03173156A (en) * | 1989-11-30 | 1991-07-26 | Kyocera Corp | Package for housing semiconductor element |
| JPH03173164A (en) * | 1989-11-30 | 1991-07-26 | Kyocera Corp | Package for housing semiconductor element |
-
1985
- 1985-08-21 JP JP60181692A patent/JPS6243155A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02251166A (en) * | 1989-03-24 | 1990-10-08 | Matsushita Electric Works Ltd | Semiconductor package for surface mounting |
| JPH03167858A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167850A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167859A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03167852A (en) * | 1989-11-27 | 1991-07-19 | Kyocera Corp | Package for semiconductor-element |
| JPH03173156A (en) * | 1989-11-30 | 1991-07-26 | Kyocera Corp | Package for housing semiconductor element |
| JPH03173164A (en) * | 1989-11-30 | 1991-07-26 | Kyocera Corp | Package for housing semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0337308B2 (en) | 1991-06-05 |
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