JPS63215057A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS63215057A JPS63215057A JP62047566A JP4756687A JPS63215057A JP S63215057 A JPS63215057 A JP S63215057A JP 62047566 A JP62047566 A JP 62047566A JP 4756687 A JP4756687 A JP 4756687A JP S63215057 A JPS63215057 A JP S63215057A
- Authority
- JP
- Japan
- Prior art keywords
- glass layer
- semiconductor device
- substrate
- lead frame
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000011521 glass Substances 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000011800 void material Substances 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 22
- 239000002245 particle Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 8
- 238000010304 firing Methods 0.000 claims description 6
- 239000000155 melt Substances 0.000 claims description 4
- 238000002844 melting Methods 0.000 abstract description 10
- 230000008018 melting Effects 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 35
- 239000001307 helium Substances 0.000 description 15
- 229910052734 helium Inorganic materials 0.000 description 15
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 14
- 229910010271 silicon carbide Inorganic materials 0.000 description 14
- 239000007789 gas Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910000833 kovar Inorganic materials 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 229910000859 α-Fe Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000543 intermediate Substances 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052575 non-oxide ceramic Inorganic materials 0.000 description 1
- 239000011225 non-oxide ceramic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は新規な半導体装置−に係り、特にガラス中のボ
イドを低減した高信頼性の半導体装置及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a novel semiconductor device, and particularly to a highly reliable semiconductor device with reduced voids in glass and a method for manufacturing the same.
大電力使用の高速ロジックまたは高速メモリ用の半導体
装置の絶縁基板としてはモリブデンやベリリヤが使用さ
れている。ところが、このようなベースは、前者は特に
絶縁物構造体（例えばアルミナ）との整合が悪く、中間
介在体（例えばコバール、チュアロイ）の使用を必要と
し、後者はシリコンの整合性が悪く、また、毒性がある
という問題があった。このような欠点を補うために開発
されたものに金属アルミニウムなみの熱伝導性を有し、
かつ電気絶縁性の特性を有する炭化ケイ素質セラミクス
（以下ＳｉＣと言う）がある、このＳｉＣ焼結体を絶縁
基板とし−て、半導体素子を実装した例に、特開昭６０
−２０５３９がある。このようにＳｉＣを絶縁基板とし
て用いると熱放散性が優れ、更にシリコンとほぼ熱膨張
係数が一致しているために、ベリリヤ、モリブデンある
いはアルミナに比べ部品点数の少ない半導体装置が得ら
九ることが知られている。しかし、ＳｉＣをベースにし
たり、Ａ／Ｎを絶縁基板として使用するとき、半導体装
置として信頼性の点から有効に使用する手法が見つかっ
ていない。Molybdenum and beryllium are used as insulating substrates for semiconductor devices for high-speed logic or high-speed memory that use large amounts of power. However, such bases are difficult to use, with the former having particularly poor compatibility with insulator structures (e.g. alumina) and requiring the use of intermediates (e.g. Kovar, Tualloy), and the latter having poor compatibility with silicon and There was a problem that it was toxic. A material developed to compensate for these drawbacks has thermal conductivity comparable to that of metal aluminum.
There is a silicon carbide ceramic (hereinafter referred to as SiC) which also has electrically insulating properties, and an example of mounting a semiconductor element using this SiC sintered body as an insulating substrate is disclosed in Japanese Unexamined Patent Application Publication No. 1986-60.
There is -20539. When SiC is used as an insulating substrate in this way, it has excellent heat dissipation properties, and its coefficient of thermal expansion is almost the same as that of silicon, so it is possible to create semiconductor devices with fewer parts compared to beryllium, molybdenum, or alumina. It has been known. However, when using SiC as a base or using A/N as an insulating substrate, no method has been found for effectively using it as a semiconductor device from the viewpoint of reliability.
特開昭５８−７４５８１号公報には磁気ヘッドの製造法
としてフェライト磁性層を所定の間隔で配置し、これら
をその上部に配置しそのガラス板を加熱してその間隙に
ガラスを浸透させてフェライト磁性体をガラスによって
接合しその積層体を形成させる際に高圧ガスによってそ
の間隙にガラスを強制的に浸透させることが開示されて
いるが、本発明の半導体装置については全く記載されて
いないし、半導体装置としてのヘリウムがスリークにつ
いても全く開示されていない。JP-A-58-74581 discloses a method for manufacturing a magnetic head in which ferrite magnetic layers are arranged at predetermined intervals, these are placed on top of the ferrite magnetic layers, the glass plate is heated, and glass is infiltrated into the gaps to produce ferrite. Although it is disclosed that the glass is forcibly penetrated into the gap by high-pressure gas when bonding magnetic materials with glass to form a laminate, there is no mention of the semiconductor device of the present invention, and there is no description of the semiconductor device of the present invention. There is also no disclosure of helium leaks as a device.
これらのＳｉＣ，ＡＱＮを絶縁基板として使用した半導
体装置を試作し、実用化試験を行った。A semiconductor device using these SiC and AQN as an insulating substrate was prototyped and tested for practical use.
その結果ヘリウムリーク試験において、リーク量が多く
、かつばらつきが大きい問題があった。そこで上記リー
ク不良の問題を解決するため種々検討した結果１部材の
熱膨張係数の違いから生じる内部応力によるガラスの割
れ、あるいは部材の熱膨張とガラスの熱膨張を合せるた
めにガラス中に添加したヒラ−によって発生するボイド
、更に印刷・焼成時等に発生するボイドがリーク不良の
原因になっていることを見い出した。As a result, in the helium leak test, there were problems with a large amount of leakage and large variations. Therefore, in order to solve the problem of leak failure mentioned above, we conducted various studies and found that the glass cracks due to internal stress caused by the difference in the thermal expansion coefficient of one member, or that the glass is added to the glass to match the thermal expansion of the member and the glass. It has been found that voids generated by filler and also voids generated during printing, firing, etc. are the cause of leakage defects.
本発明の目的は、半導体装置の低融点ガラス中のボイド
を体積比で７％以下とし、かつボイドの粒径を０．１１
ｍ以下に抑制した信頼性の高い半導体装置及びその製造
方法を提供することにある。The purpose of the present invention is to reduce the volume ratio of voids in the low melting point glass of a semiconductor device to 7% or less, and to reduce the particle size of the voids to 0.11%.
It is an object of the present invention to provide a highly reliable semiconductor device in which the semiconductor device is suppressed to less than m, and a method for manufacturing the same.
本発明は、電気絶縁性基板上に搭載された半導体素子、
半導体素子からの信号を外部に取り出すリードフレーム
、リードフレームと半導体素子とを電気的に接続する細
線及び、基板上にガラス層によって接合され、且半導体
素子、細線及びリードフレームの一部を外気より遮断封
止す゛るキャップを備えた半導体装置において、ガラス
層中のボイド率が７体積％以下で、且ガラス層中のボイ
ドの最大粒径が０．１１ｍｍ以下であることを特徴とす
る半導体装置にある。The present invention provides a semiconductor element mounted on an electrically insulating substrate,
A lead frame that extracts signals from a semiconductor element to the outside, a thin wire that electrically connects the lead frame and the semiconductor element, and a glass layer bonded to the substrate, and a part of the semiconductor element, the thin wire, and the lead frame are exposed to the outside air. A semiconductor device equipped with a cap for blocking and sealing, characterized in that the void ratio in the glass layer is 7% by volume or less, and the maximum grain size of the voids in the glass layer is 0.11 mm or less. be.
更に、本発明は電気絶縁性基板上に半導体素子接合用メ
タライズ層を有し、半導体素子の信号を外部に取り出す
リードフレームが基板上にガラス側によって接合されて
いる半導体装置用基板、又は、金属又はセラミックス焼
結体からなる平板状部材の外周部全周にガラス層が設け
られている半導体装置封止用キャップにおいて、ガラス
層のボイド率が３．５体積％以下で、且ガラス層のボイ
ド最大粒径が０．８ｍｍ以下であることを特徴とするも
のである。Furthermore, the present invention provides a substrate for a semiconductor device, which has a metallized layer for bonding a semiconductor element on an electrically insulating substrate, and a lead frame for extracting signals from the semiconductor element to the outside, which is bonded to the glass side on the substrate, or a metallized layer. Or, in a semiconductor device sealing cap in which a glass layer is provided around the entire outer periphery of a flat plate-shaped member made of a ceramic sintered body, the void ratio of the glass layer is 3.5% by volume or less, and the voids in the glass layer are It is characterized by a maximum particle size of 0.8 mm or less.
本発明の半導体装置の製造法は、前述の半導体装置にお
いて、予め電気絶縁性基板上にリードフレームをガラス
層によって接合するとともに、キャップにガラス層を焼
成によって形成し、次いでリードフレームを接合した基
板及びガラス層を有する前記キャップを前記ガラス層の
溶融する温度で且ガス加圧下で加熱した後、前記加圧下
で前記ガラス層を凝固させる処理を施し、次いで基板と
キャップとをキャップに形成−された前記加圧下での加
熱温度より低い温度でガラス層を軟化させて接合し封止
することを特徴とするものである。The manufacturing method of a semiconductor device of the present invention is such that, in the semiconductor device described above, a lead frame is bonded in advance to an electrically insulating substrate with a glass layer, a glass layer is formed on the cap by firing, and then the lead frame is bonded to the substrate. and the cap having the glass layer is heated at a temperature at which the glass layer melts and under gas pressure, and then subjected to a treatment to solidify the glass layer under the pressure, and then the substrate and the cap are formed into a cap. The glass layer is softened at a temperature lower than the heating temperature under pressure, and the glass layer is bonded and sealed.
更に、本発明は、前述の基板上にメタライズ層を有し、
半導体素子の信号を外部に取り出すリードフレームが基
板上にガラス層によって接合されている半導体装置用基
板の製造法において、予め基板上に前記リードフレーム
をガラス層によって接合した後、前記リードフレームを
接合した基板に対し、又は金属又はセラミックス焼結体
からなる平板状部材の外周部全周にガラス層が設けられ
ている半導体装置封止用キャップの製造法において、予
め部材にガラス層を焼成して設けた後、その部材に対し
ガラス層が溶融する温度で且ガス加圧下で加熱し１次い
で前記加圧下でガラス層を凝固させることを特徴とする
ものである。Furthermore, the present invention has a metallized layer on the aforementioned substrate,
In a method for manufacturing a substrate for a semiconductor device in which a lead frame for extracting signals from a semiconductor element to the outside is bonded to a substrate with a glass layer, the lead frame is bonded to the substrate in advance with a glass layer, and then the lead frame is bonded. In a method for manufacturing a semiconductor device sealing cap in which a glass layer is provided on the entire outer periphery of a flat plate-like member made of a metal or ceramic sintered body, the glass layer is fired on the member in advance. After being provided, the member is heated at a temperature at which the glass layer melts and under gas pressure, and then the glass layer is solidified under the pressure.
前述の問題を解決するのには、ガラス中の亀裂やボイド
を無くすことである。亀裂に関しては部材の熱膨張係数
を揃えることが必要である。そのためにはＳｉＣ絶縁材
を基板とした場合、枠体やキャップ等の部材には４０〜
５０Ｘ１０″″７／”Ｃの熱膨張係数を有するムライト
セラミックスは金属コバールが適当で、これら部材によ
って亀裂を少なくすることを可能にした。また窒化アル
ミニウムを基板とした場合には、窒化アルミニウムやア
ルミナが適当である。A solution to the aforementioned problems is to eliminate cracks and voids in the glass. Regarding cracks, it is necessary to match the thermal expansion coefficients of the members. For this purpose, when using SiC insulating material as a substrate, parts such as frames and caps must have a
For mullite ceramics with a thermal expansion coefficient of 50X10''''7/''C, metal Kovar is suitable, and these materials have made it possible to reduce cracks.Also, when aluminum nitride is used as a substrate, aluminum nitride or alumina is appropriate.
ボイドに関しては、その発生する原因に次のよ 。Regarding voids, the causes of their occurrence are as follows.
うな事柄が考えられる。すなわち、１）印刷時の空気の
巻き込みによるもの、２）焼成時に生ずるガラス中のバ
インダーの抜けからによるもの、３）セラミックスとガ
ラスの反応によるもの、４）半導体装置の構造上、ガラ
スを厚くする必要性から、ガラスを形成するとき、印刷
時に重ね塗りを行わねばならないために、スクリーンの
メツシュ跡がボイドとなって残るなど数多くある。I can think of things like this. Namely, 1) due to the entrainment of air during printing, 2) due to the release of the binder in the glass that occurs during firing, 3) due to the reaction between ceramics and glass, and 4) due to the thickness of the glass due to the structure of the semiconductor device. Due to necessity, when forming glass, multiple coatings must be applied during printing, resulting in the mesh marks of the screen remaining as voids.
本発明者らは半導体装置を多数作製し、ガラス中のボイ
ドの粒径及びボイド率と半導体装置の気密性について検
討したところ次のことが明らかになった。すなわち、基
板上にガラスを印刷・焼成したグレーズのままのガラス
中のボイ“ドは体積比で１０〜１３％程度あり、このと
きの粒径は最大径で０．２８ｍが存在している。これを
高温・高ガス圧力下で処理（以下加圧処理という）する
とボイド率は２〜４％に少なくなり、粒径も最大で０．
０８ｍｍ と約１／３程度小さくなる。この小さくなっ
た加圧処理材を半導体装置の封止温度に再加熱しても、
ガラス中のボイドはグレーズ時の大きさに戻らず、ボイ
ド率で４〜６．５％１粒径で最大０．１ｍであった。こ
の状態での半導体装置の気密性は著しく改善され、高信
頼性の半導体装置を可能にした。The present inventors manufactured a large number of semiconductor devices and studied the particle size and void ratio of voids in glass and the airtightness of the semiconductor devices, and as a result, the following became clear. That is, the voids in the glass as a glaze obtained by printing and firing the glass on the substrate are about 10 to 13% by volume, and the maximum particle size at this time is 0.28 m. When this is treated at high temperature and high gas pressure (hereinafter referred to as pressure treatment), the void ratio is reduced to 2-4%, and the particle size is also reduced to 0.
08mm, which is about 1/3 smaller. Even if this reduced pressure-treated material is reheated to the sealing temperature of the semiconductor device,
The voids in the glass did not return to the size at the time of glazing, and the void ratio was 4 to 6.5% and the maximum particle size was 0.1 m. The airtightness of the semiconductor device in this state was significantly improved, making it possible to manufacture a highly reliable semiconductor device.
電気絶縁性基板として非酸化物系セラミックス焼結体が
好ましく、Ｓ ｉＣ，Ｓ ｉ３Ｎ４．ＡＱＮを主成分と
する焼結体、又はこれらの混合物を主成分とする焼結体
が好ましく、特にこれらのものに対しＢｅ量として０．
１〜３．０重量％（特にＢｅＯが好ましい）を含む焼結
体で、室温の熱伝導率が０．１ｃａＱ／ａｌ−８・℃以
上を有し、室温の比抵抗が１０９Ω国以上を有するもの
、更に同様に０．３ｃａＱ／ａｏｓ ・’Ｃ以上、１０
１０Ω国以上とするものが好ましい。Non-oxide ceramic sintered bodies are preferable as the electrically insulating substrate, such as SiC, Si3N4. A sintered body containing AQN as a main component or a mixture thereof is preferable, and in particular, a sintered body containing AQN as a main component or a mixture thereof is preferable, and in particular, the amount of Be for these products is 0.
A sintered body containing 1 to 3.0% by weight (especially preferably BeO), having a thermal conductivity at room temperature of 0.1 caQ/al-8・℃ or more, and a specific resistance at room temperature of 109Ω or more. 0.3caQ/aos ・'C or more, 10
It is preferable that the resistance be 10Ω or more.
半導体素子はＳｉ又は化合物半導体物質からなり、基板
上に金、半田等によって接合される。The semiconductor element is made of Si or a compound semiconductor material, and is bonded onto the substrate using gold, solder, or the like.
リードフレームにはコバール等のＦｅ−Ｎｉ−Ｃｏ系合
金のファーニコ等が用いられる。For the lead frame, Fe--Ni--Co alloy Farnico, such as Kovar, is used.
細線はリードフレームと素子とに固相接合され、素子に
はボール形成によって接合される。金、銅。The thin wire is solid state bonded to the lead frame and the device, and is bonded to the device by ball formation. gold, copper.
又はアルミニウム線等の直径５０μｍ程度の細線が用い
られる。Alternatively, a thin wire such as an aluminum wire having a diameter of about 50 μm is used.
ガラスには特に前述の非酸化物系基板に対し、ＰｂＯを
主成分とする硼珪酸鉛ガラスが好ましく。As for the glass, lead borosilicate glass containing PbO as a main component is particularly preferable for the above-mentioned non-oxide substrate.
室温付近の熱膨張係数が５０Ｘ１０″’ ？ ／−Ｃ以
下となるものが好ましく、ＢｚＯａ、ＡＬｚ○ａ、Ｓｉ
Ｏ２等が微量含有したものが好ましい。It is preferable that the thermal expansion coefficient near room temperature is 50X10'''?/-C or less, and BzOa, ALz○a, Si
Preferably, it contains a small amount of O2 or the like.
本発明における加圧処理はガラスを溶融状態として行う
もので、加圧する前に予めガラスの軟化温度付近で減圧
して焼成されたガラス層中の有機物等の揮発成分ガス成
分を除去することが好ましい、減圧は１〜１０″″４Ｉ
ＩｍＨｇ程度が好ましく、前述の加熱溶融させるまでの
昇温中に行うことができる。The pressure treatment in the present invention is carried out while the glass is in a molten state, and it is preferable to reduce the pressure in advance near the softening temperature of the glass to remove volatile gas components such as organic substances in the fired glass layer before applying pressure. , pressure reduction is 1~10''4I
The temperature is preferably about ImHg, and it can be carried out during the heating up to the above-mentioned heating and melting.
加圧処理は加熱温度及び圧力によってコン１〜ロールさ
れるもので、特に加熱温度軟化温度と基本にしてそれよ
りも高すぎても低すぎても形成されるボイドの含有量及
び大きさが違う。特に、使用されるガラスの軟化温度よ
り８０〜１２０℃高い温度範囲で、２．５〜４．０気圧
にてガス印加することが好ましい、軟化温度での加圧保
持時間は２〜１０分の短時間で好ましく、ガラスが凝固
するまで加圧するのが好ましい。Pressure treatment is controlled by heating temperature and pressure, and in particular, the content and size of voids that are formed are different depending on the heating temperature and softening temperature. . In particular, it is preferable to apply gas at a pressure of 2.5 to 4.0 atm in a temperature range 80 to 120 degrees Celsius higher than the softening temperature of the glass used.The pressure is maintained at the softening temperature for 2 to 10 minutes. It is preferable to apply pressure for a short time, and it is preferable to pressurize until the glass solidifies.
リードフレームの接合温度はガラスの軟化温度より４０
〜８０℃高い温度に加熱し、ガラス中にリードフレーム
が埋まるように荷重を加えて行われる。The bonding temperature of the lead frame is 40° higher than the softening temperature of glass.
This is done by heating the glass to a temperature higher than 80°C and applying a load so that the lead frame is buried in the glass.
キャップの封止温度は前述の加圧温度より低い温度で行
われる。それより高い温度では再びボイドが大きくなり
加圧による効果が失われてしまう。The sealing temperature of the cap is lower than the above-mentioned pressing temperature. At higher temperatures, the voids become larger again and the effect of pressurization is lost.
その温度はガラスの軟化温度より４０〜８０℃高い温度
で行い、さらに荷重を加えることによって行うのが好ま
しい、この封止工程によって加圧処理したものよりボイ
ド率及びその大きさが大きくなるので、加圧処理におけ
るこれらの条件を各コントロールしなければならない。It is preferable to carry out the process at a temperature 40 to 80 degrees Celsius higher than the softening temperature of the glass, and to apply a load, as the void ratio and size will be larger than those subjected to pressure treatment through this sealing process. Each of these conditions in the pressure treatment must be controlled.
〔実施錆 第１図は本発明に係る半導体装置の断面図である。[Execution rust FIG. 1 is a sectional view of a semiconductor device according to the present invention.
第１図においてＳｉＣに２重量％ＢｅＯを含む焼結体か
らなる絶縁基板３の一方の面上の中央部に半導体素子７
が金属ソルダ層８によって接着され、更に同面上の外周
部には、低融点ガラス層４を介して、ムライト質セラミ
ックス、又は、金属製コバール材からなる枠体１１が気
密に封着されている。また低融点ガラス層４には複数個
のリード片５が気密に封着されている。リード片５の一
端と半導体素子７との間は、Ａｕ、ＡＱ、Ｃｕ等のボン
デングワイヤ９によって電気的に接続している。更に枠
体１１の他方の面は、金属ソルダ一層、又は低融点ガラ
ス層１ｏによりキャップ６と気密に封着されている。ま
たアルミニウムなどの金属からなる冷却フィン１は冷却
能を高めたい場合に樹脂、半田等によって絶縁基板３に
取付けられる。特に、冷却フィン１は熱伝導性フィラー
で充填されたエポキシ樹脂系またはシリコーン樹脂系接
着材２によって接着されるのが好ましい。In FIG. 1, a semiconductor element 7 is placed in the center on one surface of an insulating substrate 3 made of a sintered body containing 2% by weight of BeO in SiC.
is bonded by a metal solder layer 8, and a frame 11 made of mullite ceramics or metal Kovar material is hermetically sealed to the outer peripheral portion on the same surface via a low melting point glass layer 4. There is. Further, a plurality of lead pieces 5 are hermetically sealed to the low melting point glass layer 4. One end of the lead piece 5 and the semiconductor element 7 are electrically connected by a bonding wire 9 made of Au, AQ, Cu, or the like. Furthermore, the other surface of the frame 11 is hermetically sealed to the cap 6 with a single layer of metal solder or a low melting point glass layer 1o. Further, the cooling fins 1 made of metal such as aluminum are attached to the insulating substrate 3 with resin, solder, etc. when it is desired to increase the cooling performance. In particular, it is preferable that the cooling fins 1 be bonded with an epoxy resin or silicone resin adhesive 2 filled with a thermally conductive filler.
第１図に示す本発明の半導体パッケージは次の工程に基
づいて組立てられる。（１）ＳｉＣ絶縁基板３の中央部
に金メタライズを施こす。その焼成温度は、８００〜１
０００℃程度で行われる。The semiconductor package of the present invention shown in FIG. 1 is assembled based on the following steps. (1) Apply gold metallization to the center of the SiC insulating substrate 3. The firing temperature is 800-1
It is carried out at about 000°C.
（２）ＳｉＣ絶縁基板３、枠体１１及びキャップ６（低
融点ガラス封止のときのみ）に低融点ガラス４を所定の
位置に、スクリーン印刷等の方法によリコーテイングし
、焼成する。ガラスとしては主成分としてＰｂＯである
硼珪酸鉛ガラスを用いた。(2) The low melting point glass 4 is recoated on the SiC insulating substrate 3, the frame 11, and the cap 6 (only when sealing with low melting point glass) at predetermined positions by a method such as screen printing, and fired. As the glass, lead borosilicate glass containing PbO as a main component was used.
他に微量のＢｚＯａ、Ｓ ｉ０２ 、ＡＱｚＯａを含む
。It also contains trace amounts of BzOa, S i02 , and AQzOa.
（３）外周の全周にガラス層を形成したＳｉＣ絶縁基板
の上にリード片５をのせ、ガラスの軟化温度より８０〜
１２０℃高く加熱し、リード片をガラス中に埋める。（
４）ガラス層を形成した枠体をリード片の上面にのせ軸
方向の圧力（約１００〜３００ｇ荷重）で加熱し互いに
接合され、リード片と基板とが組立てられる。このとき
の加熱温度は、ガラスの軟化温度（約３５０℃）より４
０〜８０℃高い温度が望ましい。（５）次に加圧処理を
行う。加圧処理は組立部材及びガラスを形成したキャッ
プ材を減圧中で軟化温度まで加熱し常圧に戻した後頁に
軟化温度より８０〜１２０’Ｃ高い温度に加熱・保持し
てガラスを完全に溶融させた後直ちに圧さく空気中２．
５〜４．０気圧でガラス表面を等方的に加圧する。１０
−３ｍｍＨｇの減圧下で昇温することによって有機物等
のガス成分を除去する。(3) Place the lead piece 5 on the SiC insulating substrate on which a glass layer is formed around the entire outer periphery, and
Heat to 120°C and bury the lead piece in the glass. (
4) The frame body with the glass layer formed thereon is placed on the upper surface of the lead piece and heated with pressure in the axial direction (approximately 100 to 300 g load) to join them together, thereby assembling the lead piece and the substrate. The heating temperature at this time is 4° below the softening temperature of glass (approximately 350°C).
A temperature 0 to 80°C higher is desirable. (5) Next, perform pressure treatment. Pressure treatment involves heating the assembly parts and the cap material forming the glass under reduced pressure to the softening temperature, returning to normal pressure, and then heating and holding the glass at a temperature 80 to 120'C higher than the softening temperature to completely soften the glass. Immediately after melting, press in air 2.
The glass surface is isotropically pressurized at 5 to 4.0 atmospheres. 10
Gas components such as organic substances are removed by increasing the temperature under reduced pressure of -3 mmHg.
加圧時間は数分という短時間で良く、冷却後凝固するま
で加圧される。圧力源は、圧さく空気ばかりでなく、窒
素、アルゴン等の不活性ガスでもよい。（６）絶＃基板
上に施した金メタライズ８の箇所に半導体素子７を軟ロ
ウ材などの金属ソルダーで接合する。（７）半導体素子
７とリード片５のインナーリード部（Ａ、ｕ及びＡ１等
のメタライズを施す）をワイヤボンデングする。（８）
前述によって加圧処理したキャップをガラスの軟化温度
より４０〜８０℃高い温度に加熱し、荷重１００〜３０
０ｇの圧力を加え気密に封止する封止後のガラス中のボ
イド率は６％及びガラス内ボイドの最大径は０．１ｍｍ
であった。（９）必要に応じ放熱フィン１を適切な接合
材２で接合する。The pressurization time may be as short as several minutes, and the pressure is applied until solidification after cooling. The pressure source may be not only compressed air but also an inert gas such as nitrogen or argon. (6) Semiconductor element 7 is bonded to the gold metallized portion 8 formed on the substrate using a metal solder such as soft brazing material. (7) Wire bonding the semiconductor element 7 and the inner lead portion of the lead piece 5 (metallized with A, u, A1, etc.). (8)
The cap that has been pressure-treated as described above is heated to a temperature 40 to 80 degrees Celsius higher than the softening temperature of the glass, and a load of 100 to 30
After applying 0g of pressure and sealing the glass airtight, the void ratio in the glass is 6% and the maximum diameter of the void in the glass is 0.1mm.
Met. (9) If necessary, the radiation fins 1 are bonded using an appropriate bonding material 2.
上記手法によって作製した半導体装置をヘリウムリーク
試験によりリーク量を測定した。その結果を第３図に示
す０表中、比較例は前述の加圧処理を行わないもので、
他の工程は全く同じ方法によって製造したものである。The amount of leakage of the semiconductor device manufactured by the above method was measured by a helium leak test. The results are shown in Table 0 in Figure 3, where the comparative example was not subjected to the above-mentioned pressure treatment.
The other steps were manufactured using exactly the same method.
また、半導体装置の信頼性を評価するため熱サイクル試
験を下記の条件で行ない、熱サイクル試験後にヘリウム
リーク量を測定した。熱サイクル試験は、半導体装置を
一５５℃に設定した浴槽中で２５分間保持し、室温中に
５分間放置した後、１５０”Ｃの恒温槽に２５分間保持
し、更に室温中で５分間放置するという熱サイクルで、
１５０回及び５００回の繰り返しを行った。Further, in order to evaluate the reliability of the semiconductor device, a thermal cycle test was conducted under the following conditions, and the amount of helium leakage was measured after the thermal cycle test. In the thermal cycle test, the semiconductor device was held in a bath set at -55°C for 25 minutes, left at room temperature for 5 minutes, then held in a constant temperature bath at 150"C for 25 minutes, and then left at room temperature for 5 minutes. In the thermal cycle of
150 and 500 repetitions were performed.
ヘリウムリーク試験の測定法は、半導体装置を入れた圧
力容器にヘリウムガスを封入した。内圧をゲージ圧で５
気圧とし２０時間以上保持した。The helium leak test was performed by filling a pressure vessel containing a semiconductor device with helium gas. The internal pressure is 5 in gauge pressure.
Atmospheric pressure was maintained for 20 hours or more.
その後１５０℃の恒温槽で２時間加熱、更に室温に２時
間放置し、半導体装置表面に吸着するヘリウムガスを放
出させた後、ヘリウムリーク試験機でリーク量を測定し
た。一方比較例として従来の作製方法で作製し、封止後
のガラス中のボイド率が１１％の半導体装置についても
同様に作製後のままと熱サイクル試験後のヘリウムリー
ク試験を行ない、そのリーク量を測定した。本発明の製
造方法で作製した半導体装置のリーク量は初期値で２．
８〜５．３ ｘ １０−１°ａｔｍ−ｃｃ／ ｓと小さ
く、バラツキも小さい。また、熱サイクル試験を５００
サイクル行った後においても、リーク量の変化はなく、
バラツキも少ない。従来の方法で作製した半導体装置の
へリームリーク量は初期値で３．５Ｘ １０−”〜４
、 ＯＸ Ｉ Ｏ−”ａｔｏ＋−ｃｃ／ ｓ と大き
く、バラツキも多い。さらに、熱サイクル数が１５０回
になると、リーク量は、８×１０″″９〜４Ｘ１０−７
ａｔｍ・ＣＣ／Ｓ と著しく増大し、バラツキもきわ
めて大きい、更に、５００サイクルになると貫通リーク
を生じ、半導体装置として不良となるものが見られた。Thereafter, it was heated in a constant temperature bath at 150° C. for 2 hours, and then left at room temperature for 2 hours to release the helium gas adsorbed on the surface of the semiconductor device, and then the amount of leakage was measured using a helium leak tester. On the other hand, as a comparative example, a helium leak test was similarly conducted on a semiconductor device manufactured using the conventional manufacturing method and with a void ratio of 11% in the glass after sealing, both as it was manufactured and after a thermal cycle test. was measured. The leakage amount of the semiconductor device manufactured by the manufacturing method of the present invention is 2.
It is as small as 8 to 5.3 x 10-1° atm-cc/s, and the variation is small. In addition, a heat cycle test of 500
Even after the cycle, there was no change in the amount of leakage.
There is little variation. The helium leakage amount of a semiconductor device manufactured by the conventional method is 3.5X 10-" to 4 at the initial value.
, OX I O-"ato+-cc/s, which is large and has many variations.Furthermore, when the number of thermal cycles reaches 150, the leakage amount is 8 x 10"9 to 4 x 10-7
atm.CC/S, and the variation was also extremely large.Furthermore, after 500 cycles, through leakage occurred and some semiconductor devices were found to be defective.
〔実施例２〕
第４図は各工程におけるガラス中のボイドの変化を示し
たものである。[Example 2] Figure 4 shows the change in voids in the glass in each step.
ボイドの測定は、軟Ｘ線装置を用い、試験を印加電圧１
００ｖ、印加電流２ｍＡで透過し影像を写真撮影して、
測定面積に対するボイド量を測定し、百分率（％）で表
した。試料は前述の半導体装置の製造工程に準じて、そ
れぞれ加熱処理をしたのち用いた。To measure voids, use a soft X-ray device and conduct the test with an applied voltage of 1
00V and an applied current of 2mA, and photographed the image.
The amount of voids relative to the measured area was measured and expressed as a percentage (%). Each sample was used after being subjected to heat treatment according to the manufacturing process of the semiconductor device described above.
本発明の製造工程におけるボイド率の変化は、ＳｉＣ絶
縁基板にガラスを焼成して形成した状態で１０〜１３％
ある。更にリードフレーム付けや組立の熱履歴を経ると
ボイド率は多少増加する。The change in void ratio in the manufacturing process of the present invention is 10 to 13% when glass is fired and formed on a SiC insulating substrate.
be. Furthermore, the void ratio increases to some extent when the lead frame is attached and subjected to heat history during assembly.
次いで４７５℃で６分間３気圧の加圧処理を施すことに
よってボイドは２〜４％と著しく少なくなる。その後の
Ｓｉペレット付は及び封止工程を経てもボイドの増加は
少なく４〜６．５ ％である。Next, by applying pressure treatment at 475° C. and 3 atm for 6 minutes, the voids are significantly reduced to 2 to 4%. Even after the subsequent Si pellet attachment and sealing process, the increase in voids is small and is 4 to 6.5%.
このように加圧処理によるボイド低域の効果は大きいこ
とがわかる。一方、比較例として従来の製造工程でのボ
イド率は、初期値に対し各工程を経るごとに多くなって
いる。Thus, it can be seen that the effect of the pressure treatment on the void low range is large. On the other hand, as a comparative example, the void ratio in the conventional manufacturing process increases with each process compared to the initial value.
本発明の製造工程における組立て時、加圧処理時及び封
止時のＸ線透過写真によってボイド率をｆＲ察した結果
、加圧処理によるボイド減少の効果が明瞭であることが
確認された。As a result of observing the void ratio fR using X-ray radiographs during assembly, pressure treatment, and sealing in the manufacturing process of the present invention, it was confirmed that the effect of pressure treatment in reducing voids was clear.
（実施例３〕
実施例１の手法で加熱温度及び加圧力を変えてガラス中
のボイド率の異なる第１図に示すパッケージを作製し、
前述と同様の熱サイクル試験によって１５０サイクル後
のヘリウムリーグを測定した。第５図にその結果を示す
。０印は加圧処理したもの、・印は無加圧のものである
。ヘリウムリーク量はボイド率が７％を謔えると急激に
増すことがわかる。しかし、７％以下ではリーク量の変
化は小さく封止性が高いことがわかる。尚、ボイド率が
７％以下のものはボイドの最大粒径も０．ＩＩ以下と小
さいが、ボイド率が８％以上のもののボイドの最大粒径
はかなり大きなバラツキを有していた。(Example 3) Packages shown in FIG. 1 with different void ratios in the glass were produced by changing the heating temperature and pressing force using the method of Example 1,
The helium league after 150 cycles was measured by the same thermal cycle test as described above. Figure 5 shows the results. The mark 0 indicates that the sample was subjected to pressure treatment, and the mark . indicates that no pressure was applied. It can be seen that the amount of helium leak increases rapidly when the void ratio reaches 7%. However, it can be seen that at 7% or less, the change in leakage amount is small and the sealing performance is high. In addition, when the void ratio is 7% or less, the maximum particle size of the void is also 0. Although the void ratio was small, i.e., II or less, the maximum particle diameter of voids with a void ratio of 8% or more had a considerably large variation.
実施例１の手法でガラス中のボイドの最大径の異なるパ
ッケージを作製し、熱サイクル試験１５０サイクル後の
ヘリウムリークを測定した。第６図にその結果を示す。Packages with different maximum diameters of voids in the glass were prepared using the method of Example 1, and helium leakage was measured after 150 cycles of a thermal cycle test. Figure 6 shows the results.
Ｑ印及び・印は前述と同様である。ガラス中のボイドの
最大粒径が０．１１ｍｍを越えるものが含まれるように
なると気密性は急激に悪くなることがわかる。尚、ボイ
ドの最大粒径が０．１１ｍと小さいものはボイド率も７
％以下と小さいが、それより大きい粒径を有するもので
はボイド率のバラツキも大きいものであった６（実施例
４〕
第２図は本発明に係る半導体装置の他の例を示す断面図
である０本実施例は第１図におけるものがキャリツブ６
の接合に際し、枠体１１が使用されたものであるが、こ
の枠体１１がキャップ６に凸状に全周にわたって一体に
形成されたもので、この凸部に予めガラス層が焼成され
たものである。The Q mark and the * mark are the same as above. It can be seen that when the glass contains voids with a maximum particle diameter exceeding 0.11 mm, the airtightness deteriorates rapidly. In addition, if the maximum particle size of the void is as small as 0.11 m, the void ratio is also 7.
% or less, but those with larger particle sizes had large variations in void ratio6 (Example 4) FIG. 2 is a cross-sectional view showing another example of the semiconductor device according to the present invention. In this embodiment, the one in Fig. 1 is caliber 6.
The frame 11 is used when joining the cap 6, and the frame 11 is integrally formed with the cap 6 in a convex shape over the entire circumference, and a glass layer is pre-fired on the convex part. It is.
このキャップへのガラス層の形成及び実施例１に形成さ
れたリードフレーム５を接合した絶縁基板３の加圧処理
は実施例１と同様の方法で実施し、次いでキャップ６と
基板３とを同様に接合した。The formation of a glass layer on this cap and the pressure treatment of the insulating substrate 3 to which the lead frame 5 formed in Example 1 was bonded were performed in the same manner as in Example 1, and then the cap 6 and the substrate 3 were bonded in the same manner. It was joined to.
前述と同様にヘリウムリーク試験の結果リーク量が約４
Ｘ １０ ”ａｔｅ ・ｃｃ／ ａ と少なく、ガ
ラス層中のボイド率が約６％及びボイドの最大粒径が０
．１ｍ以下であることが確認された。As mentioned above, the helium leak test results showed that the leakage amount was approximately 4
X 10 "ate cc/a", the void ratio in the glass layer is about 6%, and the maximum particle size of the void is 0.
．． It was confirmed that the distance was 1 m or less.
以上の如く、本発明の半導体装置の製造方法によれば、
ガラス中のボイドの低減と粒径を抑制することにより、
封止後の熱疲労による特性の劣化を無くする顕著な効果
が得られる。また、高熱伝導電気絶縁性のＳｉＣ基板上
にペレットを取り付け、かつベースにリードフレームと
枠体を接合し。As described above, according to the method for manufacturing a semiconductor device of the present invention,
By reducing voids in glass and controlling particle size,
A remarkable effect of eliminating deterioration of characteristics due to thermal fatigue after sealing can be obtained. In addition, the pellets are mounted on a SiC substrate with high thermal conductivity and electrical insulation, and the lead frame and frame are bonded to the base.
ペレットのボンデングバットをワイヤーでリードフレー
ムのインナーリード部と電気的に接続し、枠体にふた材
を接合封止したことにより、高速ロジックや高速メモリ
に好適な半導体装置を得ることができる。A semiconductor device suitable for high-speed logic and high-speed memory can be obtained by electrically connecting the bonding butt of the pellet to the inner lead portion of the lead frame with a wire and bonding and sealing the lid material to the frame.
第１図及び第２図は本発明に係る半導体装置の断面図、
第３図及び第４図は本発明及び比較に係る半導体装置の
ヘリウムリーク試験におけるリーク量を示すデータ、第
５図はボイド率とリーク量との関係を示す線図、第６図
はボイドの最大粒径とリーク量との関係を示す線図であ
る。
１・・・放熱フィン、３・・・電気絶縁性基板、４・・
・ガラス層、５・・・リードフレーム、６・・・キャッ
プ、７・・・第６凹1 and 2 are cross-sectional views of a semiconductor device according to the present invention,
3 and 4 are data showing the amount of leakage in helium leak tests of semiconductor devices according to the present invention and comparison, FIG. 5 is a diagram showing the relationship between the void ratio and the amount of leakage, and FIG. FIG. 3 is a diagram showing the relationship between maximum particle size and leakage amount. 1... Heat dissipation fin, 3... Electrical insulating board, 4...
・Glass layer, 5... Lead frame, 6... Cap, 7... Sixth recess
Claims (1)
体素子からの信号を外部に取り出すリードフレーム、該
リードフレームと半導体素子とを電気的に接続する細線
、及び前記基板上にガラス層によつて接合され、且前記
半導体素子、細線及びリードフレームの一部を外気より
遮断封止するキャップを備えた半導体装置において、前
記ガラス層中のボイド率が７体積％以下で、且ガラス層
中のボイドの最大粒径が０．１１ｍｍ以下であることを
特徴とする半導体装置。 ２、電気絶縁性基板上に半導体素子接合用メタライズ層
を有し、前記半導体素子の信号を外部に取り出すリード
フレームが前記基板上にガラス層によつて接合されてい
る半導体装置用基板において、前記ガラス層中のボイド
率が３．５体積％以下で、且ガラス層中のボイドの最大
粒径が０．８ｍｍ以下であることを特徴とする半導体装
置用基板。 ３、金属又はセラミックス焼結体からなる平板状部材の
外周部全周にガラス層が設けられている半導体装置用キ
ャップにおいて、前記ガラス層のボイド率が３．５体積
％以下で、且ガラス層のボイド最大粒径が０．８ｍｍ以
下であることを特徴とする半導体装置封止用キャップ。 ４、電気絶縁性基板上に搭載された半導体素子、該半導
体素子からの信号を外部に取り出すリードフレーム、該
リードフレームと半導体素子とを電気的に接続する細線
、及び前記基板上にガラス層によつて接合され、且前記
半導体素子、細線及びリードフレームの一部を外気より
遮断封止するキャップを備えた半導体装置の製造法にお
いて、予め前記基板上に前記リードフレームを前記ガラ
ス層によつて接合するとともに、前記キャップにガラス
層を焼成によつて形成し、次いで前記リードフレームを
接合した前記基板及び前記ガラス層を有する前記キャッ
プを前記ガラス層の溶融する温度で且ガス加圧下で加熱
した後、前記加圧下で前記ガラス層を凝固させる処理を
施し、次いで、前記基板とキャップとを前記キャップに
形成された前記ガラスによつて前記加圧下での加熱温度
より低い温度で前記ガラス層を軟化させて接合し前記封
止することを特徴とする半導体装置の製造法。 ５、電気絶縁性基板上に半導体素子接合用メタライズ層
を有し、前記半導体素子の信号を外部に取り出すリード
フレームが前記基板上にガラス層によつて接合されてい
る半導体装置用基板の製造法において、予め前記基板上
に前記リードフレームを前記ガラス層によつて接合した
後、前記リードフレームを接合した前記基板を前記ガラ
ス層が溶融する温度で且ガス加圧下で加熱し、次いで前
記加圧下で前記ガラス層を凝固させる処理を施すことを
特徴とする半導体装置用基板の製造法。 ６、金属又はセラミックス焼結体からなる平板状部材の
外周部全周にガラス層が設けられている半導体装置用キ
ャップの製造法において、予め前記部材にガラス層を焼
成して設けた後、前記ガラス層が溶融する温度で且ガス
加圧下で加熱し、次いで前記加圧下で前記ガラス層を凝
固させることを特徴とする半導体装置封止用キャップの
製造法。[Scope of Claims] 1. A semiconductor element mounted on an electrically insulating substrate, a lead frame for extracting signals from the semiconductor element to the outside, a thin wire electrically connecting the lead frame and the semiconductor element, and the aforementioned In a semiconductor device having a cap bonded to a substrate by a glass layer and sealing the semiconductor element, the thin wire, and a part of the lead frame from outside air, the void ratio in the glass layer is 7% by volume or less. A semiconductor device characterized in that the maximum grain size of voids in the glass layer is 0.11 mm or less. 2. A substrate for a semiconductor device, which has a metallized layer for bonding a semiconductor element on an electrically insulating substrate, and a lead frame for extracting a signal from the semiconductor element to the outside is bonded to the substrate by a glass layer. A substrate for a semiconductor device, characterized in that the void ratio in the glass layer is 3.5% by volume or less, and the maximum grain size of the voids in the glass layer is 0.8 mm or less. 3. In a cap for a semiconductor device in which a glass layer is provided around the entire outer periphery of a flat plate-like member made of a metal or ceramic sintered body, the void ratio of the glass layer is 3.5% by volume or less, and the glass layer A cap for sealing a semiconductor device, characterized in that the maximum void particle size is 0.8 mm or less. 4. A semiconductor element mounted on an electrically insulating substrate, a lead frame for extracting signals from the semiconductor element to the outside, a thin wire electrically connecting the lead frame and the semiconductor element, and a glass layer on the substrate. In the method for manufacturing a semiconductor device, the lead frame is bonded to the semiconductor element, the thin wire, and a cap for sealing a part of the lead frame from outside air. At the same time as bonding, a glass layer was formed on the cap by firing, and then the substrate to which the lead frame was bonded and the cap having the glass layer were heated at a temperature at which the glass layer melted and under gas pressure. After that, the glass layer is solidified under the applied pressure, and then the glass layer is heated at a temperature lower than the heating temperature under the applied pressure using the glass formed on the cap. 1. A method for manufacturing a semiconductor device, comprising softening, bonding, and sealing. 5. A method for manufacturing a substrate for a semiconductor device, which has a metallized layer for bonding a semiconductor element on an electrically insulating substrate, and a lead frame for extracting signals from the semiconductor element to the outside is bonded to the substrate by a glass layer. After bonding the lead frame onto the substrate in advance through the glass layer, the substrate to which the lead frame is bonded is heated under gas pressure at a temperature at which the glass layer melts, and then heated under gas pressure. A method for manufacturing a substrate for a semiconductor device, comprising performing a treatment for solidifying the glass layer. 6. In a method for manufacturing a cap for a semiconductor device in which a glass layer is provided around the entire outer periphery of a flat plate-like member made of a metal or ceramic sintered body, after the glass layer is previously fired and provided on the member, the 1. A method for manufacturing a cap for sealing a semiconductor device, comprising heating at a temperature at which a glass layer melts and under gas pressure, and then solidifying the glass layer under the pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4756687A JPH0824153B2 (en) | 1987-03-04 | 1987-03-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4756687A JPH0824153B2 (en) | 1987-03-04 | 1987-03-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63215057A true JPS63215057A (en) | 1988-09-07 |
| JPH0824153B2 JPH0824153B2 (en) | 1996-03-06 |
Family
ID=12778771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4756687A Expired - Lifetime JPH0824153B2 (en) | 1987-03-04 | 1987-03-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0824153B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012102291A1 (en) * | 2011-01-27 | 2012-08-02 | パナソニック株式会社 | Glass-embedded silicon substrate and method for manufacturing same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5241184A (en) * | 1975-09-30 | 1977-03-30 | Fuji Kobunshi Kogyo Kk | Composition of defoaming agent |
| JPS5874581A (en) * | 1981-10-26 | 1983-05-06 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Ceramic piece adhering method |
-
1987
- 1987-03-04 JP JP4756687A patent/JPH0824153B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5241184A (en) * | 1975-09-30 | 1977-03-30 | Fuji Kobunshi Kogyo Kk | Composition of defoaming agent |
| JPS5874581A (en) * | 1981-10-26 | 1983-05-06 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Ceramic piece adhering method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012102291A1 (en) * | 2011-01-27 | 2012-08-02 | パナソニック株式会社 | Glass-embedded silicon substrate and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0824153B2 (en) | 1996-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4517584A (en) | Ceramic packaged semiconductor device | |
| KR910007016B1 (en) | Components for semiconductor | |
| JP4362366B2 (en) | Method for forming air cavity package of semiconductor circuit element | |
| JPS6327860B2 (en) | ||
| JPH0261539B2 (en) | ||
| US5314842A (en) | Resin-sealed type semiconductor device and method for manufacturing the same | |
| KR100260686B1 (en) | Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity | |
| JP3336240B2 (en) | Semiconductor element mounting board | |
| JPH0741159Y2 (en) | Hermetically sealed ceramic package | |
| JPS63215057A (en) | Semiconductor device and its manufacture | |
| JPS6243155A (en) | Integrated circuit package | |
| JPH0117258B2 (en) | ||
| EP0100817A2 (en) | A hermetically sealed casing of an electrical device and process of manufacturing | |
| US4765528A (en) | Plating process for an electronic part | |
| JP2650044B2 (en) | Connection structure between components for semiconductor devices | |
| JP2000252392A (en) | Wiring board for mounting semiconductor device and its mounting structure | |
| JP3426827B2 (en) | Semiconductor device | |
| KR0168841B1 (en) | Metal electronic package and the manufacture method | |
| JP3300525B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPS61256746A (en) | Semiconductor device | |
| JP3070929B2 (en) | Package assembly method and package | |
| CA1304172C (en) | Metal electronic package | |
| JP3269420B2 (en) | Hermetic terminal and method of manufacturing the same | |
| JPH0572751B2 (en) | ||
| JPH0756886B2 (en) | Method of manufacturing semiconductor package |