JPS60202955A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60202955A
JPS60202955A JP59058273A JP5827384A JPS60202955A JP S60202955 A JPS60202955 A JP S60202955A JP 59058273 A JP59058273 A JP 59058273A JP 5827384 A JP5827384 A JP 5827384A JP S60202955 A JPS60202955 A JP S60202955A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
sealing glass
cap
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59058273A
Other languages
Japanese (ja)
Inventor
Kunizo Sawara
佐原　邦造
Kanji Otsuka
寛治 大塚
Masatoshi Seki
関　正俊
Takashi Ishida
尚 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59058273A priority Critical patent/JPS60202955A/en
Publication of JPS60202955A publication Critical patent/JPS60202955A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the generation of cracks in a sealing section, and to enable hermetic sealing by sealing a substrate manufactured by a material mainly comprising silicon carbide and a cap by amorphous sealing glass. CONSTITUTION:A pellet 3 consisting of silicon is fixed at the central section of one surface of a substrate 1 through a gold-silicon eutectic section 2. Electrode sections for the pellet 3 are bonded and connected with the inner end sections of leads 5 as external terminals by wires 4. The leads 5 are sealed hermetically under the state in which they are held between a cap 7 made of alumina or mullite and the SiC substrate 1 by sealing glass 6. The sealing glass 6 is composed of amorphous sealing glass mainly comprising lead, and has a small thermal expansion coefficient and is fixed positively.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置、特に、高密度実装を請求される半
導体装置に適用して特に有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is particularly effective when applied to semiconductor devices, and particularly to semiconductor devices that require high-density packaging.

〔背景技術〕[Background technology]

大規模集積回路（ＬＳＩ）の如き半導体装置においては
、半導体素子（半導体ベレット）はシリコン（Ｓｉ）材
料で作られているのが通常であり、この半導体ベレット
はダイボンディング、７エイスダウンボンデイング等の
方式で基板に実装される。In semiconductor devices such as large-scale integrated circuits (LSI), semiconductor elements (semiconductor pellets) are usually made of silicon (Si) material, and these semiconductor pellets are processed by die bonding, 7-eighth down bonding, etc. It is mounted on the board using this method.

ところが、通常用いられる基板はアルミナ系材料で作ら
れているので、基板の材料と半導体ベレットのシリコン
材料との間の熱膨張率の差により、半導体ペレットと基
板との間の接続部に応力が集中し、半導体ペレットの剥
離、配縁の断線の不良発生をひき起こす原因となり易い
上に、冷却のために複雑な系が要求され名という問題が
ある。However, since commonly used substrates are made of alumina-based materials, the difference in thermal expansion coefficient between the substrate material and the silicon material of the semiconductor pellet causes stress in the connection between the semiconductor pellet and the substrate. This tends to cause defects such as peeling of semiconductor pellets and disconnection of wiring, and requires a complicated system for cooling.

そこで、シリコンとの熱膨張係数の差が少ない、０．１
〜８，５重量％のベリ；リウムを含む炭化ケイ素であっ
てホットプレスにより成形された材料すなわち特開昭５
７−２５９１号公報に開示された材料を基板（以下、Ｓ
ｉＣ基板と略称する）とすることが考えられる。Therefore, the difference in thermal expansion coefficient from silicon is small, 0.1
Silicon carbide containing ~8.5% by weight of lithium and molded by hot pressing, that is, JP-A-5
The material disclosed in Publication No. 7-2591 was used as a substrate (hereinafter referred to as S
It is conceivable to use an iC board (abbreviated as an iC board).

ところが、ＳｉＣ基板を通常のアルミナ系基板用封止ガ
ラスでキャップと封着すると、ＳｉＣ基板とキャップと
の熱膨張係数の差が太きいため、制止完了後の熱処理時
や信頼性試験時、あるいは実際の製品使用時等において
封止ガラス部にり２ツクが生じ、封止後リーク不良を起
こすおそれのあることが本発明者によって見い出された
。However, when a SiC substrate is sealed with a cap using ordinary sealing glass for alumina-based substrates, there is a large difference in thermal expansion coefficient between the SiC substrate and the cap. The inventor of the present invention has discovered that when the product is actually used, two cracks may occur in the sealing glass portion, which may cause leakage defects after sealing.

また、ＳｉＣ基板に放熱フィンを取り付けて使用したい
場合、たとえば放熱フィンが熱膨張係数の大きいアルミ
ニウム材料で作られていると、ＳｉＣ基板と放熱フィン
との熱膨張係数の差が大きいので、両者の結合部にクラ
ック等が生じるという問題があることを本発明者は見い
出した。Also, if you want to use a heat dissipation fin attached to a SiC substrate, for example, if the heat dissipation fin is made of aluminum material with a large coefficient of thermal expansion, there will be a large difference in the coefficient of thermal expansion between the SiC substrate and the heat dissipation fin. The inventor has discovered that there is a problem in that cracks and the like occur at the joint.

〔発明の目的〕[Purpose of the invention]

本発明の１つの目的は、半導体装置の構成裂素間の熱膨
張係数の差圧起因するクラック等を防止し、高い信頼性
の気密封止、または放熱を行うことのできる技術を提供
することＫある。One object of the present invention is to provide a technology that can prevent cracks caused by differential pressures in thermal expansion coefficients between constituent elements of a semiconductor device and perform highly reliable hermetic sealing or heat dissipation. There is K.

本発明の他の目的は、ＳｉＣ基板とキャップとの間の封
止ガラス部のクラックを防止できる技術を提供すること
にある。Another object of the present invention is to provide a technique that can prevent cracks in the sealing glass portion between the SiC substrate and the cap.

本発明の他の目的は、ＳｉＣ基板と放熱フィンとの間の
結合部のクラックを防止できる技術を提供することにあ
る。Another object of the present invention is to provide a technique that can prevent cracks in the joint between the SiC substrate and the radiation fin.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単忙説明すれば、次の通りである。A brief summary of typical inventions disclosed in this application is as follows.

すなわち、ＳｉＣ基板とキャップとの間、およびＳｉＣ
基板と放熱フィンとの間をそれぞれ非結晶封止ガラスま
たはシリコーン系接着剤で封着することにより、被封着
物間の熱膨張係数の差を小さくし、封着部のクラックを
防止できるようにしたものである。That is, between the SiC substrate and the cap, and between the SiC
By sealing between the substrate and the heat dissipation fins using amorphous sealing glass or silicone adhesive, the difference in thermal expansion coefficient between the objects to be sealed can be reduced and cracks in the sealed portion can be prevented. This is what I did.

し実施例〕 図は本発明の一実施例による半導体装置の断面図である
。Embodiment] The figure is a sectional view of a semiconductor device according to an embodiment of the present invention.

この実施例における半導体装置の基板１はたとえば特開
昭５７−２５９１号公報に記載されている０、１〜８．
５重量％のベリリウムを含む炭化ケイ素（ＳムＣ）を主
成分とする材料で作られている。炭化ケイ素（ＳｉＣ）
は炭素（Ｃ）とケイ素（Ｓｉ、シリコン）との化合物で
、ＳｉＣの粉末にたとえば焼結助剤としての酸化ベリリ
ウム（Ｂｅ０）粉末およびバインダを混合し、粉末プレ
スで成形してこれをホットプレスにより焼結することに
より作ることができる。The substrate 1 of the semiconductor device in this embodiment is, for example, 0, 1 to 8.
It is made of a material based on silicon carbide (SmuC) containing 5% by weight of beryllium. silicon carbide (SiC)
is a compound of carbon (C) and silicon (Si). SiC powder is mixed with, for example, beryllium oxide (Be0) powder as a sintering aid and a binder, then molded using a powder press and then hot pressed. It can be made by sintering.

この基板１の一方の面（図の下面）の中央部付近忙は、
シリコン（ＳＫ）よりなるペレット３が金−シリコン（
Ａｕ−８ｉ）共晶部２を介して固着されている。ペレッ
ト３の電極部はワイヤ４により、外部端子であるリード
５の内端部とボンディングされ、電気的忙接続されてい
る。The area near the center of one side of the board 1 (lower side in the figure) is
Pellets 3 made of silicon (SK) are made of gold-silicon (
Au-8i) is fixed via the eutectic part 2. The electrode portion of the pellet 3 is bonded to the inner end portion of a lead 5, which is an external terminal, by a wire 4, and is electrically connected.

リード５は封止ガラス６により、アルミナまたはムライ
ト製キャップ７とＳｉＣ基板１との間に挾み込まれた状
態で気密制止される。封止ガラス６は、鉛を主成分とす
る非結晶封止ガラスよりなる。この封止ガラス６は熱膨
張係数が３０〜３００℃で５０±３Ｘ１０／’Ｃと小さ
いので、３０〜４００℃で３７±２Ｘ１０／”Ｃである
ＳｉＣ基板１の熱膨張係数と近く、キャップ７の熱膨張
係数（４０〜２５０℃で４６±５Ｘ１０／℃、４０〜４
００℃で５０±５Ｘ１０／’Ｃまたは４０〜８００℃で
５９±５Ｘ１０／’Ｃ）　との差も小さい。一方、リー
ド５はたとえば鉄、銅、ニッケル。The lead 5 is hermetically sealed by a sealing glass 6 while being sandwiched between a cap 7 made of alumina or mullite and the SiC substrate 1 . The sealing glass 6 is made of amorphous sealing glass containing lead as a main component. This sealing glass 6 has a small thermal expansion coefficient of 50±3X10/'C at 30 to 300°C, which is close to that of the SiC substrate 1, which is 37±2X10/'C at 30 to 400°C. Thermal expansion coefficient (46±5X10/℃ at 40-250℃, 40-4
(50±5X10/'C at 00℃ or 59±5X10/'C at 40-800℃) is also small. On the other hand, the lead 5 is made of iron, copper, or nickel, for example.

またはコバルト系の材料で作られている。また、リード
５の露出表面上には半田８が被覆されている。リード５
の熱膨張係数は、３０〜４００℃で３３〜４２Ｘ１０／
’Ｃ、または３０〜４５０℃で４５〜５１Ｘ１０−／”
Ｃである。or made of cobalt-based materials. Furthermore, the exposed surfaces of the leads 5 are coated with solder 8. lead 5
The thermal expansion coefficient of is 33~42X10/ at 30~400℃
'C, or 45-51X10-/'' at 30-450℃
It is C.

また、前記、ＳｉＣ基板１の他の面（図の上面）には、
たとえばアルミニウムを主成分とする放熱フィン１０が
シリコーン系接着剤９で固着され、ペレット３から発生
される熱をより効率的に放散するようになっている。Further, on the other surface (the upper surface in the figure) of the SiC substrate 1,
For example, heat dissipation fins 10 mainly made of aluminum are fixed with a silicone adhesive 9 to dissipate heat generated from the pellets 3 more efficiently.

このシリコーン系接着剤９はＳｉＣ基板１と放熱フィン
１０（熱膨張係数は１７５ｘｌＯ／’ｃと大きい）との
熱膨張係数差によって生じる応力を吸収することができ
るものであり、ＳｉＣ基板１と放熱フィン１０とを極め
て確実に固着できる。This silicone adhesive 9 can absorb the stress caused by the difference in thermal expansion coefficient between the SiC substrate 1 and the heat dissipation fin 10 (the coefficient of thermal expansion is as large as 175xlO/'c), and it The fins 10 can be fixed very reliably.

したがって、本実施例では、各構成要素が相互の熱膨張
係数の差ができるだけ小さくなるよう罠、かつその差を
吸収できるように組み合わせて半導体装置を構成してい
るので、良好な気密封止性および固着性等を得ることが
できる。Therefore, in this embodiment, the semiconductor device is configured so that the difference in thermal expansion coefficient between each component is as small as possible, and is combined to absorb the difference, so that good hermetic sealing is achieved. and adhesion, etc. can be obtained.

〔効　果〕〔effect〕

（１）炭化ケイ素を主成分とする材料で作られた基板と
キャップとを非結晶封止ガラスで封止したことにより、
封止部のクラック等を生じることなく確実な気密封止が
可能となり、高い信頼性を得ることができる。(1) By sealing the substrate and cap made of a material whose main component is silicon carbide with amorphous sealing glass,
Reliable airtight sealing is possible without causing cracks or the like in the sealing portion, and high reliability can be achieved.

１２）炭化ケイ素を主成分とする基板と放熱フィンとが
シリコーン系接着剤で接着されていることにより基板と
放熱フィンとの間の熱膨張係数の差を吸収でき、放熱フ
ィンの固着性および放熱性を確保することができる。12) By bonding the silicon carbide-based substrate and the radiation fins with silicone adhesive, the difference in thermal expansion coefficient between the substrate and the radiation fins can be absorbed, improving the adhesion of the radiation fins and heat radiation. It is possible to ensure sex.

（３１基板とペレットとの熱膨張係数がほぼ同じである
ので、大形のペレットを実装してもペレットクラック等
を起こすことを防止できる。(Since the thermal expansion coefficients of the No. 31 substrate and the pellets are almost the same, it is possible to prevent pellet cracks from occurring even when large pellets are mounted.

（４１炭化ケイ素を主成分とする基板は放熱性が良好で
あり、高パワーのＬＳＩの実装が可能であり、熱抵抗を
低減できる。(Substrates containing 41 silicon carbide as a main component have good heat dissipation properties, can mount high-power LSIs, and can reduce thermal resistance.

（５）　簡単な構造で前記（１１〜（４）のような優れ
た諸効果を得ることができ、半導体装置としてのコスト
パフォーマンスが著しく向上する。(5) The excellent effects described in (11 to (4)) can be obtained with a simple structure, and the cost performance as a semiconductor device is significantly improved.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、キャップや放熱フィン等の構造や熱膨張係数
を前記以外のものとすることができる。For example, the structures and thermal expansion coefficients of the cap, heat radiation fins, etc. may be other than those described above.

また、リードフレームを必ずしも使用する必要はなく、
放熱フィンを省略することもできる。Also, it is not necessary to use a lead frame,
The radiation fins can also be omitted.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるフラットタイプの半
導体装置に適用した場合について説明したが、それに限
定されるものではなく、たとえば、ＤＩＬＧ型等の他の
種類の半導体装置にも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to a flat type semiconductor device, which is the background field of application, but the invention is not limited thereto. It can also be applied to other types of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明による一実施例である半導体装置の断面図で
ある。 １・・・基板、２・・ＡｕＳｉ共晶部、３・・・ペレッ
ト、４・・・ワイヤ、５・・・リード、６・・非結晶封
止ガラス、７・・・キャップ、８・・・半田、９・・・
シリコーン系接着剤、１０・・・放熱フィン。The figure is a sectional view of a semiconductor device that is an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... AuSi eutectic part, 3... Pellet, 4... Wire, 5... Lead, 6... Amorphous sealing glass, 7... Cap, 8...・Handa, 9...
Silicone adhesive, 10...radiating fin.

Claims (1)

【特許請求の範囲】 １、炭化ケイ素を主成分とする材料で作られた基板とキ
ャップとを非結晶封止ガラスで封止してなる半導体装置
。 ２　非結晶封止ガラスが鉛を主成分とすることを特徴と
する特許請求の範囲第１項記載の半導体装置。 ８、非結晶封止ガラスの熱膨張係数が３０〜３００℃で
５０±３Ｘ１０／’ｃであることを特徴とする特許請求
の範囲第１項記載の半導体装置。 ４、　キャップがムライトよりなることを特徴とする特
許請求の範囲第１項記載の半導体装置。 ５、炭化ケイ素を主成分とする材料で作られた基板と、
キャップと、前記基板に取り付けられた放熱フィンとか
らなり、前記基板と放熱フィンとがシリコーン系接着剤
で接着されてなることを特徴とする半導体装置。 ６、放熱フィンがアルミニウムを主成分とすることを特
徴とする特許請求の範囲第５項記載の半導体装置。 ？、基板とキャップとが非結晶封止ガラスで封止されて
〜・ることを特徴とする特許請求の範囲第５項または第
６項のいずれかに記載の半導体装置。[Claims] 1. A semiconductor device in which a substrate made of a material containing silicon carbide as a main component and a cap are sealed with amorphous sealing glass. 2. The semiconductor device according to claim 1, wherein the amorphous sealing glass contains lead as a main component. 8. The semiconductor device according to claim 1, wherein the amorphous sealing glass has a thermal expansion coefficient of 50±3X10/'c at 30 to 300°C. 4. The semiconductor device according to claim 1, wherein the cap is made of mullite. 5. A substrate made of a material whose main component is silicon carbide;
1. A semiconductor device comprising a cap and a radiation fin attached to the substrate, the substrate and the radiation fin being bonded together with a silicone adhesive. 6. The semiconductor device according to claim 5, wherein the heat dissipation fin is mainly composed of aluminum. ? 7. The semiconductor device according to claim 5, wherein the substrate and the cap are sealed with an amorphous sealing glass.
JP59058273A 1984-03-28 1984-03-28 Semiconductor device Pending JPS60202955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59058273A JPS60202955A (en) 1984-03-28 1984-03-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59058273A JPS60202955A (en) 1984-03-28 1984-03-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60202955A true JPS60202955A (en) 1985-10-14

Family

ID=13079574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59058273A Pending JPS60202955A (en) 1984-03-28 1984-03-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60202955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63197343U (en) * 1987-06-11 1988-12-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63197343U (en) * 1987-06-11 1988-12-19

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