JPS61256746A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61256746A
JPS61256746A JP60097812A JP9781285A JPS61256746A JP S61256746 A JPS61256746 A JP S61256746A JP 60097812 A JP60097812 A JP 60097812A JP 9781285 A JP9781285 A JP 9781285A JP S61256746 A JPS61256746 A JP S61256746A
Authority
JP
Japan
Prior art keywords
spacer
glass
cap
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60097812A
Other languages
Japanese (ja)
Inventor
Takanobu Yamamoto
隆宣 山本
Tomiro Yasuda
安田　冨郎
Hideo Suzuki
秀夫 鈴木
Shigeru Takahashi
茂 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60097812A priority Critical patent/JPS61256746A/en
Publication of JPS61256746A publication Critical patent/JPS61256746A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce signal delay, by providing a low permittivity spacer between an SiC substrate and a cap, and penetrating a lead from a glass bonded layer between the spacer and the cap. CONSTITUTION:Au is metallized on the specified parts of a sintered substrate 3, which comprises SiC including 0.05-5wt % Be or a Be compound and has a theoritical density of 90% or more, and mullite ceramic spacer B 10, whose thermal expansion coefficient is 5.5X10<-6>/ deg.C or less at 20-400 deg.C. Glass is applied on the substrate 3 and the spacers B 10 and A 9 and temporarily burned. A lead 5 is held between the spacers A 9 and B 10. The glass is burned and bonded in an airtight manner. An Si element 7 is bonded on the Au on the substrate by soft solder, whose melting point is lower than that of the glass. After the wiring, a cap is sealed 26 to the spacer B 10 by the soft solder 11 in an airtight manner. A cooling fin 1 is bonded 27 and an insulating coat 12 is attached. In this constitution, a signal delay time due to the high permittivity of the SiC can be shortened by about 38%, and the selecting range of the glass becomes wide.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係り、特に電気絶縁性の炭化ケイ
素（Ｓｉ（ｌを使用したパッケージに好適な構造を有す
る半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure suitable for a package using electrically insulating silicon carbide (Si(l)).

〔発明の背景〕[Background of the invention]

一般にセラミックス系の絶縁基板、キャップ及び封止材
からなるパッケージによって気密に囲われた小室内に、
半導体素子並びに外部から導入されたリード片の端部と
両者を電気的に接続したワイヤとを収容した構造よりな
る集積回路バツケージは今日広く使われている。この種
のパッケージでセラミックス系の絶縁基板にはアルミナ
（Ａｔ　２０！　）が最も多く使われている。しかし、
このアルミナの熱伝導率は０．０５Ｃａｔ／ｃｒｎ−５
−Ｃ程度と銅やアルミニュウム金属などに比べて一桁以
上も低く、半導体素子の熱放散の点からは満足できる材
料ではない。このため、半導体素子の大容量化、高集積
化及び小型化を図るうえで大きな障害となっている。従
って半導体素子をとりつける絶縁基板用セラミックスは
優れた熱伝導性を有することが要求される。Generally, inside a small chamber hermetically enclosed by a package consisting of a ceramic insulating substrate, a cap, and a sealing material,
Integrated circuit packages are widely used today, and have a structure that accommodates a semiconductor element, the end of a lead piece introduced from the outside, and a wire that electrically connects the two. Alumina (At 20!) is most often used for the ceramic insulating substrate in this type of package. but,
The thermal conductivity of this alumina is 0.05Cat/crn-5
-C, which is more than an order of magnitude lower than metals such as copper and aluminum, and is not a satisfactory material from the standpoint of heat dissipation in semiconductor devices. For this reason, this is a major hindrance in achieving larger capacity, higher integration, and smaller size of semiconductor elements. Therefore, ceramics for insulating substrates on which semiconductor elements are attached are required to have excellent thermal conductivity.

このようにアルミナに勝る高熱伝導性を有する電気絶縁
性のセラミックスが要求されていたが、その要求に答え
る材料として開発されたのが、金属アルミニュウムなみ
の熱伝導性を有し、かつ電気絶縁性の特性を有する炭化
ケイ素質セラミックス（以下、ｓｉｃと言う）であった
。さらにその８ｉＣを絶縁基板とし、半導体素子を実装
したパッケージの例として第１図に示すような構造があ
る。このようにＳｉＣを絶縁基板として用いると、熱放
散性が優れているうえに、更にシリコンとほぼ熱膨張係
数が一致しているために、アルミナに比べ、部品点数が
少なくなり、信頼性が向上した。There was a demand for electrically insulating ceramics with high thermal conductivity superior to that of alumina, and the material developed to meet this demand was one that had thermal conductivity comparable to that of metallic aluminum and was electrically insulating. It was a silicon carbide ceramic (hereinafter referred to as SIC) having the following characteristics. Furthermore, there is a structure shown in FIG. 1 as an example of a package in which the 8iC is used as an insulating substrate and a semiconductor element is mounted. When SiC is used as an insulating substrate in this way, it not only has excellent heat dissipation properties, but also has a coefficient of thermal expansion that is almost the same as silicon, which reduces the number of parts and improves reliability compared to alumina. did.

上記のようにＳｉＣを絶縁基板として用いると、半導体
素子の大容量化、高集積化及び小型化が可能となるが、
ＳｉＣを汎用のパッケージとして用いるのに障害となっ
ている要因として、誘電率が大きいという問題がある。When SiC is used as an insulating substrate as described above, it is possible to increase the capacity, high integration, and miniaturize semiconductor devices.
One of the obstacles to using SiC as a general-purpose package is its high dielectric constant.

そのため高速の信号伝送を要求される配線回路に適用す
る場合に問題となってくる。また、第１図に示す構造の
パッケージでは最後の封止工程にガラスを用いているが
、そのガラス封止が絶縁基板上に半導体素子を接着して
のちに行なわれるため、高融点のガラスは使用に適しな
い。最高でも５００Ｃ以下の温度で封止可能な低融点ガ
ラスが選定されねばならない。This poses a problem when applied to wiring circuits that require high-speed signal transmission. In addition, in the package with the structure shown in Figure 1, glass is used in the final sealing process, but since the glass sealing is performed after bonding the semiconductor element onto the insulating substrate, high melting point glass is used. Not suitable for use. A low melting point glass must be selected that can be sealed at a temperature of at most 500C or less.

さらにそのガラスの熱膨張係数は、ＳｉＣ及びキャップ
材（ムライト）とほぼ一致していることが封止部の亀裂
を防ぐために必要である。この場合に要求される熱膨張
係数は（３０〜５５’１Ｘ１０−）／Ｃであることを本
発明者らは確認している。しかし現状では、このように
低融点で、かつ（４０〜５０）Ｘ１０−’／Ｃ程度の熱
膨張係数を有し、接着性に優れたガラスを得ることは容
易ではなく、生産性の点から問題となる。Furthermore, it is necessary that the coefficient of thermal expansion of the glass is approximately the same as that of SiC and the capping material (mullite) in order to prevent cracks in the sealing portion. The present inventors have confirmed that the required thermal expansion coefficient in this case is (30-55'1X10-)/C. However, at present, it is not easy to obtain glass with such a low melting point, a coefficient of thermal expansion of about (40 to 50) It becomes a problem.

〔発明の目的〕[Purpose of the invention]

本発明の目的は前記の知見に基づき、ＳｉＣを絶縁基板
に使用した場合における前記の問題点を解決した集積回
路パッケージを提供することにある。Based on the above findings, an object of the present invention is to provide an integrated circuit package that solves the above problems when SiC is used as an insulating substrate.

〔発明の概要〕[Summary of the invention]

本発明は第１図に示す構造のパッケージを試作し、実用
化を行なったが、汎用のパッケージとして種々の集積回
路に応用しようとした場合、前記のような問題に直面し
、適用が限定されるケースが生じた。そこで、従来の構
造ではリード片を８ｉＣ基板とキャップ材の間のガラス
接合層から貫通させる構造にしていたため、ＳｉＣ基板
の高誘電率である特性の影響を受け、信号遅延が問題と
なっていたことに気づき、本発明ではＳｉＣ基板とキャ
ップ材の間に低誘電率のスペーサを置き、そのスペーサ
とキャップ材の間のガラス接合層からリード片を貫通さ
せる構造にして、信号遅延の問題を解決したものである
。In the present invention, a package with the structure shown in FIG. 1 was prototyped and put into practical use. However, when trying to apply it to various integrated circuits as a general-purpose package, the above-mentioned problems were encountered, and the application was limited. A case has arisen. Therefore, in the conventional structure, the lead piece was passed through the glass bonding layer between the 8iC substrate and the cap material, which caused a problem of signal delay due to the high dielectric constant of the SiC substrate. In the present invention, a spacer with a low dielectric constant is placed between the SiC substrate and the cap material, and a lead piece is passed through the glass bonding layer between the spacer and the cap material to solve the problem of signal delay. This is what I did.

さらに最終の封止工程にガラスを用いているため、低融
点ガラスしか使用できず、生産性の点で問題となってい
ることに着目し、最終の封止工程を低温で行なえる軟ロ
ウ材を用いることができるように更に前記スペーサとキ
ャップ材の間に別のスペーサを載置した構造としたもの
である。Furthermore, since glass is used in the final sealing process, only low-melting glass can be used, which poses a problem in terms of productivity. Further, another spacer is placed between the spacer and the cap material so that the cap material can be used.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第２図及び第３図により説明
する。第２図は本発明になるパッケージの横断面を示し
たものである。第３図は第２図に示すパッケージの組立
手順を示したものである。An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 shows a cross section of the package according to the present invention. FIG. 3 shows a procedure for assembling the package shown in FIG. 2.

第２図においてＳｉＣからなる絶縁基板３の一方の面上
の中央部に半導体素子７が金属ソルダ層１１によって接
着され、更に同面上の外周部には封止用ガラス／１ｌｉ
４を介して、ムライト質セラミックスからなるスペーサ
Ａ９が気密に封着されている。更にそのスペーサＡ９の
他の面は同じ封止用ガラス層４を介して、スペーサＢＩ
Ｏと気密に封着されている。また封止用ガラス層４には
複数個のリード片５が気密に封着されている。リード片
５の一端と半導体素子７との間はボンディングワイヤ８
によって電気的に接続されている。リード片５の他端は
スペーサＡの周縁から外方に延びている。更にスペーサ
ＢＩＯの他方の面は金属ソルダ層によりキャップ６と気
密に封着されている。In FIG. 2, a semiconductor element 7 is bonded to the center of one surface of an insulating substrate 3 made of SiC with a metal solder layer 11, and a sealing glass/1li is further bonded to the outer periphery of the same surface.
A spacer A9 made of mullite ceramics is hermetically sealed via the spacer A9. Further, the other surface of the spacer A9 is connected to the spacer BI through the same sealing glass layer 4.
It is hermetically sealed with O. Further, a plurality of lead pieces 5 are hermetically sealed to the sealing glass layer 4. A bonding wire 8 is connected between one end of the lead piece 5 and the semiconductor element 7.
electrically connected by. The other end of the lead piece 5 extends outward from the periphery of the spacer A. Further, the other surface of the spacer BIO is hermetically sealed to the cap 6 by a metal solder layer.

またアルミニュウムなどの金属からなる冷却フィン１は
冷却性能を高めたい場合て絶縁基板３に取付られる。該
フィン１は熱伝導性フィシで充填されたエポキシ樹脂系
またはシリコーン樹脂系接着材によって接着されること
が望ましい。また絶縁コート１２はリード片５の保護の
ため設けるが、必ずしも必要ではない。Further, the cooling fins 1 made of metal such as aluminum are attached to the insulating substrate 3 when it is desired to improve the cooling performance. The fins 1 are preferably bonded using an epoxy resin or silicone resin adhesive filled with thermally conductive fibers. Further, although the insulating coat 12 is provided to protect the lead piece 5, it is not necessarily necessary.

第２図に示すパッケージは第３図に示す手順に基づいて
組立てる。まず絶縁基板３及びスペーサＢＩＯの所定の
部分に金メタライズを施こす。その焼成温度は通常、８
００〜１０００ｒ堤度である。The package shown in FIG. 2 is assembled based on the procedure shown in FIG. First, gold metallization is applied to predetermined portions of the insulating substrate 3 and the spacer BIO. The firing temperature is usually 8
00~1000r bank degree.

次に絶縁基板３、スペーサＡ９及びスペーサＢ１０にガ
ラスを塗付し、及焼成する。しかる後に、絶縁基板３、
スペーサＡ９及びスペーサＢＩＯを、スペーサＡとＢの
間にリード片５をはさみ、積層して、ガラス層を焼成し
、それらを気密に接合する。次に絶縁基板上に施した金
メタライズの箇所に半導体素子７を軟ロウなどの金属ソ
ルダ１１で接合する。接合時の温度はガラスの融点より
低いロウ材を用いる必要がある。更に半導体素子７とリ
ード片５の一端をワイヤボンディングした後、キャップ
６を金属ソルダ１１によりスペーサＢ１０と気密に封止
する。このよってしてパッケージを組立てた後、冷却フ
ィン１及び絶縁コート１２を取付ける。Next, glass is applied to the insulating substrate 3, spacer A9, and spacer B10, and then fired. After that, the insulating substrate 3,
Spacer A9 and spacer BIO are stacked with lead piece 5 sandwiched between spacers A and B, and the glass layer is fired to join them airtightly. Next, the semiconductor element 7 is bonded to the gold metallized portion on the insulating substrate using a metal solder 11 such as soft solder. It is necessary to use a brazing material whose temperature during bonding is lower than the melting point of glass. Furthermore, after wire bonding the semiconductor element 7 and one end of the lead piece 5, the cap 6 is hermetically sealed with the spacer B10 using the metal solder 11. After the package is assembled in this way, the cooling fins 1 and the insulation coat 12 are attached.

このように本実施例によると、リード片がムライトのス
ペーサに挾まれて置かれているため、半導体素子の信号
遅延時間はＳｉＣ基板の誘電率の影響を受けず、主とし
てムライトの誘電率の影響を受ける。８ｉＣの誘電率は
４０（室温）程度であるが、ムライトは６〜７程度であ
る。一般に信号遅延時間（ｔｏ）は次式で表わされる。According to this embodiment, since the lead pieces are placed between the mullite spacers, the signal delay time of the semiconductor element is not affected by the dielectric constant of the SiC substrate, but is mainly influenced by the dielectric constant of mullite. receive. The dielectric constant of 8iC is about 40 (at room temperature), while that of mullite is about 6 to 7. Generally, the signal delay time (to) is expressed by the following equation.

ここで １、、：遅延時間 ε　：誘電率 ｔ：配線長 Ｃ：光速 従って配線長が同じパッケージの場合には本発明（Ｃな
る構造のパッケージは従来に比べて信号遅延時間は３８
優に低減できる。Here, 1, : Delay time ε : Dielectric constant t : Wiring length C : Speed of light Therefore, in the case of packages with the same wiring length, the signal delay time of the package with structure C is 38
It can be easily reduced.

またガラスによる接合を半導体素子取付けの前に実施す
るので、半導体素子の耐熱限度の制約を受けず、使用で
きるガラスの選択範囲が広がり、誘電率が低く、かつガ
ラス封上部の信頼性や生産性が向上するようなガラスが
使用できる。In addition, since bonding with glass is performed before mounting the semiconductor element, it is not limited by the heat resistance limit of the semiconductor element, and the range of glass that can be used is expanded, the dielectric constant is low, and the reliability and productivity of the glass sealing part are improved. Glass that improves can be used.

第３図は他の実施例を示すもので、第２図に示すスペー
サＢＩＯを取り除いた構造である。本構造では半導体素
子を取り付けた後に、ガラスの封止を行なわなければな
らないので、ガラスの徨類を選択する際、半導体素子の
耐熱限度の制約を受ける。しかし構造が簡略化できるた
め、低融点で接着性に優れ、且つ低誘電率のガラスを適
用できる場合には本構造にする方が望ましい。FIG. 3 shows another embodiment, which has a structure in which the spacer BIO shown in FIG. 2 is removed. In this structure, since the glass must be sealed after the semiconductor element is attached, the selection of the glass material is subject to the heat resistance limit of the semiconductor element. However, since the structure can be simplified, this structure is preferable when glass having a low melting point, excellent adhesiveness, and a low dielectric constant can be used.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、高熱伝導性を有し、シリコンとほぼ同
じ熱膨張係数を有し、絶縁基板として理想的な材料であ
るＳｉＣが持つ唯一の短所である高誘電率である特性に
よる信号遅延時間が３８係程度に短縮でき、種々のパッ
ケージに適用可能となる。According to the present invention, the signal delay is caused by the characteristic of high dielectric constant, which is the only disadvantage of SiC, which has high thermal conductivity, has almost the same coefficient of thermal expansion as silicon, and is an ideal material as an insulating substrate. The time can be reduced to about 38 steps, and it can be applied to various packages.

更にまた、最終の封止工程をガラスに代り、金属ノルダ
とすることにより、ガラスの選択範囲が広くなり、接着
性や信頼性に優れ、且つ誘電率の小さいガラスを適用で
きる。Furthermore, by using a metal solder instead of glass in the final sealing process, the range of glass selection is widened, and glass with excellent adhesiveness and reliability and a low dielectric constant can be used.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＳｉＣを用いたパッケージの構造を示す
縦断面図、第２図は本発明になるパッケージの構造を示
す縦断面図、第３図は第２図に示すパッケージの製造手
順を示す説明図、第４図は本発明になる他の実施例を示
すパッケージの縦断面図。 ｌ・・・冷却フィン、２・・・接着剤、３・・・ＳｉＣ
絶縁基板、４・・・ガラス、５・・・リード片、６・・
・キャップ、７・・・半導体素子、８・・・ボンディン
グワイヤ、９・・・スペー？Ａ、１０・・・スペーサＢ
、１１・・・金Ｍ、７に羊　１　目 茅２　目 ＃　３　口 ｒカ゛ラスず４寸−仮燈颯〕FIG. 1 is a vertical sectional view showing the structure of a conventional package using SiC, FIG. 2 is a vertical sectional view showing the structure of the package according to the present invention, and FIG. 3 is a manufacturing procedure for the package shown in FIG. 2. FIG. 4 is a vertical sectional view of a package showing another embodiment of the present invention. l...Cooling fin, 2...Adhesive, 3...SiC
Insulating substrate, 4...Glass, 5...Lead piece, 6...
・Cap, 7... Semiconductor element, 8... Bonding wire, 9... Spacer? A, 10...Spacer B
, 11...Gold M, sheep on 7, 1st eye, 2nd eye, #3, 4 sun without callus - temporary light]

Claims (1)

【特許請求の範囲】 １、炭化ケイ素質絶縁基板及びキャップを含む複数個の
部材を接合して気密に囲われた小室内に、該基板上に載
置された半導体素子と該室外から導入されたリード片の
端部及びそれらを電気的に接続したワイヤが収容されて
なる集積回路パッケージにおいて、該基板と該キャップ
の間に一個又は複数個のスペーサを載置し、かつ該リー
ド片は該キャップと該スペーサの接合部、もしくは複数
個の該スペーサの接合部から導入されていることを特徴
とする半導体装置。 ２、スペーサの材料として室温〜４００℃での熱膨張係
数が５５×１０＾−＾６／℃以下のムライト質セラミッ
クスを用いたことを特徴とする特許請求の範囲第１項記
載の半導体装置。 ３、絶縁基板がベリリウムおよびベリリウム化合物のう
ちから選ばれた少なくとも１種をベリリウムとして０．
０５〜５重量％含むほかは実質的に炭化ケイ素からなり
、かつ理論密度の９０％以上の密度を有する焼結体であ
る特許請求の範囲第１項記載の半導体装置。 ４、リード片を間にはさんで載置されている該スペーサ
と該スペーサがガラスにより気密に接合されており、か
つ該スペーサと該キャップをガラスの融点より低い融点
を有する金属ソルダで接合したことを特徴とする特許請
求の範囲第１項記載の半導体装置。[Claims] 1. A plurality of members including a silicon carbide insulating substrate and a cap are bonded together, and a semiconductor element placed on the substrate and a semiconductor device introduced from outside the room are placed in a small chamber airtightly enclosed. In an integrated circuit package in which the ends of the lead pieces and the wires that electrically connect them are housed, one or more spacers are placed between the substrate and the cap, and the lead pieces are attached to the ends of the lead pieces. A semiconductor device characterized in that the semiconductor device is introduced from a joint between a cap and the spacer, or a joint between a plurality of spacers. 2. The semiconductor device according to claim 1, wherein a mullite ceramic having a thermal expansion coefficient of 55×10^-^6/°C or less at room temperature to 400°C is used as the material of the spacer. 3. The insulating substrate is made of beryllium and at least one selected from beryllium and beryllium compounds.
2. The semiconductor device according to claim 1, wherein the semiconductor device is a sintered body consisting essentially of silicon carbide except that it contains 05 to 5% by weight, and having a density of 90% or more of the theoretical density. 4. The spacer placed with the lead piece in between and the spacer are hermetically bonded with glass, and the spacer and the cap are bonded with a metal solder having a melting point lower than the melting point of the glass. A semiconductor device according to claim 1, characterized in that:
JP60097812A 1985-05-10 1985-05-10 Semiconductor device Pending JPS61256746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60097812A JPS61256746A (en) 1985-05-10 1985-05-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60097812A JPS61256746A (en) 1985-05-10 1985-05-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61256746A true JPS61256746A (en) 1986-11-14

Family

ID=14202169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60097812A Pending JPS61256746A (en) 1985-05-10 1985-05-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61256746A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314855A (en) * 1987-06-17 1988-12-22 Shinko Electric Ind Co Ltd Ceramic package
JPS63318146A (en) * 1987-06-20 1988-12-27 Shinko Electric Ind Co Ltd Ceramic package and manufacture thereof
US5477081A (en) * 1991-03-29 1995-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314855A (en) * 1987-06-17 1988-12-22 Shinko Electric Ind Co Ltd Ceramic package
JPS63318146A (en) * 1987-06-20 1988-12-27 Shinko Electric Ind Co Ltd Ceramic package and manufacture thereof
US5477081A (en) * 1991-03-29 1995-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package

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