JPH01220853A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH01220853A JPH01220853A JP63046576A JP4657688A JPH01220853A JP H01220853 A JPH01220853 A JP H01220853A JP 63046576 A JP63046576 A JP 63046576A JP 4657688 A JP4657688 A JP 4657688A JP H01220853 A JPH01220853 A JP H01220853A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit element
- wiring layer
- aluminum nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 17
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 15
- 239000000919 ceramic Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 3
- 230000004927 fusion Effects 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000011230 binding agent Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000005997 Calcium carbide Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- CLZWAWBPWVRRGI-UHFFFAOYSA-N tert-butyl 2-[2-[2-[2-[bis[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]amino]-5-bromophenoxy]ethoxy]-4-methyl-n-[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]anilino]acetate Chemical compound CC1=CC=C(N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)C(OCCOC=2C(=CC=C(Br)C=2)N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)=C1 CLZWAWBPWVRRGI-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は配線基板上に半導体集積回路素子を搭載した混
成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit in which a semiconductor integrated circuit element is mounted on a wiring board.
従来、この種の混成集積回路は、アルミナ（Ａｆｔ ０
３ ）を主成分とするセラミック基板上に膜厚印刷技術
もしくは薄膜パターン形成技術を以て導体配線層を形成
し、このようにして得られた配線基板上に半導体集積回
路素子を導電性ペーストあるいは絶縁性ペーストなどの
グイボンディング剤を用いて搭載し、更に半導体集積回
路素子の電極と導体配線層をワイヤーボンディングによ
り接続していた。Conventionally, this type of hybrid integrated circuit is made of alumina (Aft 0
3) A conductive wiring layer is formed on a ceramic substrate mainly composed of the following by using thick film printing technology or thin film patterning technology, and a semiconductor integrated circuit element is placed on the thus obtained wiring board using a conductive paste or an insulating paste. It was mounted using a bonding agent such as paste, and the electrodes of the semiconductor integrated circuit element and the conductor wiring layer were connected by wire bonding.
しかしながら、この構造では配線基板上の半導体集積回
路素子搭載部の周辺にボンディングワイヤを接続する導
体配線層を配置することを必要とし、半導体集積回路素
子の実装効率が低いものとなっている。However, in this structure, it is necessary to arrange a conductive wiring layer for connecting bonding wires around the semiconductor integrated circuit element mounting portion on the wiring board, resulting in a low mounting efficiency of the semiconductor integrated circuit element.
そこで、従来では第３図に示すようなフリップチップ実
装方式を利用した混成集積回路が提案されている。Therefore, conventionally, a hybrid integrated circuit using a flip-chip mounting method as shown in FIG. 3 has been proposed.
図において、１１は電気的接続を行うために半田を半球
状に盛り上げた端子電極（以下、バンプ電極という）１
２を形成した半導体集積回路素子、２１はアルミナセラ
ミック基板２２上に導体配線層２３が形成された配線基
板である。前記バンプ電極１２は配線基板２１の導体配
線層２３に溶融接続され、これにより半導体集・積回路
素子１１は配線基板２１に搭載され、かつその電気的接
続がなされている。In the figure, reference numeral 11 denotes a terminal electrode (hereinafter referred to as a bump electrode) 1 which is a hemispherical hemispherical heap of solder for electrical connection.
2 is a semiconductor integrated circuit element, and 21 is a wiring board in which a conductor wiring layer 23 is formed on an alumina ceramic substrate 22. The bump electrodes 12 are fused and connected to the conductor wiring layer 23 of the wiring board 21, so that the semiconductor integrated circuit element 11 is mounted on the wiring board 21 and electrically connected thereto.
上述した従来のフリップチップ実装方式による混成集積
回路では、ワイヤーボンディングによって実装する場合
と比較して実装効率を向上できる反面、接合部となるバ
ンプ電極１２がフレキシビリティに乏しいため、配線基
板２１と半導体集積回路素子１１の熱膨張係数の差異に
よる機械的ストレスに起因する接合不良が発生するとい
う問題がある。また配線基板と半導体集積回路素子が接
する部分が少ないために熱放散性に乏しく、放熱対策が
難しいという問題もある。In the hybrid integrated circuit using the conventional flip-chip mounting method described above, the mounting efficiency can be improved compared to mounting by wire bonding. There is a problem in that bonding failures occur due to mechanical stress due to differences in thermal expansion coefficients of the integrated circuit elements 11. Another problem is that heat dissipation is poor because there are few contact areas between the wiring board and the semiconductor integrated circuit element, making it difficult to take heat dissipation measures.
本発明は上述した接合不良及び放熱対策を改善した混成
集積回路を提供することを目的としている。An object of the present invention is to provide a hybrid integrated circuit with improved measures against the above-mentioned defective junctions and heat dissipation.
〔課題を解決するための手段］
本発明の混成集積回路は、窒化アルミニウムを主成分と
するセラミック基板上に導体配線層を形成して配線基板
を構成し、半導体集積回路素子に設けたバンプ電極を前
記導体配線層に接続して該半導体集積回路素子を前記配
線基板に搭載した構成としている。[Means for Solving the Problems] The hybrid integrated circuit of the present invention has a wiring board formed by forming a conductive wiring layer on a ceramic substrate mainly composed of aluminum nitride, and bump electrodes provided on a semiconductor integrated circuit element. is connected to the conductor wiring layer, and the semiconductor integrated circuit element is mounted on the wiring board.
〔作用］
上述した構成では、窒化アルミニウムセラミック基板の
熱膨張係数がシリコンと同等であり、かつその熱伝導率
はアルミナセラミックの５〜８倍あり、シリコンで構成
される半導体集積回路素子との間における機械的ストレ
スを解消し、かつ放熱効果を向上する。[Function] In the above-described configuration, the aluminum nitride ceramic substrate has a thermal expansion coefficient equivalent to that of silicon, and its thermal conductivity is 5 to 8 times that of alumina ceramic. This eliminates the mechanical stress caused by heat dissipation and improves the heat dissipation effect.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
図において、２は窒化アルミニウムセラミック基板であ
り、この上に導体配線層３と保護絶縁膜４を形成して配
線基板ｌを構成している。また、１１は半導体集積回路
素子であり、その表面にはバンプ電極１２を形成してい
る。そして、このバンプ電極１２を前記配線基板１の導
体配線層３に溶融接続させることにより、半導体集積回
路素子１１を配線基板ｌに搭載し、混成集積回路を構成
している。In the figure, reference numeral 2 denotes an aluminum nitride ceramic substrate, on which a conductive wiring layer 3 and a protective insulating film 4 are formed to constitute a wiring board l. Further, 11 is a semiconductor integrated circuit element, and a bump electrode 12 is formed on the surface thereof. Then, by melting and connecting the bump electrodes 12 to the conductor wiring layer 3 of the wiring board 1, the semiconductor integrated circuit element 11 is mounted on the wiring board 1, thereby forming a hybrid integrated circuit.
ここで、前記窒化アルミニウムセラミック基板２は、窒
化アルミニウム粉末に焼結助剤として酸化イツトリウム
粉末を混合し、有機バインダーを加え、ドクターブレー
ド法によって作成した厚さ２００μｍのグリーンシート
を積層した後、脱バインダーを行い１９００°Ｃで常圧
焼成して形成している。Here, the aluminum nitride ceramic substrate 2 is made by mixing yttrium oxide powder as a sintering aid with aluminum nitride powder, adding an organic binder, and laminating a green sheet with a thickness of 200 μm made by a doctor blade method. It is formed by applying a binder and firing at 1900°C under normal pressure.
このよう番こして形成される窒化アルミニウムセラミッ
ク基板１の熱膨張係数はシリコンの熱膨張係数と同等の
４．５Ｘ１０−’／ｋ、熱伝導率は１００ｗ／ｍｋであ
った。The aluminum nitride ceramic substrate 1 thus formed had a thermal expansion coefficient of 4.5×10-'/k, which is equivalent to that of silicon, and a thermal conductivity of 100 w/mk.
また、前記導体配線層３はＴｉ−Ｐｄ−Ａｕ積層膜から
なり、これを前記基板１に全面形成した後、公知の薄膜
パターン形成工程を以て所要のパターンに形成している
。The conductive wiring layer 3 is made of a Ti--Pd--Au laminated film, which is formed on the entire surface of the substrate 1 and then formed into a desired pattern using a known thin film pattern forming process.
なお、半導体集積回路素子１１はシリコンで形成され、
かつバンプ電極１２はその表面に半球状に形成されてい
ることはこれまでと同じである。Note that the semiconductor integrated circuit element 11 is made of silicon,
As before, the bump electrode 12 is formed in a hemispherical shape on its surface.
また、図示は省略するが、半導体集積回路素子１１を搭
載した配線基板１に外部端子を接続し、かつ外装樹脂に
よる封止を行って混成集積回路を形成することは言うま
でもない。Although not shown in the drawings, it goes without saying that external terminals are connected to the wiring board 1 on which the semiconductor integrated circuit element 11 is mounted and sealed with an exterior resin to form a hybrid integrated circuit.
ここで、前記窒化アルミニウムセラミック基板２の他の
製造方法として、窒化アルミニウム粉末に焼結助剤とし
て炭化カルシウム粉末を混合し、有機バインダーを加え
、ドクターブレード法によって作成した厚さ１００μｍ
のグリーンシートを積層した後、脱バインダーを行い１
９００°Ｃで常圧焼成する方法も採用できる。この窒化
アルミニウムセラミック基板の熱膨張係数は４．３Ｘ１
０−’／ｋ、熱伝導率は１６０ｗ／ｍｋであった。Here, as another method for manufacturing the aluminum nitride ceramic substrate 2, a thickness of 100 μm was prepared by mixing aluminum nitride powder with calcium carbide powder as a sintering aid, adding an organic binder, and using a doctor blade method.
After laminating the green sheets, the binder is removed and 1
A method of firing at 900°C under normal pressure can also be adopted. The thermal expansion coefficient of this aluminum nitride ceramic substrate is 4.3X1
0-'/k, and the thermal conductivity was 160 w/mk.
このようにして得られた混成集積回路を一５５°Ｃ〜１
５０°Ｃ間の温度サイクル試験により評価したところ第
２図に示すような結果が得られた。The hybrid integrated circuit thus obtained was heated to 155°C.
When evaluated by a temperature cycle test at 50°C, the results shown in FIG. 2 were obtained.
なお、ここでは、比較のために９６％アルミナセラミッ
ク基板からなる配線基板を用いた従来と同じ混成集積回
路の温度サイクル試験を同時に行っている。なお、この
９６％アルミナセラミック基板の熱膨張係数は、８Ｘ１
０−’／ｋ、熱伝導率は２０ｗ／ ｍ ｋである。For comparison, a temperature cycle test was also conducted on a conventional hybrid integrated circuit using a wiring board made of a 96% alumina ceramic board. The thermal expansion coefficient of this 96% alumina ceramic substrate is 8X1
0-'/k, and the thermal conductivity is 20w/mk.
第２図において、グラフの横軸は試験サイクル数（対数
目盛）、縦軸は累積不良率である。そして、Ａは前記実
施例によって得られた混成集積回路の試験結果、Ｂは比
較のために形成した従来型の混成集積回路の試験結果で
ある。In FIG. 2, the horizontal axis of the graph is the number of test cycles (logarithmic scale), and the vertical axis is the cumulative failure rate. A shows the test results of the hybrid integrated circuit obtained in the above embodiment, and B shows the test results of the conventional hybrid integrated circuit formed for comparison.
これより明らかなように、従来型の混成集積回路では２
００サイクル以後不良が多発するのに対し、本例のもの
は３００サイクルに至ってもなお不良の発生は皆無であ
り、その改善の効果の著しいことが明確に示されている
。As is clear from this, in conventional hybrid integrated circuits, 2
While defects frequently occur after 00 cycles, in this example, no defects occurred even after 300 cycles, clearly showing that the improvement was significant.
以上説明したように本発明は、バンプ電極を用いたフリ
ップチップ法により半導体集積回路素子の搭載を行って
いるために、実装効率の向上による高集積化が可能とな
る。As explained above, in the present invention, since semiconductor integrated circuit elements are mounted by the flip-chip method using bump electrodes, it is possible to achieve high integration by improving mounting efficiency.
また、配線基板にシリコンと同等の熱膨張係数を有する
窒化アルミニウムセラミックを用いているので、熱スト
レスに起因するバンプ電極の接合不良を抑止し、ひいて
は混成集積回路の信頼性を向上することが可能となる。In addition, since aluminum nitride ceramic, which has a coefficient of thermal expansion equivalent to that of silicon, is used for the wiring board, it is possible to prevent bonding failures of bump electrodes caused by thermal stress, thereby improving the reliability of hybrid integrated circuits. becomes.
更に、窒化アルミニウムセラミックは、従来用いられて
いるアルミナセラミック基板の５〜８倍の熱伝導率を有
しているので、この基板を通して半導体集積回路素子の
放熱効果を向上させ、かつ半導体集積回路素子の実装密
度をさらに向上することが可能となる。Furthermore, since aluminum nitride ceramic has a thermal conductivity 5 to 8 times higher than that of conventionally used alumina ceramic substrates, it can improve the heat dissipation effect of semiconductor integrated circuit elements through this substrate, and improve the thermal conductivity of semiconductor integrated circuit elements. This makes it possible to further improve the packaging density.
第１図は本発明の混成集積回路の一実施例の断面図、第
２図は本発明及び従来の混成集積回路の温度サイクル試
験結果を示す図、第３図は従来のフリップチップ実装構
造の混成集積回路の断面図である。
１・・・配線基板、２・・・窒化アルミニウムセラミッ
ク基板、３・・・導体配線層、４・・・保護絶縁層、１
１・・・半導体集積回路素子、１２・・・バンプ電極、
２１・・・配線基板、２２・・・アルミナセラミック、
２３・・・導体配線層。Fig. 1 is a cross-sectional view of an embodiment of the hybrid integrated circuit of the present invention, Fig. 2 is a diagram showing the temperature cycle test results of the inventive and conventional hybrid integrated circuits, and Fig. 3 is a diagram of the conventional flip-chip mounting structure. 1 is a cross-sectional view of a hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Wiring board, 2... Aluminum nitride ceramic substrate, 3... Conductor wiring layer, 4... Protective insulating layer, 1
1... Semiconductor integrated circuit element, 12... Bump electrode,
21... Wiring board, 22... Alumina ceramic,
23... Conductor wiring layer.
Claims (1)
に導体配線層を形成して配線基板を構成し、半導体集積
回路素子に設けたバンプ電極を前記導体配線層に接続し
て該半導体集積回路素子を前記配線基板に搭載したこと
を特徴とする混成集積回路。1. A conductive wiring layer is formed on a ceramic substrate mainly composed of aluminum nitride to form a wiring board, and bump electrodes provided on a semiconductor integrated circuit element are connected to the conductive wiring layer to form the semiconductor integrated circuit element. A hybrid integrated circuit mounted on the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63046576A JPH01220853A (en) | 1988-02-29 | 1988-02-29 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63046576A JPH01220853A (en) | 1988-02-29 | 1988-02-29 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01220853A true JPH01220853A (en) | 1989-09-04 |
Family
ID=12751127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63046576A Pending JPH01220853A (en) | 1988-02-29 | 1988-02-29 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01220853A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03259571A (en) * | 1990-03-08 | 1991-11-19 | Fujitsu Ltd | Photodetector |
-
1988
- 1988-02-29 JP JP63046576A patent/JPH01220853A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03259571A (en) * | 1990-03-08 | 1991-11-19 | Fujitsu Ltd | Photodetector |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5286927A (en) | Method of manufacturing circuit board and circuit board itself manufactured by said method | |
| JPH0332914B2 (en) | ||
| US4908696A (en) | Connector and semiconductor device packages employing the same | |
| US7110241B2 (en) | Substrate | |
| JPH0568877B2 (en) | ||
| JPH01220853A (en) | Hybrid integrated circuit | |
| JPH07162157A (en) | Multilayered board | |
| JPS6243155A (en) | Integrated circuit package | |
| JPS6016749B2 (en) | Packages for integrated circuits | |
| JP2817553B2 (en) | Semiconductor package structure and method of manufacturing the same | |
| JP2506270B2 (en) | High thermal conductivity circuit board and high thermal conductivity envelope | |
| JPH02106956A (en) | Semiconductor device and manufacture thereof | |
| JPH10242324A (en) | Electrode-built-in ceramic substrate and manufacture thereof | |
| CN107170878A (en) | The ceramic substrate and preparation method of a kind of nanometer Ag composite solder paste LED/light source | |
| JPH01205558A (en) | Hybrid integrated circuit | |
| JP2004281470A (en) | Wiring board | |
| JPH04167553A (en) | Semiconductor device | |
| JP2004288661A (en) | Wiring board | |
| JP2004014995A (en) | Thermoelectric transformation module and its manufacturing method | |
| JP2000236034A (en) | Package for electronic component | |
| JP2000114442A (en) | Package for electronic part | |
| JP3148941B2 (en) | Ceramic circuit board | |
| JPH0636601Y2 (en) | Circuit board | |
| JP3931360B2 (en) | Thick film multilayer substrate | |
| JP2798188B2 (en) | Semiconductor device test equipment |