JPH02251166A - Semiconductor package for surface mounting - Google Patents
Semiconductor package for surface mountingInfo
- Publication number
- JPH02251166A JPH02251166A JP7364989A JP7364989A JPH02251166A JP H02251166 A JPH02251166 A JP H02251166A JP 7364989 A JP7364989 A JP 7364989A JP 7364989 A JP7364989 A JP 7364989A JP H02251166 A JPH02251166 A JP H02251166A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- printed wiring
- wiring board
- heat
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 230000017525 heat dissipation Effects 0.000 claims description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 241000272168 Laridae Species 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- ZBTDWLVGWJNPQM-UHFFFAOYSA-N [Ni].[Cu].[Au] Chemical compound [Ni].[Cu].[Au] ZBTDWLVGWJNPQM-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、半導体搭載用に用いられる表面実装用の半
導体パッケージに係る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a surface mounting semiconductor package used for mounting a semiconductor.
［従来の技術］
プリント配線板による表面実装用の半導体パソケジとし
てプリント配線板に寸法の短いピンを挿入した特殊なビ
ングリッドアレイ（ＰＧＡ）やプリント配線板の端面に
外部端子を直接配設したりドレスチップキャリア（ＰＬ
ＣＣ）が知られてし・る。しかし、前者にあっては、マ
ザーボード上の回路導体との接続箇所の位置決めが困難
な上に接続した後の接続確認が電気的にしかできない、
後者にあっては、マザーホードの回路導体にＰＬＣＣを
直接接続するためＰＬＣＣの端面の外部端子間に短絡を
生じないように実装するのが困難な上に、マザーボード
の変形によりＰＬＣＣがはずれやすく、また、ＰＬＣＣ
が熱伝導性の悪いマザボードに殆ど接して実装されるの
で放熱性が著しく悪くなると言う問題があった。[Prior art] As a semiconductor package for surface mounting using a printed wiring board, a special bin grid array (PGA) in which short pins are inserted into the printed wiring board, and external terminals are directly arranged on the end surface of the printed wiring board. Dress chip carrier (PL
CC) is known. However, in the former case, it is difficult to position the connection point with the circuit conductor on the motherboard, and the connection can only be confirmed electrically after connection.
In the latter case, since the PLCC is directly connected to the circuit conductor of the motherboard, it is difficult to mount the PLCC without causing a short circuit between the external terminals on the end face of the PLCC, and the PLCC is easily detached due to deformation of the motherboard. , PLCC
There was a problem in that the heat dissipation performance was significantly deteriorated because it was mounted almost in contact with the motherboard, which had poor thermal conductivity.
〔発明が解決しようとする課題］
マザーボードへの実装が容易で実装後の検査確認が行い
易く、マザーボードの変形にも追随しはずれることがな
い表面実装用パッケージを提供することにある。[Problems to be Solved by the Invention] It is an object of the present invention to provide a surface mounting package that can be easily mounted on a motherboard, is easy to inspect and confirm after mounting, and does not come off even when the motherboard is deformed.
〔課題を解決するための手段］
本発明に係る半導体パッケージは、前記の課題を解決す
るため絶縁層とこの絶縁層の表面に配設した導電パター
ンとからなるプリント配線板の外側に突出した金属の薄
板条片から形成された外部端子と前記導電パターンとが
プリント配線板上で電気的に接続固着されたことを特徴
とする表面実装用半導体パッケージを提供することにあ
る。[Means for Solving the Problems] In order to solve the above-mentioned problems, a semiconductor package according to the present invention has a metal protruding to the outside of a printed wiring board consisting of an insulating layer and a conductive pattern disposed on the surface of the insulating layer. An object of the present invention is to provide a semiconductor package for surface mounting, characterized in that an external terminal formed from a thin plate strip and the conductive pattern are electrically connected and fixed on a printed wiring board.
以下図面に基づいて詳しく説明する。第１図は本発明の
一実施例に係る表面実装用半導体パッケジの斜視図で第
２図はそのＸ−Ｙ断面図である。A detailed explanation will be given below based on the drawings. FIG. 1 is a perspective view of a surface mounting semiconductor package according to an embodiment of the present invention, and FIG. 2 is an X-Y sectional view thereof.
第２図の表面実装用半導体パッケージは、絶縁層１及び
絶縁層１の一方の表面に配設した導電パクン２と半導体
チップ７搭載用の第１の凹部６とが形成されてなるプリ
ント配線板３の端部において、−例をあげれば厚−！ｙ
０．１２ｍｍ、幅０．５ｍｍの金属の薄板条片からなる
外部端子５の−・端と前記導電パターン２とを電気的に
接続固着した構成を備え、外部端子５の他の一端を半導
体パシケジをマザーボード４に表面実装し易い様に鉤状
（ガルウィング）に曲げ加工がされている。このためマ
ザーボード４と半導体パッケージの外部端子５との表面
実装箇所が容易に観察でき実装も検査も行いやすい。さ
らに、外部端子５が金属の薄板条片からなるためマザー
ボード４の変形に対して緩衝材として作用する。したが
って、マザーボド４に表面実装された半導体パッケージ
はマザボード４からはずれない。半導体チップ７搭載用
の第１の凹部６は、本件パッケージを薄く作るための配
慮である。さらに、半導体チップ７が搭載されるプリン
ト配線板３の表面にはワイヤー８で半導体チップ７に接
続する導電パターン２を包囲するように半導体封止用樹
脂材料の流れ止め用の枠９が四角形状に形成されている
。なお、枠９の形状は特に四角形に限定するものではな
く円形などでも良い。The surface mounting semiconductor package shown in FIG. 2 is a printed wiring board formed with an insulating layer 1, a conductive pad 2 disposed on one surface of the insulating layer 1, and a first recess 6 for mounting a semiconductor chip 7. At the end of 3 - for example, the thickness -! y
The - end of the external terminal 5 made of a thin metal strip with a width of 0.12 mm and a width of 0.5 mm is electrically connected and fixed to the conductive pattern 2, and the other end of the external terminal 5 is connected to a semiconductor package. It is bent into a hook shape (gull wing) so that it can be easily surface mounted on the motherboard 4. Therefore, the surface mounting location between the motherboard 4 and the external terminals 5 of the semiconductor package can be easily observed, making mounting and inspection easy. Furthermore, since the external terminals 5 are made of thin metal strips, they act as a buffer against deformation of the motherboard 4. Therefore, the semiconductor package surface-mounted on the motherboard 4 does not come off the motherboard 4. The first recess 6 for mounting the semiconductor chip 7 is a consideration for making the present package thin. Further, on the surface of the printed wiring board 3 on which the semiconductor chip 7 is mounted, a rectangular frame 9 for preventing the flow of the resin material for semiconductor sealing is provided so as to surround the conductive pattern 2 connected to the semiconductor chip 7 with the wire 8. is formed. Note that the shape of the frame 9 is not particularly limited to a rectangular shape, and may be circular or the like.
第３図の表面実装用半導体パッケージは、一端が前記導
電パターン２と電気的に接続固着された金属の薄板条片
からなる外部端子５で他の一端は半導体パッケージがマ
ザーボード４に表面実装した時のマザーボード４に占め
る実装面積を縮小化するためにＪ型に外部端子５が曲げ
加工がされたものであり、外部端子５が可撓性に優れた
金属の薄板条片からなるためマザーボード４の変形に対
して追従する作用を有する。したがって、マザボード４
に表面実装された半導体パッケージははずれない。The semiconductor package for surface mounting shown in FIG. In order to reduce the mounting area occupied by the motherboard 4, the external terminals 5 are bent into a J-shape. It has the effect of following deformation. Therefore, motherboard 4
Surface-mounted semiconductor packages cannot be removed.
第４図の表面実装用半導体パッケージは、絶縁層ｌに埋
設された熱伝導板１０を備え、この熱伝導板１０の一方
の表面は絶縁層１に形成された第１の凹部６の底面とな
り半導体チップ７の搭載面として露出し、他方の表面は
放熱用として絶縁層１に形成された第２の凹部１１の底
面となり放熱面としてマザーボード４と反対側で外部に
露出し、第１の凹部６の底面の熱伝導板１０に搭載した
半導体チップ７の発生する熱は熱伝導板１０に吸収され
第２の凹部１１の底面の熱伝導板１０から外気中へ放熱
するので内部にこもることがない。The surface mounting semiconductor package shown in FIG. 4 includes a heat conductive plate 10 embedded in an insulating layer 1, and one surface of this heat conductive plate 10 serves as the bottom surface of a first recess 6 formed in the insulating layer 1. The other surface is exposed as a mounting surface for the semiconductor chip 7, and the other surface is the bottom surface of the second recess 11 formed in the insulating layer 1 for heat radiation, and is exposed to the outside on the side opposite to the motherboard 4 as a heat radiation surface. The heat generated by the semiconductor chip 7 mounted on the heat conduction plate 10 on the bottom surface of the second recess 11 is absorbed by the heat conduction plate 10 and radiated into the outside air from the heat conduction plate 10 on the bottom surface of the second recess 11, so that it is not trapped inside. do not have.
第２の凹部１１の底面に露出した放熱面に放熱体１２を
取付けると放熱効果がさらに高まる。この放熱体１２は
頂片部１３に突条１４を多数有し、この頂片部１３を支
える金座１５を設けて構成され、この構成により放熱面
の拡大を回っている。When the heat radiator 12 is attached to the heat radiating surface exposed at the bottom of the second recess 11, the heat radiating effect is further enhanced. The heat radiating body 12 has a large number of protrusions 14 on the top piece 13, and is provided with a metal washer 15 that supports the top piece 13. This structure allows the heat radiating surface to be enlarged.
したがって、第１の凹部６の底面の熱伝導板１０に搭載
した半導体チップ７の発生する熱は熱伝導板１０に吸収
され内部にこもることなく外部に突き出した放熱体１２
へと移動し、この放熱体１２の表面積の拡大された放熱
体１２の頂片部１３から空気中に一層効果的に放熱でき
る。さらに、金属の薄板条片からなる外部端子５の一端
には導電パターン２と面接する第１の水平片１６を設げ
て電気的に接続固着され、この第１の水平片１６に延設
された垂直成分を有する縦片１７を設けてプリント配線
板３を受げ、さらに、他端にはこの縦片１７に延設され
た上記第１の水平片■６と反対向きの第２の水平片１８
を設けて本生導体パソケジがマザーボード４に表面実装
し易い鉤状（ガルウィング）に曲げ加工がされている。Therefore, the heat generated by the semiconductor chip 7 mounted on the heat conduction plate 10 on the bottom surface of the first recess 6 is absorbed by the heat conduction plate 10 and is not trapped inside, but instead is transferred to the heat radiator 12 that protrudes outside.
, and the heat can be more effectively radiated into the air from the top piece portion 13 of the heat radiator 12, which has an enlarged surface area. Further, one end of the external terminal 5 made of a thin metal strip is provided with a first horizontal piece 16 that faces the conductive pattern 2 and is electrically connected and fixed, and the external terminal 5 is provided with a first horizontal piece 16 extending into the first horizontal piece 16. A vertical piece 17 having a vertical component such as Piece 18
The actual conductor path cage is bent into a hook shape (gull wing) so that it can be easily surface-mounted on the motherboard 4.
したがって、外部端子５がプリント配線板３を受ける形
状のため半導体パッケージが重くなっても、熱が加わり
接続固着部分が軟化した場合でもプリント配線板３が外
部端子５からはずれるのを阻止することができる。さら
に、半導体チップ７が搭載されるプリント配線板の表面
にはワイヤー８で半導体チップ７に接続する導電パター
ン２を包囲して半導体封止用樹脂材料の流れ止め用の枠
９が形成されている。Therefore, even if the semiconductor package becomes heavy due to the shape in which the external terminals 5 receive the printed wiring board 3, even if the connection fixing portion becomes soft due to the application of heat, it is possible to prevent the printed wiring board 3 from coming off from the external terminals 5. can. Further, on the surface of the printed wiring board on which the semiconductor chip 7 is mounted, a frame 9 is formed to surround the conductive pattern 2 connected to the semiconductor chip 7 with a wire 8 and to prevent the flow of the semiconductor sealing resin material. .
第５図の表面実装用半導体パッケージは、絶縁Ｎ１に埋
設された熱伝導板１０を備え、この熱伝導板１０の一方
の表面はプリント配線板３に形成された半導体チップ７
搭載用の第１の凹部６の底面として露出し、他方の表面
は放熱用としてプリント配線板３に形成された第２の凹
部１１の底面となりマザーホード４と反対側に露出し放
熱効果を高めている。この効果はスルホール導電路１９
を介してプリント配線板３の導電パターン２に、該導電
パターン２と反対側に形成された導電端子２０に接続し
、この導電端子２０に金属の薄板条片からなる外部端子
５の一端の第１の水平片１６とを電気的に接続固着し、
外部端子５の他端は半導体パッケージとしてマザーボー
ト４に実装し易い様に第１の水平片１６と第２の水平片
１８を継片１７に互いに逆方向に折曲形成されている。The surface mounting semiconductor package shown in FIG. 5 includes a heat conductive plate 10 embedded in an insulation N1, and one surface of this heat conductive plate 10 is connected to a semiconductor chip 7 formed on a printed wiring board 3.
It is exposed as the bottom surface of the first recess 6 for mounting, and the other surface becomes the bottom surface of the second recess 11 formed in the printed wiring board 3 for heat radiation, and is exposed on the side opposite to the motherboard 4 to enhance the heat radiation effect. There is. This effect is due to the through-hole conductive path 19
is connected to the conductive pattern 2 of the printed wiring board 3 through the conductive terminal 20 formed on the opposite side of the conductive pattern 2, and to this conductive terminal 20, one end of an external terminal 5 made of a thin metal strip is connected. electrically connect and fix the horizontal piece 16 of 1,
The other end of the external terminal 5 is formed by bending a first horizontal piece 16 and a second horizontal piece 18 into a joint piece 17 in opposite directions so that it can be easily mounted on the motherboard 4 as a semiconductor package.
外部端子５を導電パターン２に接続するスルボール導電
路１９を介して導電パターン２と反対側の導電端子２０
に接続固着する係る構成によって半導体千ツブ７を塔載
した面の導体パターン２がプリント配線板３の端部に展
設されていない場合でも外部端子５を端部に取りつける
ことができる点で有効である。さらに、第２の凹部１１
に露出した熱伝導板１０は導電パターン２と反対側に形
成された表面の導体２１に金属層でなる放熱体１３を介
して接続一体化されている。したがって第１の凹部６の
底面の熱伝導板１０に塔載した半導体チップ７から発生
する熱は、熱伝導板ＩＯに吸収され熱伝導板１０と接続
一体化した金属層でなる放熱体１３へと移動する。した
がって、金属層でなるこの放熱体１３の表面積の拡大に
より空気中に一層効果的に放熱できる。A conductive terminal 20 on the side opposite to the conductive pattern 2 is connected to the conductive pattern 2 via a through-ball conductive path 19 that connects the external terminal 5 to the conductive pattern 2.
This structure is effective in that the external terminal 5 can be attached to the end of the printed wiring board 3 even if the conductor pattern 2 on the surface on which the semiconductor tube 7 is mounted is not extended to the end of the printed wiring board 3. It is. Furthermore, the second recess 11
The exposed heat conductive plate 10 is integrally connected to a conductor 21 formed on the surface opposite to the conductive pattern 2 via a heat radiator 13 made of a metal layer. Therefore, the heat generated from the semiconductor chip 7 mounted on the heat conduction plate 10 on the bottom surface of the first recess 6 is absorbed by the heat conduction plate IO and transferred to the heat dissipation body 13 made of a metal layer connected and integrated with the heat conduction plate 10. and move. Therefore, by increasing the surface area of this heat sink 13 made of a metal layer, heat can be more effectively radiated into the air.
次に、表面実装用半導体パッケージの使用材料について
述べる。第１図から第４図の表面実装用半導体パッケー
ジを構成するプリント配線板３の絶縁層１、半導体封止
用樹脂材料の流れ止め用の枠９としては、基材に樹脂を
含浸乾燥して得られたプリプレグの樹脂を硬化した絶縁
材料が用いられる。ここで絶縁層１と枠９の樹脂として
は耐熱性、耐湿性に優れかつ樹脂純度、特にイオン性不
純物の少ないものが好ましい。具体的にはエポキシ樹脂
、ポリイミド樹脂、フッソ樹脂、フエノル樹脂、ＰＰＯ
樹脂などの樹脂が適している。なお絶縁層１と枠９の基
材としては、紙よりガラス繊維などの無機材料の方が耐
熱性、耐湿性などに優れ好ましい。Next, the materials used in the surface-mount semiconductor package will be described. The insulating layer 1 of the printed wiring board 3 constituting the surface mounting semiconductor package shown in FIGS. 1 to 4 and the frame 9 for preventing the flow of the resin material for semiconductor encapsulation are made by impregnating a resin into a base material and drying it. An insulating material obtained by curing the resin of the obtained prepreg is used. Here, the resin for the insulating layer 1 and the frame 9 is preferably one that has excellent heat resistance and moisture resistance, and has high resin purity, particularly low ionic impurities. Specifically, epoxy resin, polyimide resin, fluorocarbon resin, phenolic resin, PPO
Resin such as resin is suitable. As the base material for the insulating layer 1 and the frame 9, an inorganic material such as glass fiber is preferable to paper because it has superior heat resistance and moisture resistance.
絶縁層１の表面に配設された導電パターン２としては銅
、真鍮、アルミニウム、鉄、ステンレスなどから適宜選
択して適用でき、中でも銅が導電性に優れ特に好ましい
。この導電パターン２を形成するにあたっては、アディ
ティブ法、ザブトラクチイブ法などの種々の方法が用い
られる。The conductive pattern 2 disposed on the surface of the insulating layer 1 can be appropriately selected from copper, brass, aluminum, iron, stainless steel, etc. Among them, copper is particularly preferred because of its excellent conductivity. In forming this conductive pattern 2, various methods such as an additive method and a subtractive method are used.
外部端子５としては、銅、りん青銅、アルミニウム、鉄
、４２アロイ（Ｎ ｉ ４２％のＮｉ−Ｆｅ合金）など
の金属の薄板から得られた厚み０．０８〜２ｍｍ、幅０
．１〜２ｍｍの金属の薄板条片から適宜選択して適用で
き、中でも４２７０イが熱膨張係数が小さ（、強度の大
きい点で優れている。The external terminal 5 is made of a thin plate of metal such as copper, phosphor bronze, aluminum, iron, 42 alloy (Ni-Fe alloy with 42% Ni), and has a thickness of 0.08 to 2 mm and a width of 0.
．． Appropriate metal thin plate strips of 1 to 2 mm can be selected and used, and among them, 4270I is excellent in that it has a small coefficient of thermal expansion (and high strength).
熱伝導板１０としては、銅、アルミニウム、鉄、ニッケ
ル、などの金属材料が適用でき、銅、アルミニウムが高
い放熱性を有するので好ましい。Metal materials such as copper, aluminum, iron, and nickel can be used as the heat conductive plate 10, and copper and aluminum are preferable because they have high heat dissipation properties.
放熱体１３を構成する頂片部に突条を有し一体化した台
座を持つものとしては、銅、りん青銅、アルミニウム、
鉄、４２アロイ（Ｎ ｉ ４２％のＮｉ−Ｆｃ合金）、
亜鉛などの金属から形成されたもの、金属層としては金
、銀、銅、ニッケル、半田などから適宜選択して適用で
き、前者では中でもアルミニウムが軽量で熱伝導率が大
さく、強度の大きい点で、また、後者では銅−ニッケル
ー金のメツキによる金属層が熱伝導率が大きく、経年変
化が少なくパッケージを薄くできる点で特に優れ好まし
い。The heat dissipating body 13 having a protrusion on the top piece and an integrated base includes copper, phosphor bronze, aluminum,
Iron, 42 alloy (Ni-Fc alloy with 42% Ni),
It is made of metal such as zinc, and the metal layer can be selected from gold, silver, copper, nickel, solder, etc. Among the former, aluminum is lightweight, has high thermal conductivity, and is strong. In the latter case, a metal layer made of copper-nickel-gold plating is particularly preferable because it has high thermal conductivity, is less likely to change over time, and allows the package to be made thinner.
本発明は叙述の如く半導体パッケージにおいて金属の薄
板条片から形成される可撓性を有する外部端子の一端を
プリント配線板の端部において導電パターンと電気的に
接続固着し、外部端子の他の一端をプリント配線板の外
側に突出して形成してなるので、マザーボードと半導体
パッケージの外部端子との表面実装箇所が容易に視覚、
観察でき実装、検査が行い易い。さらに、外部端子がマ
ザーボードの変形に対して緩衝材として作用しマザーボ
ードに表面実装された半導体パッケージははずれないと
言う効果も有する。As described above, in a semiconductor package, the present invention electrically connects and fixes one end of a flexible external terminal formed from a thin metal strip to a conductive pattern at the end of a printed wiring board, and Since one end is formed to protrude outside the printed wiring board, the surface mounting area between the motherboard and the external terminals of the semiconductor package can be easily seen and
Easy to observe, implement, and test. Furthermore, the external terminals act as a buffer against deformation of the motherboard, so that the semiconductor package surface-mounted on the motherboard does not come off.
第１図は本発明の一実施例の斜視図で第２図はそのＸ−
Ｙ断面図を示し、第３図、第４図、第５図はそれぞれ他
の実施例の同様の断面図である。
１・・・絶縁層 ２・・・導電パターン３・・
・プリント配線板 ４・・・マザーボード５・・・外部
端子 ６・・・第１の凹部７・・・半導体チップ
８・・・ワイヤ９・・・枠 １０・・・
熱伝導板１１・・・第２の凹部 １２・・・放熱体１
９・・・スルホール導電路
２０・・・導電端子 ２１・・・導体特許出願人
松下電工株式会社Figure 1 is a perspective view of one embodiment of the present invention, and Figure 2 is its X-
A Y sectional view is shown, and FIGS. 3, 4, and 5 are similar sectional views of other embodiments. 1... Insulating layer 2... Conductive pattern 3...
- Printed wiring board 4... Motherboard 5... External terminal 6... First recess 7... Semiconductor chip 8... Wire 9... Frame 10...
Heat conduction plate 11...Second recess 12...Radiator 1
9... Through-hole conductive path 20... Conductive terminal 21... Conductor patent applicant
Matsushita Electric Works Co., Ltd.
Claims (6)
ンとからなるプリント配線板の外側に突出した金属の薄
板条片から形成された外部端子と前記導電パターンとが
プリント配線板上で電気的に接続固着されたことを特徴
とする表面実装用半導体パッケージ。(1) A printed wiring board consisting of an insulating layer and a conductive pattern disposed on the surface of the insulating layer has an external terminal formed from a thin metal strip protruding outside the printed wiring board, and the conductive pattern formed on the printed wiring board. A surface mount semiconductor package characterized by being electrically connected and fixed.
伝導板の一方の表面が前記絶縁層に形成された第１の凹
部の底面として露出していることを特徴とする請求項１
記載の表面実装用半導体パッケージ。(2) A heat conductive plate is provided which is embedded in the insulating layer, and one surface of the heat conductive plate is exposed as a bottom surface of a first recess formed in the insulating layer. 1
The surface mount semiconductor package described above.
プ搭載面を形成し、熱伝導板の他方の表面は放熱面とし
て前記絶縁層に形成された第２の凹部の底面に露出して
なることを特徴とする請求項２記載の表面実装用半導体
パッケージ。(3) The heat conductive plate exposed in the first recess forms a semiconductor chip mounting surface, and the other surface of the heat conductive plate is exposed as a heat dissipation surface on the bottom surface of the second recess formed in the insulating layer. 3. The surface mounting semiconductor package according to claim 2, characterized in that the semiconductor package comprises:
とを特徴とする請求項３記載の表面実装用半導体パッケ
ージ。(4) The semiconductor package for surface mounting according to claim 3, characterized in that a heat radiator is attached to the heat radiating surface of the heat conductive plate.
半導体封止用樹脂材料の流れ止め用の枠が形成されたこ
とを特徴とする請求項１、２、３又は４のいずれか記載
の表面実装用半導体パッケージ。(5) A frame for preventing the flow of semiconductor encapsulating resin material is formed on the printed wiring board on the semiconductor chip mounting surface side. Semiconductor package for surface mounting.
ール導電路で反対の表面に配設された導電端子に接続さ
れ、導電端子と外部端子とが接続固着されてなることを
特徴とする請求項１、２、３、４又は５のいずれか記載
の表面実装用半導体パッケージ。(6) A claim characterized in that the conductive pattern on one surface of the insulating layer is connected to a conductive terminal provided on the opposite surface by a through-hole conductive path, and the conductive terminal and the external terminal are connected and fixed. The surface mounting semiconductor package according to any one of Items 1, 2, 3, 4, or 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7364989A JPH02251166A (en) | 1989-03-24 | 1989-03-24 | Semiconductor package for surface mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7364989A JPH02251166A (en) | 1989-03-24 | 1989-03-24 | Semiconductor package for surface mounting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02251166A true JPH02251166A (en) | 1990-10-08 |
Family
ID=13524345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7364989A Pending JPH02251166A (en) | 1989-03-24 | 1989-03-24 | Semiconductor package for surface mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02251166A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04164361A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Resin-sealed semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS601847A (en) * | 1983-06-20 | 1985-01-08 | Toshiba Corp | Hybrid integrated circuit |
| JPS61183936A (en) * | 1985-02-08 | 1986-08-16 | Toshiba Corp | Semiconductor device |
| JPS6243155A (en) * | 1985-08-21 | 1987-02-25 | Hitachi Ltd | Integrated circuit package |
| JPS63257255A (en) * | 1987-04-14 | 1988-10-25 | Sumitomo Electric Ind Ltd | Integrated circuit package |
| JPS6447058A (en) * | 1987-08-18 | 1989-02-21 | Shinko Electric Ind Co | Package for semiconductor device |
-
1989
- 1989-03-24 JP JP7364989A patent/JPH02251166A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS601847A (en) * | 1983-06-20 | 1985-01-08 | Toshiba Corp | Hybrid integrated circuit |
| JPS61183936A (en) * | 1985-02-08 | 1986-08-16 | Toshiba Corp | Semiconductor device |
| JPS6243155A (en) * | 1985-08-21 | 1987-02-25 | Hitachi Ltd | Integrated circuit package |
| JPS63257255A (en) * | 1987-04-14 | 1988-10-25 | Sumitomo Electric Ind Ltd | Integrated circuit package |
| JPS6447058A (en) * | 1987-08-18 | 1989-02-21 | Shinko Electric Ind Co | Package for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04164361A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Resin-sealed semiconductor device |
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