JPH0337308B2 - - Google Patents

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Publication number
JPH0337308B2
JPH0337308B2 JP60181692A JP18169285A JPH0337308B2 JP H0337308 B2 JPH0337308 B2 JP H0337308B2 JP 60181692 A JP60181692 A JP 60181692A JP 18169285 A JP18169285 A JP 18169285A JP H0337308 B2 JPH0337308 B2 JP H0337308B2
Authority
JP
Japan
Prior art keywords
thermal expansion
coefficient
glass
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60181692A
Other languages
Japanese (ja)
Other versions
JPS6243155A (en
Inventor
Satoru Ogiwara
Tomoji Ooishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60181692A priority Critical patent/JPS6243155A/en
Priority to US06/890,533 priority patent/US4729010A/en
Priority to EP86305894A priority patent/EP0211618B1/en
Priority to DE8686305894T priority patent/DE3672709D1/en
Publication of JPS6243155A publication Critical patent/JPS6243155A/en
Publication of JPH0337308B2 publication Critical patent/JPH0337308B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は、集積回路パツケージに係わり、特
に、基板に熱伝導性がよく、半導体素子の熱膨張
係数に近似した炭化ケイ素質セラミツクスを用い
た集積回路パツケージに関する。 〔従来の技術〕 セラミツクス質絶縁基板、キヤツプ及び封止ガ
ラスによつて気密に囲われた小室内に、半導体素
子並びに外部から導入されたリード端部と両者を
電気的に接続した接合部とを収容した構造からな
る集積回路パツケージは、今日広く実用に供せら
れている。 そのようなパツケージを用いた際の難点として
半導体素子に生じた熱の放熱特性が極めて悪いと
いうことである。このことは半導体素子の大容量
化、高集積化及び小型化を図るうえで大きな障害
となつている。従つて、集積回路パツケージにお
いて、半導体素子を接着する絶縁基板には、電気
絶縁性とともに優れた熱伝導性を有することが要
求される。また、シリコンを用いた集積回路を接
着するために、基板用材料としては、熱膨張係数
がシリコンに近似することが望まれる。 このような要求を満足する材料として、炭化ケ
イ素質セラミツクスがある。それを絶縁基板とし
て、熱放散性の良好な集積回路パツケージの製作
を可能にした（特開昭59−134852、特開昭60−
66843）。 〔発明が解決しようとする問題点〕 しかし、前記炭化ケイ素質基板の適用に関する
検討の進行に伴い、炭化ケイ素質基板に半導体素
子を搭載し、半導体素子に電気的リード端部を接
続し、これら、半導体素子とリード接続部をキヤ
ツプと封止ガラスによりパツケージをつくり、ガ
ラスを貫通して電気的リードを外部に取り出す集
積回路パツケージを作製したところ、封止ガラス
部、特にリード端子周辺のガラスに亀裂を生ずる
という問題を生じた。そして、この場合、半導体
素子が入つた小室内と外気とがつながるため、外
気中に含まれる水分が小室内に入り、動作不良に
つながる恐れがある。 〔問題点を解決するための手段〕 上記した封止ガラスに生ずる亀裂は、リード材
料の熱膨張率が大きいことに起因する熱応力によ
るものと考えられる。 そして、前記封止ガラス部のクラツク防止手段
として一般的に考えられるのは、封止ガラスと熱
膨張係数が合致したリード材料を用いることであ
るが、本発明者等の研究によれば、炭化ケイ素質
セラミツクスを基板として用いる本発明の対象と
なるパツケージの場合には、リード材料の熱膨張
係数をガラスの熱膨張係数のそれと合致させて
も、前記クラツクの防止には何等有効ではないこ
とが確認された。 そこで、本発明者等はさらに研究を進めた結
果、リード材料の熱膨張係数をガラスの熱膨張係
数を基準にして設定するのではなく、前記基板の
熱膨張係数を基準としてこれとほぼ同等かまたは
それ以下とすることにより、きわめて有効に前記
封止ガラス部のクラツクが防止されることを突き
止め、この新規な知見にもとづいて本発明を完成
するに到つたものである。 本発明は上記知見に基づき、リード材料の熱膨
張係数を限定することにより、一層高い安定性と
信頼性を有する集積回路パツケージを提供するも
のであつて、その特徴は炭化ケイ素質基板、キヤ
ツプ及び封止ガラスによつて気密に囲われた小室
内に、該基板上に載置された半導体素子と該室外
から封止ガラスを貫通して導入されたリードから
なる集積回路パツケージにおいて、リード材料の
熱膨張係数を基板の熱膨張係数とほぼ同等かまた
はそれ以下、さらに具体的には、40×10-7／℃以
下に限定することにある。 ここで、本発明で用いられる基板材料は実質的
に炭化ケイ素からなるセラミツクス基板である。
特に、ベリリウム及びベリリウム化合物のうちか
ら選ばれた少なくとも１種をベリリウム量にして
0.05〜５重量％を含む炭化ケイ素セラミツクスが
適する。その熱膨張係数は35〜40×10-7／℃であ
る。キヤツプに用いる材料はムライト質セラミツ
クス、炭化ケイ素質セラミツクス、ジルコン質セ
ラミツクス、窒化ケイ素質セラミツクスなどが使
われ、その熱膨張係数は35〜50×10-7／℃を有す
る材料に限定される。また、封止ガラスとして
は、熱膨張係数が45〜55×10-7／℃に限定され、
しかも、封止温度が470℃以下に限定された低融
点ガラスである。封止温度が限定される理由は、
基板の上に接合された半導体素子が、封止作業温
度が470℃以上の高温になると、半導体の電極に
用いられているAl等が半導体のPn接合部に拡散
し、劣化をおこすためである。このように低温で
接着作業ができ、熱膨張係数が炭化ケイ素質セラ
ミツクスに近似したガラスはない。このため、低
融点の硼ケイ酸鉛系ガラスに負の熱膨張係数をも
つチタン酸鉛またはβ−ユークリプタイト等のフ
イラーをガラスに混合して、熱膨張係数を小さく
している。しかし、これらフイラを多量に入れる
とガラスの流動性が悪くなるためガラスの熱膨張
係数は45〜55×10-7／℃に限定される。 上記に示すような材料を組み合わせて第１図に
示すような炭化ケイ素質セラミツクスを基板とし
て用い熱処理によりガラスでパツケージを作製す
る際に、上記のようにこの封止ガラス部、特にリ
ード端子周辺のガラスにクラツクが入りやすいも
のであるが、前述のように本発明においては、リ
ード材料の熱膨張係数を基板の熱膨張係数とほぼ
同等またはそれ以下の40×10-7／℃以下にするこ
とにより、封止ガラスに貫通したクラツクを生じ
ない信頼性の優れたパツケージを作製することが
可能となるものである。そして、このようなクラ
ツク防止の効果は、リード材料の熱膨張係数を前
記のように限定することにより、封止ガラス中に
封入されたリード材料が、本来基板より大きい熱
膨張係数を有する封止ガラスのそれを基板の熱膨
張係数に近づける作用をするからであると考えら
れる。 このようなリード材料としてはコバール（Ni
−Co−Fe合金）がある。特にNi28.5〜30.0、
Co12.5〜14、C0.02以下、Si0.2以下、Mn0.8以下、
残りFe（wt％）の組成のコバールが適する。 〔実施例〕 第１図に本発明の集積回路パツケージの断面を
例示する。同図において炭化ケイ素質セラミツク
スからなる基板４の一方の面４ａ上の中央部に半
導体素子１が金属ソルダ層７によつて接着され、
同面上に封止ガラス層６によつて接着された複数
個のリード片３の一端３ａと該素子１との間はボ
ンデイングワイヤ２によつて電気的に接続されて
いる。リード片３の他端３ｂは、基板４の周縁か
ら外方に延びている。素子１、ボンデイングワイ
ヤ２及びリード片３の端部３ａは絶縁基板４とキ
ヤツプ５とによつて囲われ、該キヤツプ５と基板
４及びリード片３との間隙は封止ガラス層６を介
して気密に封着されている。 上記パツケージの構造において、キヤツプ材
料、ガラス材料及びリード材料をかえて、パツケ
ージを作製した。基板材料は熱膨張係数が35〜40
×10-7／℃をもつ炭化ケイ素質セラミツクスであ
る。特に、ベリリウムを0.05〜５重量％を含む、
抵抗率108Ω・cm以上の電気絶縁性と、熱伝導率
0.2〜0.7cal／cm・ｓ・℃の特性を持つ、炭化ケイ
素質セラミツクスが有効である。 このパツケージは以下の方法で作製される。ま
ず、炭化ケイ素基板の上に、半導体素子を接合す
るためのAuペーストを印刷、焼成して、基板上
に金属ソルダ層７を形成する。次に、炭化ケイ素
基板上に封止ガラス６を印刷し、焼成して、ガラ
スを基板につける。リード片３を封止ガラス層６
の上面に設置し、ガラスの軟化温度以上、例えば
450〜480℃に加熱して、リード片を接着する。半
導体素子１を基板上の金属ソルダ層７に設置し、
350〜450℃に加熱することにより金属ソルダ層７
を形成して、半導体素子を接着する。半導体素子
とリード片端子とをワイヤ２により電気的に接続
する。次に、封止ガラス６が付いたキヤツプ材５
を載せ、445〜460℃で加熱して、封止ガラスで封
着する。これにより集積回路パツケージが作製さ
れる。封止後及び−55〜150℃の冷熱サイクル20
回を試験後、ヘリウムリークテストにより、リー
ク量を測定し、パツケージの良品、不良品を判定
した。 第１表に、各種材料の組み合わせとパツケージ
の良品、不良品との判定結果を示す。 [Industrial Field of Application] The present invention relates to an integrated circuit package, and particularly to an integrated circuit package using silicon carbide ceramics as a substrate, which has good thermal conductivity and has a coefficient of thermal expansion close to that of a semiconductor element. [Prior art] A semiconductor element, a lead end introduced from the outside, and a joint electrically connecting the two are placed in a small chamber hermetically enclosed by a ceramic insulating substrate, a cap, and a sealing glass. Integrated circuit packages consisting of enclosed structures are in widespread use today. A drawback of using such a package is that the heat dissipation characteristics of the heat generated in the semiconductor element are extremely poor. This is a major hindrance in achieving larger capacity, higher integration, and smaller size of semiconductor devices. Therefore, in an integrated circuit package, an insulating substrate to which a semiconductor element is bonded is required to have not only electrical insulation properties but also excellent thermal conductivity. Further, in order to bond an integrated circuit using silicon, it is desirable that the substrate material have a thermal expansion coefficient similar to that of silicon. Silicon carbide ceramics are a material that satisfies these requirements. By using it as an insulating substrate, it became possible to manufacture integrated circuit packages with good heat dissipation (Japanese Patent Application Laid-Open No. 59-134852,
66843). [Problems to be Solved by the Invention] However, with the progress of studies regarding the application of the silicon carbide substrate, semiconductor elements are mounted on the silicon carbide substrate, and electrical lead ends are connected to the semiconductor elements. When we fabricated an integrated circuit package in which the semiconductor element and the lead connection part were made of a cap and sealing glass, and the electrical leads were taken out to the outside by penetrating the glass, we found that the sealing glass part, especially the glass around the lead terminals, This caused the problem of cracking. In this case, since the small chamber containing the semiconductor element is connected to the outside air, moisture contained in the outside air may enter the small chamber, leading to malfunction. [Means for Solving the Problems] The cracks that occur in the above-mentioned sealing glass are considered to be caused by thermal stress caused by the large coefficient of thermal expansion of the lead material. A commonly thought method for preventing cracks in the sealing glass section is to use a lead material whose coefficient of thermal expansion matches that of the sealing glass, but according to research by the present inventors, carbonization In the case of a package subject to the present invention that uses silicone ceramics as a substrate, even if the coefficient of thermal expansion of the lead material matches that of glass, it is not effective in preventing the above-mentioned cracks. confirmed. Therefore, as a result of further research, the present inventors decided to set the thermal expansion coefficient of the lead material not based on the thermal expansion coefficient of glass, but to set it almost equal to the thermal expansion coefficient of the substrate. It has been found that the cracking of the sealing glass portion can be extremely effectively prevented by setting the thickness of the sealing glass portion to 50% or less, and based on this new knowledge, the present invention has been completed. Based on the above findings, the present invention provides an integrated circuit package with even higher stability and reliability by limiting the thermal expansion coefficient of the lead material, and its features include a silicon carbide substrate, a cap, and In an integrated circuit package consisting of a semiconductor element mounted on a substrate and a lead introduced from outside the room through the sealing glass, the lead material is placed in a small chamber hermetically enclosed by sealing glass. The objective is to limit the thermal expansion coefficient to approximately the same as or less than the thermal expansion coefficient of the substrate, more specifically to 40×10 −7 /° C. or less. Here, the substrate material used in the present invention is a ceramic substrate consisting essentially of silicon carbide.
In particular, at least one selected from beryllium and beryllium compounds is added in an amount of beryllium.
Silicon carbide ceramics containing from 0.05 to 5% by weight are suitable. Its coefficient of thermal expansion is 35-40×10 −7 /°C. The materials used for the cap include mullite ceramics, silicon carbide ceramics, zircon ceramics, and silicon nitride ceramics, and are limited to materials having a coefficient of thermal expansion of 35 to 50 x 10 -7 /°C. In addition, as a sealing glass, the coefficient of thermal expansion is limited to 45 to 55 × 10 -7 /℃,
Moreover, it is a low melting point glass whose sealing temperature is limited to 470°C or less. The reason why the sealing temperature is limited is
This is because when a semiconductor element bonded on a substrate is sealed at a high temperature of 470°C or higher, Al, etc. used in the semiconductor's electrodes diffuse into the Pn junction of the semiconductor, causing deterioration. . There is no glass that can be bonded at such low temperatures and has a thermal expansion coefficient similar to that of silicon carbide ceramics. For this reason, a filler such as lead titanate or β-eucryptite, which has a negative coefficient of thermal expansion, is mixed with lead borosilicate glass having a low melting point to reduce the coefficient of thermal expansion. However, if a large amount of these fillers are added, the fluidity of the glass deteriorates, so the coefficient of thermal expansion of the glass is limited to 45 to 55 x 10 -7 /°C. When a package is made of glass by heat treatment using silicon carbide ceramics as a substrate as shown in Figure 1 by combining the materials shown above, the sealing glass part, especially around the lead terminals, is Glass tends to crack, but as mentioned above, in the present invention, the coefficient of thermal expansion of the lead material should be 40×10 -7 /°C or less, which is approximately equal to or lower than the coefficient of thermal expansion of the substrate. This makes it possible to produce a highly reliable package that does not cause cracks that penetrate the sealing glass. This crack prevention effect is achieved by limiting the coefficient of thermal expansion of the lead material as described above. This is thought to be due to the effect of bringing the coefficient of thermal expansion of glass closer to that of the substrate. Kovar (Ni) is an example of such a lead material.
-Co-Fe alloy). Especially Ni28.5~30.0,
Co12.5~14, C0.02 or less, Si0.2 or less, Mn0.8 or less,
Kovar with a composition of remaining Fe (wt%) is suitable. [Embodiment] FIG. 1 illustrates a cross section of an integrated circuit package of the present invention. In the figure, a semiconductor element 1 is bonded to the center of one surface 4a of a substrate 4 made of silicon carbide ceramics with a metal solder layer 7.
One end 3a of a plurality of lead pieces 3 bonded on the same surface by a sealing glass layer 6 and the element 1 are electrically connected by a bonding wire 2. The other end 3b of the lead piece 3 extends outward from the periphery of the substrate 4. The end portions 3a of the element 1, bonding wire 2, and lead piece 3 are surrounded by an insulating substrate 4 and a cap 5, and the gaps between the cap 5, the substrate 4, and the lead piece 3 are separated by a sealing glass layer 6. Hermetically sealed. Packages were manufactured by changing the cap material, glass material, and lead material in the above package structure. The substrate material has a thermal expansion coefficient of 35-40
It is a silicon carbide ceramic with a temperature of ×10 -7 /℃. In particular, it contains 0.05 to 5% by weight of beryllium.
Electrical insulation with resistivity of 108 Ω・cm or more and thermal conductivity
Silicon carbide ceramics with properties of 0.2 to 0.7 cal/cm・s・℃ are effective. This package is produced by the following method. First, an Au paste for bonding a semiconductor element is printed and fired on a silicon carbide substrate to form a metal solder layer 7 on the substrate. Next, sealing glass 6 is printed on the silicon carbide substrate and fired to attach the glass to the substrate. Glass layer 6 sealing lead piece 3
above the softening temperature of the glass, e.g.
Heat to 450-480℃ to glue the lead pieces. A semiconductor element 1 is placed on a metal solder layer 7 on a substrate,
Metal solder layer 7 is formed by heating to 350~450℃
is formed to bond the semiconductor element. The semiconductor element and the lead piece terminals are electrically connected by wires 2. Next, the cap material 5 with the sealing glass 6 is attached.
is placed, heated at 445-460°C, and sealed with sealing glass. This produces an integrated circuit package. After sealing and -55 to 150℃ cooling cycle 20
After testing twice, the amount of leakage was measured using a helium leak test to determine whether the package was good or defective. Table 1 shows the combinations of various materials and the results of determining whether the package is good or defective.

【表】【table】

【表】 熱膨張係数が41×10-7／℃、43×10-7／℃のリ
ード材料を用いたNo.１、２、６、11及び12のパツ
ケージはいずれもヘリウムリーク不良をおこして
いる。本発明の熱膨張係数が39×10-7／℃以下の
リード材料を用いたパツケージはいずれもヘリウ
ムリーク不良がなく、良好である。尚、キヤツプ
材にアルミナ材料を用いたパツケージは、リード
材料が低熱膨張係数であつてもガラスにクラツク
を生ずる。 第２表も第１表と同様に構成材料をかえて作製
したパツケージのヘリウムリークテストによる良
品、不良品をみたものである。[Table] Packages No. 1, 2, 6, 11, and 12 using lead materials with thermal expansion coefficients of 41×10 -7 /℃ and 43×10 -7 /℃ all caused helium leak defects. There is. All packages using the lead material of the present invention having a coefficient of thermal expansion of 39×10 -7 /°C or less have no helium leakage defects and are in good condition. Incidentally, in a package using an alumina material for the cap material, cracks occur in the glass even if the lead material has a low coefficient of thermal expansion. Similar to Table 1, Table 2 also shows the results of the helium leak test of packages manufactured using different constituent materials, and shows the good and defective products.

【表】【table】

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、炭化ケ
イ素質セラミツクスを基板に用いた集積回路パツ
ケージにおいて、所定の冷熱サイクルテストにさ
らしても封止ガラスに亀裂が生じないものが得ら
れるという顕著な効果を奏するものである。 As explained above, according to the present invention, it is possible to obtain an integrated circuit package using silicon carbide ceramics as a substrate, in which the sealing glass does not crack even when subjected to a prescribed thermal cycle test. It is effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第４図は、それぞれ本発明の集積回路
パツケージの異なる実施例の断面図である。 １……半導体素子、２……ボンデイングワイ
ヤ、３……リード片、４……基板（Sic）、５……
キヤツプ、６……封止ガラス層、７……金属ソル
ダ層、シリコン配線基板、９……冷却フイン、１
０……接着剤、１１……フランジ、１２……はん
だ、１３……配線。 1-4 are cross-sectional views of different embodiments of integrated circuit packages of the present invention. 1... Semiconductor element, 2... Bonding wire, 3... Lead piece, 4... Substrate (SIC), 5...
Cap, 6... Sealing glass layer, 7... Metal solder layer, silicon wiring board, 9... Cooling fin, 1
0...adhesive, 11...flange, 12...solder, 13...wiring.

Claims (1)

【特許請求の範囲】 １ 絶縁基板、キヤツプ及び封止ガラスによつて
気密に囲まれたケース内に、該絶縁基板に搭載さ
れた半導体素子と、該ケース内部に導入された電
気的リードの端部と、該半導体素子及び該電気的
リードの端部を接続する接続部とが収納されてい
る集積回路パツケージにおいて、該絶縁基板は熱
膨張係数が35〜40×10-7／℃である炭化ケイ素質
セラミツクスから成り、該キヤツプは熱膨張係数
が35〜50×10-7／℃であるセラミツクスから成
り、該封止ガラスは熱膨張係数45〜55×10-7／℃
のガラスから成り、該電気的リードは熱膨張係数
が40×10-7／℃以下である合金からなることを特
徴とする集積回路パツケージ。 ２ 封止ガラスは、封止作業温度が470℃以下で
ある低融点ガラスであることを特徴とする特許請
求の範囲第１項記載の集積回路パツケージ。 ３ 電気的リードは、Ni−Co−Fe合金であるこ
とを特徴とする特許請求の範囲第１項記載の集積
回路パツケージ。[Claims] 1. A semiconductor element mounted on the insulating substrate and the ends of electrical leads introduced into the case in a case hermetically surrounded by an insulating substrate, a cap, and a sealing glass. In the integrated circuit package, the insulating substrate is made of a carbonized material having a coefficient of thermal expansion of 35 to 40×10 -7 /°C. The cap is made of silicon ceramics, the cap is made of ceramics with a thermal expansion coefficient of 35 to 50 x 10 -7 /°C, and the sealing glass has a thermal expansion coefficient of 45 to 55 x 10 -7 /°C.
An integrated circuit package, characterized in that the electrical leads are made of an alloy having a coefficient of thermal expansion of 40×10 −7 /° C. or less. 2. The integrated circuit package according to claim 1, wherein the sealing glass is a low melting point glass whose sealing operation temperature is 470° C. or lower. 3. The integrated circuit package according to claim 1, wherein the electrical leads are made of a Ni-Co-Fe alloy.
JP60181692A 1985-08-05 1985-08-21 Integrated circuit package Granted JPS6243155A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60181692A JPS6243155A (en) 1985-08-21 1985-08-21 Integrated circuit package
US06/890,533 US4729010A (en) 1985-08-05 1986-07-30 Integrated circuit package with low-thermal expansion lead pieces
EP86305894A EP0211618B1 (en) 1985-08-05 1986-07-31 Integrated circuit package
DE8686305894T DE3672709D1 (en) 1985-08-05 1986-07-31 INTEGRATED CIRCUIT PACK.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60181692A JPS6243155A (en) 1985-08-21 1985-08-21 Integrated circuit package

Publications (2)

Publication Number Publication Date
JPS6243155A JPS6243155A (en) 1987-02-25
JPH0337308B2 true JPH0337308B2 (en) 1991-06-05

Family

ID=16105199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60181692A Granted JPS6243155A (en) 1985-08-05 1985-08-21 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS6243155A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02251166A (en) * 1989-03-24 1990-10-08 Matsushita Electric Works Ltd Semiconductor package for surface mounting
JP2736455B2 (en) * 1989-11-27 1998-04-02 京セラ株式会社 Package for storing semiconductor elements
JP2736456B2 (en) * 1989-11-27 1998-04-02 京セラ株式会社 Package for storing semiconductor elements
JP2736459B2 (en) * 1989-11-30 1998-04-02 京セラ株式会社 Package for storing semiconductor elements
JP2736464B2 (en) * 1989-11-30 1998-04-02 京セラ株式会社 Package for storing semiconductor elements
JP2736451B2 (en) * 1989-11-27 1998-04-02 京セラ株式会社 Package for storing semiconductor elements
JP2736452B2 (en) * 1989-11-27 1998-04-02 京セラ株式会社 Package for storing semiconductor elements

Also Published As

Publication number Publication date
JPS6243155A (en) 1987-02-25

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