JP2001338999A - Semiconductor element storing package - Google Patents

Semiconductor element storing package

Info

Publication number
JP2001338999A
JP2001338999A JP2000160751A JP2000160751A JP2001338999A JP 2001338999 A JP2001338999 A JP 2001338999A JP 2000160751 A JP2000160751 A JP 2000160751A JP 2000160751 A JP2000160751 A JP 2000160751A JP 2001338999 A JP2001338999 A JP 2001338999A
Authority
JP
Japan
Prior art keywords
semiconductor element
package
insulating substrate
high thermal
thermal conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000160751A
Other languages
Japanese (ja)
Inventor
Shoichi Nakagawa
彰一 仲川
Kazutaka Maeda
和孝 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000160751A priority Critical patent/JP2001338999A/en
Publication of JP2001338999A publication Critical patent/JP2001338999A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance connection reliability with an outside circuit board by suppressing the occurrence of shearing stress for a connection terminal without losing heat radiation from a high heat conduction cover body even when a heat cycle is repeatedly applied in a semiconductor element storing package mounting a semiconductor element by a flip chip and attaching the high heat conduction cover body on the upper face of the semiconductor element. SOLUTION: The semiconductor element storing package is provided with the high heat conduction cover body 9 mounting the semiconductor element 2 provided with a connection electrode by the flip chip on a metalized wiring layer 3 on the surface of a substantially rectangular insulation board 1, adhering and forming the metalized wiring layer 3 so as to cover the semiconductor element 2, and adhering a part thereof to the upper face of the semiconductor element 2, and a plurality of the connection terminals 5 comprising solder connected electrically to the semiconductor element 2 provided on the rear face of an insulation board 1. The high heat conduction cover body 9 has a substantially rectangular shape, a leg part 11 is provided inward from the outermost edge part of the substantially rectangular shape, and the leg part 11 and the insulation board 1 are fixed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高熱伝導性蓋体を
有する半導体素子収納用パッケージの構造に関するもの
であり、特にパッケージの絶縁基板と外部回路基板との
接続信頼性を向上させるための改善に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a package for housing a semiconductor element having a high thermal conductive lid, and more particularly to an improvement for improving the reliability of connection between an insulating substrate of a package and an external circuit board. It is about.

【0002】[0002]

【従来技術】最近のLSI等の半導体集積回路素子(以
下、半導体素子という。)を収納する半導体素子収納用
パッケージにおいて、ワークステーションやパソコンな
どに使用される場合、性能の向上と共に多ピン化が必要
となっており、BGA(Ball Grid Arra
y)やCSP(Chip Size Package)
等のパッケージが使用されている。
2. Description of the Related Art In semiconductor device housing packages for housing recent semiconductor integrated circuit devices (hereinafter, referred to as semiconductor devices) such as LSIs, when used in workstations, personal computers, and the like, the number of pins is increased along with the improvement in performance. Is required, and BGA (Ball Grid Arra)
y) or CSP (Chip Size Package)
Etc. are used.

【0003】一般に、半導体素子とパッケージとの接続
は、半導体素子をパッケージの表面に接着し、半導体素
子上面の電極とパッケージの配線層とをワイヤによって
接続する方法が用いられているが、半導体素子の高集積
化に伴い、最近では半導体素子下面に接続用電極を形成
しパッケージの接続端子とを直接ロウ付けするフリップ
チップ実装する方式が採用されつつある。
In general, a method of connecting a semiconductor element to a package is such that a semiconductor element is adhered to a surface of a package and an electrode on an upper surface of the semiconductor element is connected to a wiring layer of the package by a wire. Recently, a method of flip-chip mounting in which a connection electrode is formed on the lower surface of a semiconductor element and a connection terminal of a package is directly brazed has been adopted with the high integration of the semiconductor device.

【0004】また、このようなフリップチップ実装した
半導体素子から発生した熱を放熱するための構造とし
て、半導体素子の上面に高熱伝導性蓋体を取りつけるこ
とが行われており、この高熱伝導性蓋体の形状や厚みを
変えることによって、種々の発熱量を有する半導体素子
の冷却に適用することができる。このような高熱伝導性
蓋体を備えた半導体素子収納用パッケージとしては、例
えば「日経エレクトロニクス1993年8月2日号」P
104に記載されているものがある。
As a structure for dissipating heat generated from such a flip-chip mounted semiconductor element, a high heat conductive lid is mounted on the upper surface of the semiconductor element. By changing the shape and thickness of the body, the present invention can be applied to cooling of a semiconductor element having various heat values. As a package for accommodating a semiconductor element having such a high heat conductive lid, for example, “Nikkei Electronics, August 2, 1993,”
104.

【0005】この半導体素子収納用パッケージは、図3
の外部回路基板に実装時の概略断面図に示すように、一
般にアルミナセラミックス等からなる絶縁基板21の表
面に、半導体素子22周辺から絶縁基板21下面にかけ
てタングステン、モリブデン等の高融点金属から成る複
数個のメタライズ配線層23が形成され、前記絶縁基板
21の下面の接続パッド24には、接続端子25が取着
形成されている。また、接続パッド24には接続端子2
5として、球状の半田がロウ付け取着されている。
The package for housing a semiconductor element is shown in FIG.
As shown in a schematic cross-sectional view when mounted on an external circuit board, a plurality of layers made of a high melting point metal such as tungsten, molybdenum, etc. are formed on the surface of an insulating substrate 21 generally made of alumina ceramic or the like from the periphery of the semiconductor element 22 to the lower surface of the insulating substrate 21. A plurality of metallized wiring layers 23 are formed, and connection terminals 25 are attached to connection pads 24 on the lower surface of the insulating substrate 21. The connection pad 24 has a connection terminal 2
5, a solder ball is attached by brazing.

【0006】また、半導体素子22は、セラミック絶縁
基板21に配設されたメタライズ配線層23と、半田や
金などの金属または導電性樹脂からなる微小な電極26
を介してフリップチップ実装接続され、その接続部は熱
硬化性樹脂27によって封止されている。
The semiconductor element 22 includes a metallized wiring layer 23 provided on a ceramic insulating substrate 21 and minute electrodes 26 made of a metal such as solder or gold or a conductive resin.
And the connection portion is sealed by a thermosetting resin 27.

【0007】半導体素子収納用パッケージaは、前記半
田からなる接続端子25を外部回路基板bの配線導体2
8上に載置当接させ、しかる後、前記球状の接続端子2
5を約150〜250℃の温度で加熱溶融し、球状半田
を配線導体28に接合させることによって外部回路基板
b上に実装される。
[0007] The semiconductor device accommodating package a is formed by connecting the connection terminal 25 made of the solder to the wiring conductor 2 of the external circuit board b.
8 and then put on the spherical connection terminal 2.
5 is heated and melted at a temperature of about 150 to 250 ° C., and is mounted on the external circuit board b by joining the spherical solder to the wiring conductor 28.

【0008】また、パッケージaにおける半導体素子2
2の上部には、熱伝導性接着材30を介して高熱伝導性
蓋体29が固着されており、半導体素子22の作動時に
発する熱を熱伝導性接着材30を介して高熱伝導性蓋体
29から外表面へと放熱される構造からなる。高熱伝導
性蓋体29は通常、四角形状であり、角部にはR部が設
けられているものもある。
The semiconductor element 2 in the package a
A high thermal conductive lid 29 is fixed to the upper part of the second semiconductor device via a thermal conductive adhesive 30, and heat generated when the semiconductor element 22 is operated is transmitted through the high thermal conductive adhesive 30. It has a structure in which heat is radiated from 29 to the outer surface. The high thermal conductive lid 29 is usually in the shape of a square, and some of the corners are provided with an R portion.

【0009】この高熱伝導性蓋体29の表面積が大きい
ほど放熱効果は高くなるが、そのため、通常、高熱伝導
性蓋体29の外形寸法は半導体素子22よりも大きく、
パッケージの絶縁基板21と同程度の大きさからなる
が、熱伝導性接着材30との接着だけでは接着面積が小
さく、不安定である。そのため、高熱伝導性蓋体29と
半導体素子22との接続を保つために、高熱伝導性蓋体
29の周縁部には絶縁基板21との取付け部31が形成
されており、半田や銀ペースト等のロウ材32を用いて
絶縁基板21表面に接着されている。この高熱伝導性蓋
体29の具体的な形状としては、取付け部31が絶縁基
板21の周縁部に枠体として形成された、いわゆるキャ
ップ形状のもの(図5(a))や、高熱伝導性蓋体の対
角角部の4隅に取付け用の脚部31が設けられたもの
(図5(b))等が使用されている。
The heat dissipation effect increases as the surface area of the high thermal conductive lid 29 increases, and therefore, the outer dimensions of the high thermal conductive lid 29 are usually larger than the semiconductor element 22.
Although it has the same size as the insulating substrate 21 of the package, the bonding area is small and unstable only by bonding to the heat conductive adhesive 30. Therefore, in order to keep the connection between the high thermal conductive lid 29 and the semiconductor element 22, a mounting portion 31 for attaching to the insulating substrate 21 is formed on the periphery of the high thermal conductive lid 29, and the solder or the silver paste is used. Is adhered to the surface of the insulating substrate 21 using the brazing material 32. As a specific shape of the high thermal conductive lid 29, a so-called cap-shaped one in which the mounting portion 31 is formed as a frame on the periphery of the insulating substrate 21 (FIG. 5A), a high thermal conductive For example, one in which mounting legs 31 are provided at four diagonal corners of the lid (FIG. 5B) is used.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、かかる
BGAパッケージにおいて、使用環境の温度変化や稼働
中の自己発熱によって温度変化が生じると、パッケージ
の絶縁基板21と外部回路基板bの熱膨張係数差に起因
した熱膨張差によって、半田からなる接続端子25には
せん断歪みが負荷される。特にパッケージ中心からの距
離の長い、対角角部に位置する接続端子において熱膨張
差が大きく、大きなせん断ひずみが発生する。
However, in such a BGA package, if a temperature change occurs due to a temperature change in the use environment or self-heating during operation, a difference in thermal expansion coefficient between the insulating substrate 21 of the package and the external circuit board b occurs. Due to the resulting difference in thermal expansion, a shear strain is applied to the connection terminal 25 made of solder. In particular, the thermal expansion difference is large at connection terminals located at diagonal corners where the distance from the package center is long, and large shear strain is generated.

【0011】パッケージの絶縁基板21はこの熱膨張差
を緩和するために半導体素子搭載側が凹となるように反
ろうと(歪もうと)する。しかし、最も反りが大きい絶
縁基板21の対角角部が、絶縁基板21表面に固着され
ている高熱伝導性蓋体29によって変形を抑制されるた
め、熱膨張差を緩和することができない。特に高熱伝導
性蓋体29の熱膨張係数が絶縁基板21の熱膨張係数よ
りも大きい場合には、絶縁基板21は外部回路基板b側
へと反るため、接続端子25に生じるせん断ひずみは極
端に大きくなる。こうしたせん断ひずみが繰り返し負荷
されると、半田からなる接続端子25は疲労し、熱疲労
破壊を引き起こしてしまうという問題があった。このよ
うな課題を解決するために、図4の概略断面図に示すよ
うに、該高熱伝導性蓋体29を小型とすることにより、
絶縁基板21の対角角部の変形抑制を緩和する方法が考
えられるが、該高熱伝導性蓋体29を小型化すると放熱
性が低下してしまうという問題があった。
In order to reduce the difference in thermal expansion, the insulating substrate 21 of the package tends to warp (strain) so that the semiconductor element mounting side is concave. However, since the diagonal corners of the insulating substrate 21 having the largest warp are suppressed from being deformed by the high thermal conductive lid 29 fixed to the surface of the insulating substrate 21, the difference in thermal expansion cannot be reduced. In particular, when the thermal expansion coefficient of the high thermal conductive lid 29 is larger than the thermal expansion coefficient of the insulating substrate 21, the insulating substrate 21 warps toward the external circuit board b, and the shear strain generated at the connection terminal 25 is extremely high. Become larger. When such shear strain is repeatedly applied, there is a problem that the connection terminal 25 made of solder becomes fatigued and causes thermal fatigue failure. In order to solve such a problem, as shown in a schematic sectional view of FIG. 4, by reducing the size of the high thermal conductive lid 29,
A method of alleviating the suppression of the deformation at the diagonal corners of the insulating substrate 21 can be considered, but there is a problem that when the high heat conductive lid 29 is miniaturized, the heat radiation property is reduced.

【0012】従って、本発明は、半導体素子をフリップ
チップ実装し半導体素子の上面に高熱伝導性蓋体が取り
付けられ、半田からなる接続端子を具備する半導体素子
収納用パッケージにおいて、半導体素子の作動/停止に
伴う熱サイクルが繰り返し印加された場合においても、
高熱伝導性蓋体からの放熱性を損なうことなく、接続端
子へのせん断応力の発生を抑制し、外部回路基板との接
続性に優れた半導体素子収納用パッケージを提供するこ
とを目的とするものである。
Accordingly, the present invention provides a semiconductor device storage package having a semiconductor device mounted flip-chip, a high thermal conductivity lid attached to an upper surface of the semiconductor device, and a connection terminal made of solder. Even if the thermal cycle accompanying the stop is repeatedly applied,
An object of the present invention is to provide a semiconductor device housing package that suppresses the occurrence of shear stress on a connection terminal without impairing heat radiation from a high thermal conductive lid and has excellent connectivity with an external circuit board. It is.

【0013】[0013]

【課題を解決するための手段】本発明によれば、メタラ
イズ配線層が被着形成された略四角形状の絶縁基板の表
面に、接続用電極を備えた半導体素子を載置し、前記メ
タライズ配線層と前記半導体素子の接続用電極とをロウ
付けしてなるとともに、前記半導体素子を覆うようにし
て前記絶縁基板表面に取着され且つその一部を前記半導
体素子の上面と接着してなる高熱伝導性蓋体と、前記絶
縁基板裏面に設けられ前記半導体素子と電気的に接続さ
れた半田からなる複数の接続端子とを具備する半導体素
子収納用パッケージであって、前記高熱伝導性蓋体が、
略四角形状からなり、前記脚部が且つ該略四角形状の最
外縁部より内側に脚部を設け、該脚部と前記絶縁基板と
を取着してなることを特徴とするものである。
According to the present invention, a semiconductor device having connection electrodes is mounted on a surface of a substantially rectangular insulating substrate on which a metallized wiring layer is formed, and the metallized wiring is formed. A layer and a connection electrode of the semiconductor element are soldered, and high heat is attached to the surface of the insulating substrate so as to cover the semiconductor element and a part of the layer is adhered to the upper surface of the semiconductor element. A conductive lid, and a semiconductor element housing package including a plurality of connection terminals made of solder provided on the back surface of the insulating substrate and electrically connected to the semiconductor element, wherein the high thermal conductive lid is ,
It has a substantially square shape, and the leg portion is provided with a leg portion inside the outermost edge portion of the substantially square shape, and the leg portion is attached to the insulating substrate.

【0014】特に前記高熱伝導性蓋体の熱膨張係数を前
記絶縁基板の熱膨張係数よりも小さくすることによって
発生する熱応力を緩和することができる。
In particular, the thermal stress generated by making the thermal expansion coefficient of the high thermal conductive lid smaller than the thermal expansion coefficient of the insulating substrate can be reduced.

【0015】また、前記半導体素子の上面を高熱伝導性
接着材によって前記高熱伝導性蓋体に接着してなること
によって半導体素子からの熱を蓋体側に効率的に伝熱す
ることができ、さらには前記高熱伝導性蓋体の上面に、
放熱フィンを接合することによってさらに放熱性を高め
ることができ、特に前記高熱伝導性蓋体は、アルミニウ
ムとSiCとの複合材料からなることが望ましい。
Further, by bonding the upper surface of the semiconductor element to the high thermal conductive lid with a high thermal conductive adhesive, heat from the semiconductor element can be efficiently transferred to the lid. Is on the upper surface of the high thermal conductive lid,
The heat dissipation can be further enhanced by joining the heat dissipation fins. In particular, it is desirable that the high thermal conductive lid is made of a composite material of aluminum and SiC.

【0016】また、前記絶縁基板は、ガラスセラミック
スからなり、前記メタライズ配線層が銅を主成分とする
導体からなることが望ましい。
It is preferable that the insulating substrate is made of glass ceramic, and the metallized wiring layer is made of a conductor containing copper as a main component.

【0017】また、半導体素子は、絶縁基板表面のメタ
ライズ配線層にフリップチップ実装してなり、半導体素
子の上面を前記蓋体と接着剤によって接着していること
が放熱性を高める上で望ましい。
It is desirable that the semiconductor element be flip-chip mounted on the metallized wiring layer on the surface of the insulating substrate, and that the upper surface of the semiconductor element be adhered to the lid with an adhesive in order to enhance heat dissipation.

【0018】本発明の半導体素子収納用パッケージによ
れば、高熱伝導性蓋体の脚部を蓋体の最外縁部よりも内
側に設けることによって、高熱伝導性蓋体による放熱性
を損なうことなく、パッケージの絶縁基板と高熱伝導性
蓋体との取り付け部を、絶縁基板の周縁よりも内側の領
域で取り付けることができるために、半導体素子の作動
/停止に伴う熱サイクルが繰り返し印加され、絶縁基板
と外部回路基板との熱膨張係数の相違に起因して絶縁基
板に半導体素子搭載側が凹となるような反り変形が生じ
た場合でも、絶縁基板の角部は拘束されていないため反
ることができ、その結果、対角角部の接続端子のせん断
ひずみを大きく低減することができ、パッケージの外部
回路基板への実装信頼性を高めることができる。
According to the semiconductor device housing package of the present invention, by providing the legs of the high thermal conductive lid inside the outermost edge of the lid, the heat radiation by the high thermal conductive lid is not impaired. Since the mounting portion between the insulating substrate of the package and the high thermal conductive lid can be mounted in a region inside the peripheral edge of the insulating substrate, the thermal cycle accompanying the operation / stop of the semiconductor element is repeatedly applied, Even if the insulating substrate undergoes warpage deformation such that the side on which the semiconductor element is mounted becomes concave due to the difference in the coefficient of thermal expansion between the substrate and the external circuit board, the corners of the insulating substrate are warped because they are not restrained. As a result, the shear strain of the connection terminals at the diagonal corners can be greatly reduced, and the mounting reliability of the package on the external circuit board can be improved.

【0019】[0019]

【発明の実施の形態】図1は、本発明にかかる半導体素
子収納用パッケージの実装構造の一実施例を示す概略図
である。図1によれば、本発明の半導体素子収納用パッ
ケージAにおいては、絶縁基板1の表面に、半導体素子
2周辺から基板1下面にかけてメタライズ配線層3が形
成され、また前記絶縁基板1の下面には接続パッド4が
形成されており、この接続パッド4には、Sn−Pb、
Sn−Pb−Bi、Sn−Ag等の半田からなる球状の
接続端子5がロウ付け取着されている。
FIG. 1 is a schematic view showing an embodiment of a mounting structure of a package for housing a semiconductor element according to the present invention. According to FIG. 1, in the package A for accommodating a semiconductor element of the present invention, a metallized wiring layer 3 is formed on the surface of the insulating substrate 1 from the periphery of the semiconductor element 2 to the lower surface of the substrate 1. Is formed with a connection pad 4, and the connection pad 4 has Sn-Pb,
A spherical connection terminal 5 made of solder such as Sn-Pb-Bi or Sn-Ag is soldered and attached.

【0020】また、半導体素子2は、フリップチップ実
装されており、具体的には絶縁基板1の上面に形成され
たパッドに対して半田等の微小な接続端子6により電気
的に接続されており、その接続部はいわゆるアンダーフ
ィル材と呼ばれる熱硬化性樹脂7によって封止されてい
る。さらに、半導体素子2の他面には、半導体素子2の
発する熱を放熱するための高熱伝導性蓋体9が熱伝導性
接着材10を介して接着されている。フリップチップ実
装することによって半導体素子2の上面を熱伝導性接着
剤10によって高熱伝導性蓋体9と熱的に接続すること
ができるために放熱性を高めることができる。
The semiconductor element 2 is flip-chip mounted. Specifically, the semiconductor element 2 is electrically connected to pads formed on the upper surface of the insulating substrate 1 by minute connection terminals 6 such as solder. The connection portion is sealed by a thermosetting resin 7 called a so-called underfill material. Further, a high heat conductive lid 9 for dissipating heat generated by the semiconductor element 2 is bonded to the other surface of the semiconductor element 2 via a heat conductive adhesive 10. By flip-chip mounting, the upper surface of the semiconductor element 2 can be thermally connected to the high heat conductive lid 9 by the heat conductive adhesive 10, so that heat dissipation can be improved.

【0021】この高熱伝導性蓋体9は、略四角形状から
なるものであって、その上面の大きさは、放熱性を最大
限に発揮するために、絶縁基板1のサイズとほぼ同じ大
きさに形成されている。そして、本発明によれば、この
高熱伝導性蓋体9における4つの最外縁部xよりも内側
の領域に、絶縁基板1への取付け用の脚部11が形成さ
れている。そして、この脚部11の端部は銀ペースト等
のロウ材12によって絶縁基板1における最外縁部より
も内側の領域に取り付けられている。
The high thermal conductive lid 9 has a substantially square shape, and its upper surface has a size substantially the same as the size of the insulating substrate 1 in order to maximize heat dissipation. Is formed. According to the present invention, the legs 11 for attachment to the insulating substrate 1 are formed in a region inside the four outermost edges x in the high thermal conductive lid 9. An end of the leg 11 is attached to a region inside the outermost edge of the insulating substrate 1 by a brazing material 12 such as a silver paste.

【0022】かかる構造において、半導体素子2の作動
/停止に伴う熱サイクルが繰り返し印加された場合、絶
縁基板1と外部回路基板Bとの間に両者の熱膨張係数の
相違に起因し、絶縁基板1には、半導体素子2搭載側が
凹となるような応力による反り変形が生じる。この反り
変形によって、パッケージの対角角部の接続端子5に生
じるせん断ひずみは低減されるが、高熱伝導性蓋体9と
絶縁基板1との取り付け用の脚部が、図5に示されるよ
うに高熱伝導性蓋体9の周縁部にそって枠状に形成され
ていたり、高熱伝導性蓋体9の対角角部の4隅に形成さ
れていると、絶縁基板1の反り変形が抑制されるため、
接続端子5に生じるせん断ひずみを緩和することができ
ない。
In such a structure, when a thermal cycle accompanying the operation / stop of the semiconductor element 2 is repeatedly applied, the insulating substrate 1 and the external circuit board B are caused by a difference in thermal expansion coefficient between the insulating substrate 1 and the external circuit board B. 1 is warped by stress such that the side on which the semiconductor element 2 is mounted becomes concave. Although the warp deformation reduces the shear strain generated in the connection terminals 5 at the diagonal corners of the package, the legs for attaching the high thermal conductive lid 9 and the insulating substrate 1 are provided as shown in FIG. If the insulating substrate 1 is formed in a frame shape along the peripheral portion of the high thermal conductive lid 9 or at four diagonal corners of the high thermal conductive lid 9, warpage of the insulating substrate 1 is suppressed. To be
The shear strain generated in the connection terminal 5 cannot be reduced.

【0023】これに対して、本発明のように、高熱伝導
性蓋体9の最外縁部より内側に脚部11を形成した場合
には、絶縁基板1の対角角部は拘束されていないため、
反ることができ、その結果、高熱伝導性蓋体9からの放
熱性を損なうことなく、対角角部の接続端子5のせん断
ひずみは大きく低減される。
On the other hand, when the legs 11 are formed inside the outermost edge of the high thermal conductive lid 9 as in the present invention, the diagonal corners of the insulating substrate 1 are not restricted. For,
As a result, the shear strain of the connection terminals 5 at the diagonal corners is greatly reduced without impairing the heat radiation from the high thermal conductive lid 9.

【0024】具体的には、脚部11の絶縁基板1との取
付け部の絶縁基板1の周縁部からの距離Lと、絶縁基板
1の一辺の長さDとの比(L/D)が0.1以上、特に
0.2以上であることが望ましい。
Specifically, the ratio (L / D) of the distance L from the peripheral portion of the insulating substrate 1 to the distance L from the peripheral portion of the insulating substrate 1 to the mounting portion of the leg portion 11 to the insulating substrate 1 is: Desirably, it is 0.1 or more, especially 0.2 or more.

【0025】また、脚部11の形状としては、図1に示
すように、キャップ形状の他に、図2(a)(b)に示
すように、高熱伝導性蓋体9の最外縁部から内側の領域
にて、4隅、または4つの辺部にそれぞれ4つの脚を設
けることも可能である。
As shown in FIG. 1, the shape of the legs 11 is not only the cap shape but also the outermost edge of the high heat conductive lid 9 as shown in FIGS. 2 (a) and 2 (b). It is also possible to provide four legs at each of the four corners or four sides in the inner area.

【0026】なお、高熱伝導性蓋体9の熱膨張係数が絶
縁基板1の熱膨張係数よりも大きい場合には、絶縁基板
1の周縁部に位置する接続端子5が、高熱伝導性蓋体9
と絶縁基板1の熱膨張差によって押しつぶされる恐れが
あるため、本発明のパッケージにおいては、高熱伝導性
蓋体9の熱膨張係数が絶縁基板1の熱膨張係数よりも小
さいことが望ましい。高熱伝導性蓋体9としては、かか
る観点から、アルミニウムとSiCとの複合材料からな
ることが最も望ましい。
When the thermal expansion coefficient of the high thermal conductive lid 9 is larger than the thermal expansion coefficient of the insulating substrate 1, the connection terminals 5 located on the peripheral edge of the insulating substrate 1 are connected to the high thermal conductive lid 9.
In the package of the present invention, it is preferable that the thermal expansion coefficient of the high thermal conductive lid 9 is smaller than the thermal expansion coefficient of the insulating substrate 1 because the thermal expansion coefficient of the insulating substrate 1 may cause crushing. From such a viewpoint, the high thermal conductive lid 9 is most preferably made of a composite material of aluminum and SiC.

【0027】なお、熱伝導性接着材10としては、種々
のものを適用できるが、熱伝導率の高いアルミナや銀な
どの粒子をフィラーとして分散させたグリスやシリコン
樹脂などの熱伝導シートなどが用いられる。
Various materials can be used as the heat conductive adhesive 10, but a heat conductive sheet such as grease or silicon resin in which particles of high heat conductivity such as alumina or silver are dispersed as a filler. Used.

【0028】前記絶縁基板1は、アルミナ、ムライト等
のセラミックス、あるいは低温焼成のガラスセラミック
スなどの電気絶縁材料から成るが、ガラスセラミックス
は、通常、アルミナセラミックス等に比較して低剛性で
あるために、絶縁基板1の反り変形によるせん断ひずみ
を緩和することができることから、本発明のパッケージ
においては絶縁基板1がガラスセラミックスからなるこ
とが望ましい。
The insulating substrate 1 is made of an electrical insulating material such as ceramics such as alumina and mullite or glass ceramics fired at a low temperature. However, glass ceramics usually have lower rigidity than alumina ceramics and the like. In addition, in the package of the present invention, it is preferable that the insulating substrate 1 is made of glass ceramic because the shear strain due to the warp deformation of the insulating substrate 1 can be reduced.

【0029】具体的に、アルミナセラミックスは、アル
ミナに対して、SiO2、MgO、CaOなどの焼結助
剤を含有し、例えば、アルミナおよび焼結助剤からなる
混合粉末に適当な有機バインダー、溶剤等を添加混合し
てスラリーを作るとともに、スラリーをドクターブレー
ド法やカレンダーロール法によってグリーンシート(生
シート)と作製し、しかる後、前記グリーンシートに適
当な打ち抜き加工を施すとともにこれを複数枚積層し、
1500〜1700℃の温度で焼成することによって作
製される。
Specifically, alumina ceramics contain sintering aids such as SiO 2 , MgO, and CaO with respect to alumina. For example, an organic binder suitable for a mixed powder of alumina and sintering aids; A slurry is prepared by adding and mixing a solvent and the like, and the slurry is formed into a green sheet (raw sheet) by a doctor blade method or a calendar roll method. Thereafter, the green sheet is subjected to an appropriate punching process and a plurality of sheets are formed. Laminated,
It is produced by firing at a temperature of 1500 to 1700 ° C.

【0030】従来の上記アルミナセラミックスは熱膨張
係数が6〜7×10-6/℃と、一般に外部回路基板とし
て用いられるガラスエポキシなどの有機系複合材料を絶
縁基板とするマザーボードなどの熱膨張係数が10〜2
5×10-6/℃のプリント配線基板よりも非常に小さ
く、熱膨張差により発生する応力が大きくなる。
The conventional alumina ceramic has a coefficient of thermal expansion of 6 to 7 × 10 −6 / ° C., which is a coefficient of thermal expansion of a mother board or the like having an insulating substrate made of an organic composite material such as glass epoxy generally used as an external circuit board. Is 10-2
It is much smaller than a printed wiring board of 5 × 10 −6 / ° C., and the stress generated due to the difference in thermal expansion becomes large.

【0031】このような熱膨張差に起因する応力を低減
するために、パッケージにおける熱膨張係数は8〜20
×10-6/℃であることが望ましい。
In order to reduce the stress caused by such a difference in thermal expansion, the thermal expansion coefficient of the package is 8 to 20.
It is desirable to be × 10 -6 / ° C.

【0032】このような熱膨張係数を有する絶縁材料と
しては、例えば、BaOを5乃至60重量%の割合で含
有する低軟化点、高熱膨張のガラスに対して、SiO2
(クオーツ)などの所定の高熱膨張性フィラーを40〜
80重量%の割合で混合して750〜1050℃で焼成
した高熱膨張性のガラスセラミックスが望ましい。その
他、高熱膨張のガラスセラミックスとしては、特開平1
0−167822号公報に記載されるような例えば、リ
チウム珪酸系ガラス、PbO系ガラス、ZnO系ガラ
ス、BaO系ガラス等のガラス成分にエンスタタイト、
フォルステライト、シリカなどの高熱膨張性のフィラ
ー、MgO、ZrO2、ペタライト等の各種セラミック
フィラーの複合材料を添加してなる複合材料が挙げられ
る。
As an insulating material having such a coefficient of thermal expansion, for example, a glass having a low softening point and a high thermal expansion containing BaO at a ratio of 5 to 60% by weight is made of SiO 2.
(Quartz) or other predetermined high thermal expansion filler
High thermal expansion glass ceramics mixed at a ratio of 80% by weight and fired at 750 to 1050 ° C. are desirable. In addition, as glass ceramics having high thermal expansion,
For example, enstatite may be added to glass components such as lithium silicate glass, PbO glass, ZnO glass, and BaO glass as described in JP-A-167822.
A composite material obtained by adding a composite material of a high thermal expansion filler such as forsterite and silica, and various ceramic fillers such as MgO, ZrO 2 and petalite is added.

【0033】また、前記メタライズ配線層3及び接続パ
ツド4は、絶縁基板材料によって適宜選択され、例え
ば、アルミナセラミックスからなる場合には、タングス
テン、モリブデン、マンガン等の高融点金属粉末から成
り、タングステン等の高融点金属粉末に適当な有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
や、ガラスセラミックスからなる場合には、Cu、A
u、Agなどの低抵抗金属を含む導体ペーストを絶縁基
板1となるグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布し、絶縁基板と同
時焼成することによって形成される。
The metallized wiring layer 3 and the connection pad 4 are appropriately selected depending on the material of the insulating substrate. Metal paste obtained by adding and mixing an appropriate organic binder, plasticizer, and solvent to the high melting point metal powder of
A conductor paste containing a low-resistance metal such as u or Ag is printed and applied in a predetermined pattern on a green sheet serving as the insulating substrate 1 by a conventionally known screen printing method, and is fired simultaneously with the insulating substrate.

【0034】尚、前記球状半田からなる接続端子5は、
例えば、絶縁基板1の接続パッド4に半田を塗布したも
の、半田を過剰に塗布し、しかる後、これを約150〜
250℃で加熱溶融させることによって溶融した半田の
表面張力によって球状としたもの、また、場合によって
は、高融点半田からなる球状半田を低融点半田によって
ロウ付けしたものであってもよい。
The connection terminal 5 made of the spherical solder is
For example, one in which solder is applied to the connection pads 4 of the insulating substrate 1, excessive solder is applied, and then,
The solder may be made into a spherical shape by the surface tension of the solder melted by being heated and melted at 250 ° C. In some cases, a spherical solder made of a high melting point solder may be soldered with a low melting point solder.

【0035】また、半導体素子2が搭載された上記半導
体素子収納用パッケージAは、前記球状半田からなる接
続端子5を外部回路基板B表面に形成された配線導体8
上に載置当接させ、しかる後、前記球状の接続端子5を
約150〜250℃の温度で加熱溶融し、球状半田から
なる接続端子5を配線導体8に接合させることによって
外部回路基板B上に実装される。
The semiconductor element housing package A on which the semiconductor element 2 is mounted is provided with a connection terminal 5 made of the spherical solder and a wiring conductor 8 formed on the surface of the external circuit board B.
Then, the spherical connection terminal 5 is heated and melted at a temperature of about 150 to 250 ° C., and the connection terminal 5 made of the spherical solder is joined to the wiring conductor 8. Implemented above.

【0036】[0036]

【実施例】表1に示す各種セラミック材料によって5×
4×40mmの形状の焼結体を作製した後、各焼結体に
ついてヤング率、および室温から400℃までの平均熱
膨張係数を測定し表1に示した。
Embodiments 5 × by various ceramic materials shown in Table 1.
After preparing sintered bodies having a shape of 4 × 40 mm, the Young's modulus and the average thermal expansion coefficient from room temperature to 400 ° C. of each sintered body were measured, and the results are shown in Table 1.

【0037】[0037]

【表1】 [Table 1]

【0038】次に、表1に示すガラスセラミック材料A
及びBを絶縁基板として用いて、その表面に半導体素子
と接続されるメタライズ配線層、内部配線層及びビアホ
ール導体、底面に導体を取りつけるための256個の接
続ランドを銅ペーストの印刷、あるいは充填により周知
の方法に従い900℃の温度で同時焼成してパッケージ
の基板を作製した。
Next, the glass ceramic material A shown in Table 1 was used.
Using B and B as an insulating substrate, a metallized wiring layer connected to a semiconductor element on its surface, an internal wiring layer and a via hole conductor, and 256 connection lands for attaching a conductor to the bottom surface are printed or filled with copper paste. A package substrate was manufactured by simultaneous firing at a temperature of 900 ° C. according to a known method.

【0039】また、絶縁材料として、表1の材料Cのア
ルミナセラミックスを、前記各導体材料としてタングス
テンを用いて1550℃で同時焼成して、上記と全く同
じ大きさのパッケージ基板を作製した。
As the insulating material, the alumina ceramic of the material C shown in Table 1 was simultaneously fired at 1550 ° C. using tungsten as each of the above-mentioned conductor materials, to produce a package substrate of exactly the same size as above.

【0040】半導体素子2としては、シリコン製(熱膨
張係数3ppm/℃)を用い、球状の接続端子5として
は、Sn63重量%−Pb37重量%の直径が0.7m
mの半田ボールによって形成した。
The semiconductor element 2 is made of silicon (coefficient of thermal expansion: 3 ppm / ° C.), and the spherical connection terminal 5 has a diameter of 63% by weight of Sn-37% by weight of Pb of 0.7 m in diameter.
m of solder balls.

【0041】なお、パッケージのサイズは、絶縁基板1
が縦17mm×横17mm×厚さ0.75mm、また、
この絶縁基板上に搭載する半導体素子は縦9mm×横9
mm×厚さ0.3mmである。また、パッケージにおけ
る接続パッド径は0.6mm、接続パッドのピッチは1
mmである。
The size of the package is the same as that of the insulating substrate 1.
Is 17mm long x 17mm wide x 0.75mm thick,
The semiconductor element mounted on this insulating substrate has a length of 9 mm and a width of 9 mm.
mm × thickness 0.3 mm. The connection pad diameter in the package is 0.6 mm, and the connection pad pitch is 1 mm.
mm.

【0042】高熱伝導性蓋体は、アルミニウムに炭化珪
素を30〜80重量%含有した、熱膨張係数が4×10
-6/℃、8×10-6/℃、12×10-6/℃の3種の材
料を用いた。
The high thermal conductive lid is made of aluminum containing 30 to 80% by weight of silicon carbide and having a coefficient of thermal expansion of 4 × 10
-6 / ° C., 8 × 10 -6 / ° C., and 12 × 10 -6 / ° C. were used.

【0043】また、高熱伝導性蓋体の形状としては、図
1に示すようなキャップ形状とし、その外形形状は、縦
13mm×横13mm×厚み1.5mm、縦15mm×
横15mm×厚み1.5mm、縦17mm×横17mm
×厚み1.5mmの3種準備し、周縁部から脚部の距離
Lを0mm、1.5mm、3mmの3種類のものを作製
した。
The shape of the high thermal conductive lid is a cap shape as shown in FIG. 1, and its outer shape is 13 mm long × 13 mm wide × 1.5 mm thick, 15 mm long ×
15mm wide x 1.5mm thick, 17mm long x 17mm wide
× Three types of 1.5 mm thick were prepared, and three types of three types were prepared in which the distance L from the periphery to the leg was 0 mm, 1.5 mm, and 3 mm.

【0044】そして、絶縁基板との取り付けにあたり、
図1のように、蓋体最外縁から内側に脚部を配置した本
発明の高熱伝導性蓋体(タイプ、)と、比較のため
に、L=0の脚部が蓋体の最外縁に位置するキャップ形
状の高熱伝導性蓋体(タイプ、、)を用意した。
Then, upon attaching the insulating substrate,
As shown in FIG. 1, the highly heat-conductive lid (type) of the present invention in which the legs are arranged inside from the outermost edge of the lid, and for comparison, the legs of L = 0 are located on the outermost edge of the lid. A cap-shaped high thermal conductive lid (type,) was prepared.

【0045】一方、外部回路基板として、ガラス−エポ
キシ基板からなる20℃からガラス転移温度までの平均
熱膨張係数が15ppm/℃の絶縁体の表面に銅箔から
なるランド部が形成されたプリント基板を準備した。
On the other hand, as an external circuit board, a printed circuit board having a land portion made of a copper foil formed on the surface of an insulator made of a glass-epoxy substrate and having an average coefficient of thermal expansion from 20 ° C. to a glass transition temperature of 15 ppm / ° C. Was prepared.

【0046】そして、上記プリント基板のランド部に半
田(Sn63重量%−Pb37重量%)ペーストをスク
リーン印刷により塗布した後、上記のパッケージの接続
端子と上記プリント基板のランド部とを位置合わせし、
加熱溶融させてパッケージをプリント基板表面に実装し
た。外部回路基板としては、縦67mm×横67mm×
厚さ1.25mmのものを使用した。
After a solder (Sn 63% by weight-Pb 37% by weight) paste is applied to the land of the printed board by screen printing, the connection terminals of the package and the land of the printed board are aligned.
The package was mounted on the surface of the printed circuit board by heating and melting. As an external circuit board, 67 mm long x 67 mm wide x
The one having a thickness of 1.25 mm was used.

【0047】次に、上記のようにしてパッケージ基板を
プリント基板表面に実装したものを大気の雰囲気にて−
40℃と125℃の各温度に制御した恒温槽に試験サン
プルを15分/15分の保持を1サイクルとして最高1
700サイクルまで繰り返した。
Next, the package substrate mounted on the printed circuit board surface as described above was placed in an air atmosphere.
A maximum of 1 cycle of holding the test sample for 15 minutes / 15 minutes in a thermostat controlled at each temperature of 40 ° C. and 125 ° C.
This was repeated up to 700 cycles.

【0048】そして、各サイクル毎にプリント基板の配
線導体とパッケージ基板との電気抵抗を100サイクル
毎に測定し、電気抵抗に変化が現れるまでのサイクル数
を表2に示した。
Then, the electric resistance between the wiring conductor of the printed circuit board and the package substrate was measured every 100 cycles for each cycle, and Table 2 shows the number of cycles until the electric resistance changed.

【0049】また、高熱伝導性蓋体の形状による放熱性
の違いを調べるために、半導体素子2の代わりに同一形
状のアルミナ製のヒーターチップをパッケージ基板にS
n63重量%、Pb37重量%の半田で実装したものを
作製した。該パッケージ基板のヒーターチップに通電
し、模擬的に発熱させ、その際のパッケージ基板の定常
状態の温度分布を放射温度計により測定し、高熱伝導性
蓋体の形状が、高熱伝導性蓋体の放熱性に及ぼす影響を
調べた。ヒーターチップの温度を最大サイズの高熱伝導
性蓋体の場合のヒーターチップの温度で規格化した値を
表2に合わせて示した。
Further, in order to examine the difference in heat radiation due to the shape of the high thermal conductive lid, an alumina heater chip of the same shape was used instead of the semiconductor element 2 on the package substrate.
A package mounted with n63% by weight and Pb37% by weight was prepared. The heater chip of the package substrate is energized to simulate heat generation, and the steady-state temperature distribution of the package substrate at that time is measured by a radiation thermometer, and the shape of the high thermal conductive lid is The effect on heat dissipation was investigated. Table 2 also shows values obtained by normalizing the temperature of the heater chip with the temperature of the heater chip in the case of the maximum size high thermal conductive lid.

【0050】[0050]

【表2】 [Table 2]

【0051】表2より明らかなように、高熱伝導性蓋体
の脚部を該蓋体の最外縁部より内側に設けたタイプ、
のパッケージでは、何れも1000サイクルまで抵抗
変化は全く認められず、良好な電気的接続状態を維持で
きた。特に、高熱伝導性蓋体の熱膨張係数が絶縁基板の
熱膨張係数よりも小さい場合、及び絶縁基板がガラスセ
ラミック焼結体である場合において、極めて安定で良好
な電気的接続状態を維持できている。また、チップ温度
比においても、最大サイズの高熱伝導性蓋体と同等の放
熱性を維持できていることがわかった。
As is clear from Table 2, the type in which the legs of the high thermal conductive lid were provided inside the outermost edge of the lid,
In each package, no change in resistance was observed at all up to 1000 cycles, and a favorable electrical connection state could be maintained. In particular, when the thermal expansion coefficient of the high thermal conductive lid is smaller than the thermal expansion coefficient of the insulating substrate, and when the insulating substrate is a glass ceramic sintered body, an extremely stable and good electrical connection state can be maintained. I have. In addition, it was found that the same heat radiation property as that of the largest-sized high-thermal-conductivity lid could be maintained in the chip temperature ratio.

【0052】しかし、従来の高熱伝導性蓋体であるタイ
プのパッケージでは、チップ温度比における該蓋体の
放熱性は十分確保されているが、1000サイクル未満
の早い段階から抵抗変化が検出され、実装後の信頼性に
欠けることがわかった。また、電気的接続状態の改善の
ために、該蓋体の外形サイズを小さくしたタイプ、
のパッケージでは、電気的接続性に対する信頼性は改善
されるものの、チップ温度比が増加し高熱伝導性蓋体の
放熱性が悪化していることがわかった。
However, in a conventional package of a type having a high thermal conductive lid, although the heat radiation of the lid at the chip temperature ratio is sufficiently ensured, a change in resistance is detected from an early stage of less than 1000 cycles. It was found that the reliability after mounting was lacking. In addition, in order to improve the electrical connection state, a type in which the outer size of the lid is reduced,
In this package, although the reliability with respect to the electrical connectivity was improved, it was found that the chip temperature ratio was increased and the heat radiation of the high thermal conductive lid was deteriorated.

【0053】[0053]

【発明の効果】以上詳述した通り、本発明によれば、絶
縁基板と高熱伝導性蓋体との取り付けを高熱伝導性蓋体
の最外縁よりも内側に設けた脚部によって行なうことに
よって、高熱伝導性蓋体の放熱性を損なうことなく、接
続端子に外部回路基板と絶縁基板との熱膨張差によるせ
ん断ひずみが生じた場合においても、高熱伝導性蓋体が
絶縁基板の反り変形を拘束することなく、接続端子への
せん断応力の発生を抑制し、パッケージを外部回路基板
に対して長期間にわたり安定に電気的接続させることが
可能となる。
As described in detail above, according to the present invention, the mounting of the insulating substrate and the high thermal conductive lid is performed by the legs provided inside the outermost edge of the high thermal conductive lid. The high thermal conductive lid restrains the warping of the insulating substrate even if shear strain occurs due to the difference in thermal expansion between the external circuit board and the insulating substrate without damaging the heat dissipation of the high thermal conductive lid. Therefore, it is possible to suppress the generation of shear stress on the connection terminals and to stably electrically connect the package to the external circuit board for a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージを説明す
るための(a)概略断面図と、(b)上面図である。
FIGS. 1A and 1B are a schematic cross-sectional view and a top view, respectively, for explaining a semiconductor element storage package according to the present invention.

【図2】本発明の半導体素子収納用パッケージにおける
高熱伝導性蓋体の他の構造を説明するための図である。
FIG. 2 is a view for explaining another structure of the high thermal conductive lid in the package for housing a semiconductor element of the present invention.

【図3】従来の半導体素子収納用パッケージを説明する
ための概略断面図である。
FIG. 3 is a schematic cross-sectional view for explaining a conventional semiconductor element storage package.

【図4】従来の他の半導体素子収納用パッケージを説明
するための概略断面図である。
FIG. 4 is a schematic cross-sectional view for explaining another conventional semiconductor element storage package.

【図5】従来の半導体素子収納用パッケージの高熱伝導
性蓋体の構造を説明するためのものである。
FIG. 5 is a view for explaining the structure of a conventional high thermal conductive lid of a package for housing a semiconductor element.

【符号の説明】 A 半導体素子収納用パッケージ B 外部回路基板 1 絶縁基板 2 半導体素子 3 メタライズ配線層 4 接続パッド 5,6 接続端子 7 熱硬化性樹脂 8 配線導体 9 高熱伝導性蓋体 10 熱伝導性接着材 11 脚部[Description of Symbols] A Package for storing semiconductor element B External circuit board 1 Insulating substrate 2 Semiconductor element 3 Metallized wiring layer 4 Connection pad 5, 6 Connection terminal 7 Thermosetting resin 8 Wiring conductor 9 High heat conductive lid 10 Heat conduction Adhesive 11 legs

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】メタライズ配線層が被着形成された略四角
形状の絶縁基板の表面に、接続用電極を備えた半導体素
子を載置し、前記メタライズ配線層と前記半導体素子の
接続用電極とをロウ付けしてなるとともに、前記半導体
素子を覆うようにして前記絶縁基板表面に取着され且つ
その一部を前記半導体素子の上面と接着してなる高熱伝
導性蓋体と、前記絶縁基板裏面に設けられ前記半導体素
子と電気的に接続された半田からなる複数の接続端子と
を具備し、前記高熱伝導性蓋体が、略四角形状からな
り、且つ該略四角形状の各縁部に脚部が設けられてお
り、該脚部と前記絶縁基板とを取着してなる半導体素子
収納用パッケージであって、該脚部が、該蓋体の最外縁
部よりも内側に設けたことを特徴とする半導体素子収納
用パッケージ。
A semiconductor device having a connection electrode is mounted on a surface of a substantially rectangular insulating substrate on which a metallized wiring layer is formed, and the metallized wiring layer is connected to a connection electrode of the semiconductor device. A high thermal conductive lid attached to the surface of the insulating substrate so as to cover the semiconductor element, and a part thereof is adhered to the upper surface of the semiconductor element; And a plurality of connection terminals made of solder electrically connected to the semiconductor element, wherein the high thermal conductive lid has a substantially square shape, and a leg is attached to each edge of the substantially square shape. A semiconductor element housing package comprising the legs and the insulating substrate attached to each other, wherein the legs are provided inside the outermost edge of the lid. Characteristic semiconductor element storage package.
【請求項2】前記高熱伝導性蓋体の熱膨張係数が、前記
絶縁基板の熱膨張係数よりも小さいことを特徴とする請
求項1記載の半導体素子収納用パッケージ。
2. The package for accommodating a semiconductor element according to claim 1, wherein the thermal expansion coefficient of the high thermal conductive lid is smaller than the thermal expansion coefficient of the insulating substrate.
【請求項3】前記半導体素子の上面を、高熱伝導性接着
材によって前記高熱伝導性蓋体に接着してなる請求項1
記載の半導体素子収納用パッケージ。
3. The semiconductor device according to claim 1, wherein an upper surface of the semiconductor element is bonded to the high thermal conductive lid with a high thermal conductive adhesive.
The package for housing a semiconductor element according to the above.
【請求項4】前記高熱伝導性蓋体が、アルミニウムとS
iCとの複合材料からなる請求項1記載の半導体素子収
納用パッケージ。
4. The high thermal conductive lid is made of aluminum and sulfur.
2. The package for accommodating a semiconductor element according to claim 1, comprising a composite material with iC.
【請求項5】前記絶縁基板が、ガラスセラミックスから
なり、前記メタライズ配線層が銅を主成分とする導体か
らなる請求項1記載の半導体素子収納用パッケージ。
5. The package according to claim 1, wherein said insulating substrate is made of glass ceramics, and said metallized wiring layer is made of a conductor containing copper as a main component.
【請求項6】前記半導体素子が前記絶縁基板表面のメタ
ライズ配線層に、フリップチップ実装してなる請求項1
記載の半導体素子収納用パッケージ。
6. The semiconductor device according to claim 1, wherein said semiconductor element is flip-chip mounted on a metallized wiring layer on a surface of said insulating substrate.
The package for housing a semiconductor element according to the above.
JP2000160751A 2000-05-30 2000-05-30 Semiconductor element storing package Pending JP2001338999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000160751A JP2001338999A (en) 2000-05-30 2000-05-30 Semiconductor element storing package

Publications (1)

Publication Number Publication Date
JP2001338999A true JP2001338999A (en) 2001-12-07

Family

ID=18664897

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Application Number Title Priority Date Filing Date
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Country Link
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