JPH03167850A - Package for semiconductor-element - Google Patents

Package for semiconductor-element

Info

Publication number
JPH03167850A
JPH03167850A JP30859489A JP30859489A JPH03167850A JP H03167850 A JPH03167850 A JP H03167850A JP 30859489 A JP30859489 A JP 30859489A JP 30859489 A JP30859489 A JP 30859489A JP H03167850 A JPH03167850 A JP H03167850A
Authority
JP
Japan
Prior art keywords
external lead
semiconductor element
lid
lead terminal
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30859489A
Other languages
Japanese (ja)
Other versions
JP2736451B2 (en
Inventor
Hiroshi Matsumoto
弘 松本
Masaaki Iguchi
井口 公明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1308594A priority Critical patent/JP2736451B2/en
Priority to US07/574,472 priority patent/US5168126A/en
Publication of JPH03167850A publication Critical patent/JPH03167850A/en
Application granted granted Critical
Publication of JP2736451B2 publication Critical patent/JP2736451B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To firmly bond blanks by a method wherein the outer surface of a core body, which is composed of an alloy of Ni and Fe at respectively specific wt.%, of an external lead terminal is covered with a covering layer composed of copper and the terminal is constituted of a metal body in which a cross-sectional area of the covering layer is a specific wt.% of a cross-sectional area of the core body. CONSTITUTION:External lead terminals 5 composed of a conductive material are arranged between an insulating substrate 1 and a lid body 2; the terminals 5 are connected electrically to individual electrodes of a semiconductor element 4 via wires 7; the external lead terminals 5 are connected to an external electric circuit; the semiconductor element 4 is connected to the external circuit. In this case, the insulating substrate 1 and the lid body 2 are covered with at least one kind out of an aluminum nitride sintered substance and a mullite sintered substance. On the other hand, the lead terminals 5 are attached and bonded simultaneously between the substrate 1 and the lid body 2 when glass members 6, for sealing use, applied to opposite main faces of the substrate 1 and the lid body 2 are melted and united and an insulating container 3 is sealed airtightly.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体素子を収容する半導体素子収納用パフケ
ージの改良に叩するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention is directed towards improving a puff cage for storing semiconductor elements.

(従来の技術) 従来、半導体素子を収容するためのパッケージ、特にガ
ラスの溶着によって封止するガラス封止型半導体素子収
納用パッケージは、絶縁基体と蓋体とから成り、内部に
半導体素子を収容する空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に電気的に接
続するための外部リード端子とから構威されており、絶
縁基体及び蓋体の相対向する主面に予め封止用のガラス
部材を被着形或すると共に、絶縁基体主面に外部リード
端子を固定し、半導体素子の各電極と外部リード端子と
をワイヤボンド接続した後、絶縁基体及び蓋体のそれぞ
に被着させた封止用のガラス部材を溶融一体化させるこ
とによって内部に半導体素子を気密に封止している。
(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a glass-sealed semiconductor element accommodating package sealed by glass welding, consists of an insulating base and a lid body, and the semiconductor element is housed inside. The structure consists of an insulating container having a cavity, and an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit, and an insulating base and a lid facing each other. A glass member for sealing is preliminarily applied to the main surface of the insulating substrate, external lead terminals are fixed to the main surface of the insulating substrate, and each electrode of the semiconductor element and the external lead terminal are connected by wire bonding, and then the insulating substrate and A semiconductor element is hermetically sealed inside by melting and integrating a sealing glass member attached to each lid.

(発明が解決しようとする課題) しかし乍ら、この従来のガラス封止型半導体素子収納用
パッケージは通常、外部リード端子がコバーJlz(2
9 WLX Ni−16 WtX Co−55 WtX
Fe合金)や42A11oy(42 WtχNi−58
 WtX Fe合金)の導電性材料から戒っており、該
コバールや42AIIoy等は導電率が低いことから以
下に述べる欠点を有する。
(Problem to be Solved by the Invention) However, in this conventional glass-sealed semiconductor element housing package, the external lead terminals are usually
9 WLX Ni-16 WtX Co-55 WtX
Fe alloy) and 42A11oy (42 WtχNi-58
(WtX Fe alloy), and Kovar, 42AIIoy, etc. have the following disadvantages due to their low conductivity.

即ち、 ■コバールや42A 1 1oyはその導電率が3.0
〜3.5χ(IACS)と低い。そのためこのコハール
や42A 1 joy等から成る外部リード端子に信号
を伝搬させた場合、信号の伝搬速度が極めて遅いものと
なり、高速駆動を行う半導体素子はその収容が不可とな
ってしまう、 ■半導体素子収納用パソケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記のに
記載のコバールや42A11oyの導電率が低いことと
相俊って電気抵抗が極めて大きなものになってきており
、外部リード端子に信号を伝搬させると、該外部リード
端子の電気抵抗に起因して信号が大きく減衰し、内部に
収容する半導体素子に信号を正確に入力することができ
ず、半導体素子に誤動作を生じさせてしまう、 等の欠点を有していた。
That is, ■ Kovar and 42A 1 1oy have an electrical conductivity of 3.0.
It is low at ~3.5χ (IACS). Therefore, when a signal is propagated to an external lead terminal made of Kohar, 42A 1 joy, etc., the signal propagation speed becomes extremely slow, making it impossible to accommodate semiconductor devices that drive at high speed. ■Semiconductor device With the progress of higher density and higher integration of the semiconductor devices housed inside the storage path cage, the number of electrodes of the semiconductor devices has increased significantly, and the number of external leads that connect each electrode of the semiconductor device to the external electric circuit is increasing. The line width of terminals is also becoming extremely thin. Therefore, the electrical resistance of the external lead terminal has become extremely large due to the low conductivity of Kovar and 42A11oy described above, and when a signal is propagated to the external lead terminal, The signal is greatly attenuated due to the electrical resistance of the device, making it impossible to accurately input the signal to the semiconductor device housed inside the device, resulting in malfunction of the semiconductor device.

(発明の目的) 本発明は上記欠点に鑑み案出されたもので、その目的は
外部リード端子における信号の減衰を極小となし、内部
に収容する半導体素子への信号の入出力を確実に行うこ
とを可能として半導体素子を長期間にわたり正常、且つ
安定に作動させることができる半導体素子収納用パンヶ
ージを提供することにある。
(Object of the Invention) The present invention was devised in view of the above drawbacks, and its purpose is to minimize the attenuation of signals at external lead terminals and ensure the input and output of signals to and from semiconductor elements housed inside. It is an object of the present invention to provide a pan cage for storing semiconductor elements, which allows the semiconductor elements to operate normally and stably for a long period of time.

また本発明の他の目的は高速駆動を行う半導体素子を収
容することができる半導体素子収納用パンケージを提供
することにある。
Another object of the present invention is to provide a semiconductor device storage pancase that can accommodate semiconductor devices that are driven at high speed.

(課題を解決するこめの手段) 本発明は絶縁基体と蓋体とから成り、内部に半導体素子
を収容するための空所を有する絶縁容器と、該容器内に
収容される半導体素子を外部電気回路に接続するための
外部リード端子とから成る半導体素子収納用バッケージ
において、前記絶縁基体及び蓋体を窒化アルミニウム質
焼結体、ムライト質焼結体、ジルコン質焼結体の少なく
とも1種で、外部リード端子をニッケル41.5乃至4
2.5WtX 、鉄57.5乃至58.5Wtχの合金
から成る芯体の外表面を銅から成る被覆層で被覆すると
共に、被覆層の断面積を芯体の断面積の20乃至40χ
とした金属体で形成したことを特徴とするものである.
(実施例) 次に本発明を添付図面に基づき詳細に説明する.第1図
及び第2図は本発明の半導体素子収納用バッケージの一
実施例を示し、■は絶縁基体、2は蓋体である。この絶
縁基体lと蓋体2とにより絶縁容器3が構戒される。
(Further Means for Solving the Problems) The present invention provides an insulating container consisting of an insulating base and a lid and having a cavity for accommodating a semiconductor element therein, and an insulating container that allows the semiconductor element housed in the container to be In a package for storing a semiconductor element comprising an external lead terminal for connection to a circuit, the insulating base and the lid are made of at least one of an aluminum nitride sintered body, a mullite sintered body, and a zircon sintered body, Nickel 41.5 to 4 for the external lead terminal
The outer surface of the core made of an alloy of 2.5 Wt
It is characterized by being made of a metal body.
(Example) Next, the present invention will be explained in detail based on the attached drawings. FIGS. 1 and 2 show an embodiment of a semiconductor element storage package according to the present invention, where .largecircle. is an insulating base and 2 is a lid. The insulating container 3 is secured by the insulating base 1 and the lid 2.

前記絶縁基体1及び蓋体2はそれぞれの中央部に半導体
素子を収容する空所を形戊するための凹部が設けてあり
、′f,gA縁基体1の凹部底面には半導体素子4が樹
脂、ガラス、ロウ剤等の接着剤を介し取着固定される。
The insulating base body 1 and the lid body 2 are each provided with a recessed portion in the center thereof to form a cavity for accommodating a semiconductor element, and the semiconductor element 4 is placed on the bottom surface of the recessed portion of the base body 1 at the edges 'f,gA'. , glass, wax, or other adhesive.

前記絶縁基体1及び蓋体2は窒化アルごニウム?焼結体
、ムライト質焼結体、ジルコン賞焼結体の少なくともl
種から成り、第l図に示すような絶8!基体1及び蓋体
2に対応した形状を有するプレス型内に、窒化アルミニ
ウム質焼結体の場合は窒化アルミニウム(AIN) 、
イソトリア(yzoi)等の原料粉末を、ムライト質焼
結体の場合はアルミナ(Al■03)、シリカ(SiO
z)等の原料粉末を、ジルコン質焼結体の場合は酸化ジ
ルコニウム(ZrO■)、シリカ(Si02)等の原料
粉末を充填させるとともに一定圧力を印加して或形し、
しかる後、戒形晶を約1300〜1800゜Cの温度で
焼戒することによって製作される。
Is the insulating base 1 and lid 2 made of argonium nitride? At least 1 of a sintered body, a mullite sintered body, and a zircon prize sintered body
It consists of seeds and has a variety of seeds as shown in Figure 1. In the case of an aluminum nitride sintered body, aluminum nitride (AIN),
Raw material powder such as isotria (yzoi), alumina (Al 03), silica (SiO
In the case of a zircon-based sintered body, raw material powder such as
After that, it is produced by burning the crystals at a temperature of approximately 1,300 to 1,800 degrees Celsius.

尚、前記絶縁基体I及び蓋体2を形成する窒化アルミニ
ウム質焼結体、ムライト質焼結体、ジルコン質焼結体は
その熱膨張係数が40〜50 x 10−’/“Cであ
り、後述する封止用ガラス部材の熱膨張係数との関係に
おいて應縁基体1及び蓋体2と封止用ガラス部材間に大
きな熱膨張の差が生しることはない。
The aluminum nitride sintered body, mullite sintered body, and zirconium sintered body forming the insulating substrate I and the lid 2 have a thermal expansion coefficient of 40 to 50 x 10-'/"C, In relation to the coefficient of thermal expansion of the sealing glass member, which will be described later, there is no large difference in thermal expansion between the rim base 1 and lid 2 and the sealing glass member.

またi?;7記絶縁基体1及び蓋体2にはその相対向す
る主面に封止用のガラス部材6が予め被着形戒されてお
り、該絶縁基体1及び蓋体2の各々に被着されている封
止用ガラス部材6を加熱溶融させ一体化させることによ
り絶縁容器3内の半導体素子4を気密に封止する。
i again? ; 7. The insulating base 1 and the lid 2 have sealing glass members 6 adhered to their opposing main surfaces in advance; The semiconductor element 4 in the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 that is included in the insulating container 3 and integrating the sealing glass member 6 .

前記絶縁基体1及び蓋体2の相対向する主面に被着され
る封止用ガラス部材6は、例えばホウケイ酸鉛系ガラス
にフイラーを添加したものから或り、原料粉末としての
酸化鉛( PbO )70.0〜90.OwtX 、酸
化*ウ素( )h(h )12.0〜13.OWtX 
, ’/リカ(SiOz)0.5 〜3.O Wt%及
びアルξナ(Altos)0.5〜3.O WtX ニ
7 イラーとしテチタン酸鉛(PbTiOi)、β−ユ
ークリプタイト(LiJbSizOs) 、コージライ
ト(Mgz^14Si50ts)、ジルコン(ZrSi
O4)、酸化スズ(SnOz)、ウイレマイト(Znt
Si04)等を30〜50VoI%添加混合すると共に
、該混合粉末を950〜1100℃の塩度で加熱溶融さ
せることによって製作される.このフィラーを添加した
ホウケイ酸鉛系のガラスはその熱膨張係数が40〜60
xlO−’/ ℃である.前記封止用ガラス部材6はそ
の熱膨張係数が40〜60X10−’/ ’Cであり、
絶縁基体l及び蓋体2の各々の熱膨張係数と近似するこ
とから絶縁基体1及び蓋体2の各々に被着されている封
止用ガラス部材6を加熱溶融させ一体化させることによ
り絶縁容器3内の半導体素子4を気密に封止する際、k
Th 8&基体1及び蓋体2と封止用ガラス部材6との
間には両者の熱膨張係数の相違に起因する熱応力が発生
することは殆どなく、絶縁基体1と蓋体2とを封止用ガ
ラス部材6を介し強固に接合することが可能となる。
The sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2 is made of, for example, lead borosilicate glass with a filler added, or lead oxide (lead oxide) as a raw material powder. PbO ) 70.0-90. OwtX, urin oxide ( ) h (h ) 12.0-13. OWtX
, '/Rica (SiOz) 0.5 ~ 3. O Wt% and Altos 0.5-3. O WtX Ni7 lead titanate (PbTiOi), β-eucryptite (LiJbSizOs), cordierite (Mgz^14Si50ts), zircon (ZrSi
O4), tin oxide (SnOz), willemite (Znt
It is produced by adding and mixing 30 to 50 VoI% of Si04), etc., and heating and melting the mixed powder at a salinity of 950 to 1100°C. Lead borosilicate glass added with this filler has a coefficient of thermal expansion of 40 to 60.
xlO-'/°C. The sealing glass member 6 has a thermal expansion coefficient of 40 to 60X10-'/'C,
Since the coefficients of thermal expansion are similar to those of the insulating base 1 and the lid 2, the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is heated and melted to form an insulating container. When the semiconductor element 4 in 3 is hermetically sealed, k
Th 8 & There is almost no thermal stress generated between the base 1 and the lid 2 and the sealing glass member 6 due to the difference in coefficient of thermal expansion between the two, and it is possible to seal the insulating base 1 and the lid 2. It becomes possible to firmly join them through the stopper glass member 6.

尚、前記封止用ガラス部材6はフィラーを添加したホウ
ケイ酸鉛系ガラスの粉末に適当な有機溶剤、溶媒を添加
して得たガラスペーストを従来周知の厚膜手法を採用す
ることによって絶縁基体1及び蓋体2の相対向する主面
に被着形或される。
The sealing glass member 6 is made by applying a well-known thick film method to a glass paste obtained by adding a suitable organic solvent to a filler-added lead borosilicate glass powder to form an insulating substrate. 1 and the lid body 2, which face each other, are adhered to each other.

また前記封止用ガラス部材6はフィラーを添加したホウ
ケイ酸鉛系のガラスに限定されるものではなく、熱膨張
係数が40〜60X1G−’/ ’Cの範囲のガラスで
あればいかなるものでも使用することができる。
Furthermore, the sealing glass member 6 is not limited to lead borosilicate glass containing filler, but any glass having a coefficient of thermal expansion in the range of 40 to 60X1G-'/'C can be used. can do.

前記絶縁基体lと蓋体2との間には導電性材料から戒る
外部リード端子5が配されており、該外部リード端子5
は半導体素子4の各電極がワイヤ7を介し電気的に接続
され、外部リード端子5を外部電気回路に接続すること
によって半導体素子4が外部電気回路に接続されること
となる。
An external lead terminal 5 made of conductive material is disposed between the insulating base l and the lid 2.
Each electrode of the semiconductor element 4 is electrically connected via the wire 7, and the semiconductor element 4 is connected to the external electric circuit by connecting the external lead terminal 5 to the external electric circuit.

前記外部リード端子5は絶縁基体lと蓋体2の相対向す
る主面に被着させた封止用ガラス部材6を熔融一体化さ
せ、絶縁容器3を気密封止する際に同時に絶縁基体1と
蓋体2との間に取着される.前記外部リード端子5はニ
ッケル41.5乃至42.5WtZ 、鉄57.5乃至
58.5Wt! (7)合金から戒る芯体の外表面を銅
から戒る被覆層で被覆すると共に、被覆層の断面積を芯
体の断面積の20乃至40Xとした金属体から戒り、そ
の導電率は27.22(IACS)、熱一膨張係数は約
49xlO−’/ ℃である。
The external lead terminal 5 is formed by melting and integrating the sealing glass member 6 attached to the opposing main surfaces of the insulating base l and the lid 2, and simultaneously sealing the insulating base 1 when the insulating container 3 is hermetically sealed. and lid body 2. The external lead terminal 5 is made of 41.5 to 42.5 WtZ of nickel and 57.5 to 58.5 Wt of iron! (7) The outer surface of the core made from an alloy is coated with a coating layer made from copper, and the cross-sectional area of the coating layer is made to be 20 to 40 times the cross-sectional area of the core. is 27.22 (IACS), and the coefficient of thermal expansion is approximately 49xlO-'/°C.

尚、前記外部リード端子5はニッケルー鉄合金(Ni−
Fe合金)のインゴソトの外表面に銅(Cu)を圧接し
、しかる後、これを圧延することによって形戒される。
The external lead terminal 5 is made of nickel-iron alloy (Ni-iron alloy).
Copper (Cu) is pressed onto the outer surface of an ingot made of (Fe alloy) and then rolled.

また前記外部リード端子5はニッケル(Ni)、鉄(F
e)の量及び芯体と被覆層の断面積は上述の範囲を外れ
ると外部リード端子5の導電率が所望する大きな値にな
らなくなると共に、熱膨張係数が絶縁基体及び蓋体の熱
膨張係数と合わなくなる。そのため外部リード端子5は
ニッケル4l.5乃至42.5WtX ,鉄57.5乃
至58.5WtX 77)合金カラ成ル芯体の外表面を
銅から成る被覆層で被覆すると共に、被覆層の断面積を
芯体の断面積の20乃至40%とした金属体で形或する
ことに振定される。
Further, the external lead terminal 5 is made of nickel (Ni), iron (F).
If the amount of e) and the cross-sectional area of the core and the cover layer are out of the above range, the conductivity of the external lead terminal 5 will not reach the desired large value, and the thermal expansion coefficient will be lower than that of the insulating base and the cover. It won't match. Therefore, the external lead terminal 5 is made of nickel 4l. 5 to 42.5 WtX, iron 57.5 to 58.5 Wt It is determined that the shape is made of a metal body with a ratio of 40%.

前記外部リード端子5はその導電率が27.22(IA
CS)であり、電気を流し易いことから外部リード端子
5の信号伝搬速度を極めて速いものとなすことができ、
絶縁容器3内に収容した半導体素子4を高速駆動させた
としても半導体素子4と外部電気回路との間における信
号の出し入れは常に安定、且つ確実となすことができる
The external lead terminal 5 has a conductivity of 27.22 (IA
CS), and since it is easy to conduct electricity, the signal propagation speed of the external lead terminal 5 can be made extremely fast.
Even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, signals can always be sent in and out between the semiconductor element 4 and the external electric circuit stably and reliably.

また外部リード端子5の導電率が高いことから外部リー
ド端子5の線幅が細くなったとしても外部リード端子5
の電気抵抗を低く抑えることができ、その結果、外部リ
ード端子5における信号の減衰を極小として内部に収容
する半導体素子4に外部電気回路から供給される電気信
号を正確に入力することができる。
Furthermore, since the conductivity of the external lead terminal 5 is high, even if the line width of the external lead terminal 5 becomes thin, the external lead terminal 5
As a result, the attenuation of the signal at the external lead terminal 5 is minimized, and the electrical signal supplied from the external electrical circuit can be accurately input to the semiconductor element 4 housed inside.

更に前記外部リード端子5はその熱膨張係数が約49x
lO−’/ ℃であり、封止用ガラス部材6の熱膨張係
数と近似することから外部リード端子5を絶縁基体1と
蓋体2の間に封止用ガラス部材6を用いて固定する際、
外部リード端子5と封止用ガラス部材6との間には両者
の熱膨張係数の相違に起因する熱応力が発生することは
なく、外部リード端子5を封止用ガラス部材6で強固に
固定することも可能となる。
Furthermore, the external lead terminal 5 has a coefficient of thermal expansion of about 49x.
lO-'/°C, which approximates the coefficient of thermal expansion of the sealing glass member 6. Therefore, when fixing the external lead terminal 5 between the insulating base 1 and the lid 2 using the sealing glass member 6, ,
No thermal stress is generated between the external lead terminal 5 and the sealing glass member 6 due to the difference in coefficient of thermal expansion between the two, and the external lead terminal 5 is firmly fixed by the sealing glass member 6. It is also possible to do so.

かくして、この半導体素子収納用パッケージによれば絶
縁基体1の凹部底面に半導体素子4を取着固定するとと
もに該半導体素子4の各電極をポンディングワイヤ7に
より外部リード端子5に接続させ、しかる後、絶縁基体
1と蓋体2とを該絶縁基体1及び蓋体2の相対向する主
面に予め被着させておいた封止用ガラス部材6を溶融一
体化させることによって接合させ、これによって最終製
品としての半導体装置が完或する。
Thus, according to this semiconductor element storage package, the semiconductor element 4 is attached and fixed to the bottom of the recess of the insulating substrate 1, and each electrode of the semiconductor element 4 is connected to the external lead terminal 5 by the bonding wire 7. , the insulating base 1 and the lid 2 are joined together by melting and integrating the sealing glass member 6 that has been previously attached to the opposing main surfaces of the insulating base 1 and the lid 2, and thereby The semiconductor device as a final product is completed.

(発明の効果) 本発明の半導体素子収納用パソケージによれば、半導体
素子を収容するための絶縁容器を構或する絶縁基体及び
蓋体を窒化アルミニウム質焼結体、ムライト質焼結体、
ジルコン質焼結体の少なくとも1種で、外部リード端子
をニソケル41.5乃至42.5WtX 、鉄57.5
乃至58.5WtX (7)合金から成る芯体の外表面
を銅から成る被覆層で被覆すると共に、被覆層の断面積
を芯体の断面積の20乃至40χとした導電率が27.
2!(IACS) 、熱膨張係数が約49XIO−’/
 ’Cの金属体で形成したことから外部リード端子の信
号伝搬速度を極めて速いものとなすことができ、絶縁容
器内に収容した半導体素子を高速駆動させたとしても半
導体素子と外部電気回路との間における信号の出し入れ
を常に安定、且つ確実となすことが可能となる。
(Effects of the Invention) According to the pathocage for storing semiconductor elements of the present invention, the insulating base and the lid which constitute the insulating container for accommodating the semiconductor elements are made of aluminum nitride sintered body, mullite sintered body,
At least one type of zircon sintered body, the external lead terminal is Nisokel 41.5 to 42.5WtX, iron 57.5
58.5WtX (7) The outer surface of the core made of alloy is covered with a coating layer made of copper, and the conductivity is 27.
2! (IACS), the coefficient of thermal expansion is approximately 49XIO-'/
Since the external lead terminal is made of a metal body of C, the signal propagation speed of the external lead terminal can be made extremely high. It becomes possible to always stably and reliably transfer signals between the two.

また外部リード端子の線幅が細くなったとしても外部リ
ード端子の電気抵抗を低く抑えることができ、その結果
、外部リード端子における信号の減衰を極小として内部
に収容する半導体素子に外部電気回路から供給される電
気信号を正確に入力することが可能となる。
In addition, even if the line width of the external lead terminal becomes thinner, the electrical resistance of the external lead terminal can be kept low, and as a result, the signal attenuation at the external lead terminal is minimized, and the external electrical circuit is connected to the semiconductor element housed inside. It becomes possible to accurately input the supplied electrical signal.

更に外部リード端子はその熱膨張係数が絶縁基体、蓋体
及び封止用ガラス部材の各々の熱膨張係数と近似し、絶
縁基体と蓋体との間に外部リード端子を挟み、各々を封
止用ガラス部材で取着接合したとしても絶縁基体及び蓋
体と封止用ガラス部材との間、外部リード端子と封止用
ガラス部材との間のいずれにも熱膨張係数の相違に起因
する熱応力は発生せず、すべてを強固に取着接合するこ
とも可能となる。
Furthermore, the coefficient of thermal expansion of the external lead terminal is close to that of each of the insulating base, the lid, and the sealing glass member, and the external lead terminal is sandwiched between the insulating base and the lid, and each is sealed. Even if they are attached and bonded using a glass material for sealing, there will be heat due to differences in thermal expansion coefficients between the insulating base and lid and the glass sealing member, and between the external lead terminal and the glass sealing member. No stress is generated, and everything can be firmly attached and joined.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第2図は第1図に示すパッケージの絶
縁基体上面より見た平面図である。
FIG. 1 is a sectional view showing an embodiment of the semiconductor element storage package of the present invention, and FIG. 2 is a plan view of the package shown in FIG. 1, viewed from the top surface of the insulating base.

Claims (1)

【特許請求の範囲】[Claims]  絶縁基体と蓋体とから成り、内部に半導体素子を収容
するための空所を有する絶縁容器と、該容器内に収容さ
れる半導体素子を外部電気回路に接続するための外部リ
ード端子とから成る半導体素子収納用パッケージにおい
て、前記絶縁基体及び蓋体を窒化アルミニウム質焼結体
、ムライト質焼結体、ジルコン質焼結体の少なくとも1
種で、外部リード端子をニッケル41.5乃至42.5
Wt%、鉄57.5乃至58.5Wt%の合金から成る
芯体の外表面を銅から成る被覆層で被覆すると共に、被
覆層の断面積を芯体の断面積の20乃至40%とした金
属体で形成したことを特徴とする半導体素子収納用パッ
ケージ。
An insulating container consisting of an insulating base and a lid and having a cavity for accommodating a semiconductor element therein, and an external lead terminal for connecting the semiconductor element housed in the container to an external electric circuit. In the semiconductor element storage package, the insulating base and the lid are made of at least one of an aluminum nitride sintered body, a mullite sintered body, and a zircon sintered body.
Nickel 41.5 to 42.5 for external lead terminals.
The outer surface of the core made of an alloy of 57.5 to 58.5 Wt% iron was coated with a coating layer made of copper, and the cross-sectional area of the coating layer was 20 to 40% of the cross-sectional area of the core. A package for storing semiconductor elements characterized by being formed of a metal body.
JP1308594A 1989-08-25 1989-11-27 Package for storing semiconductor elements Expired - Lifetime JP2736451B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1308594A JP2736451B2 (en) 1989-11-27 1989-11-27 Package for storing semiconductor elements
US07/574,472 US5168126A (en) 1989-08-25 1990-08-27 Container package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1308594A JP2736451B2 (en) 1989-11-27 1989-11-27 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH03167850A true JPH03167850A (en) 1991-07-19
JP2736451B2 JP2736451B2 (en) 1998-04-02

Family

ID=17982922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1308594A Expired - Lifetime JP2736451B2 (en) 1989-08-25 1989-11-27 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2736451B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463248A (en) * 1993-05-18 1995-10-31 Kabushiki Kaisha Toshiba Semiconductor package using an aluminum nitride substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5188459A (en) * 1975-01-31 1976-08-03 FUKUGORIIDOSEN
JPS6243155A (en) * 1985-08-21 1987-02-25 Hitachi Ltd Integrated circuit package
JPS63169056A (en) * 1987-01-05 1988-07-13 Kobe Steel Ltd Lead frame material
JPS63314855A (en) * 1987-06-17 1988-12-22 Shinko Electric Ind Co Ltd Ceramic package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5188459A (en) * 1975-01-31 1976-08-03 FUKUGORIIDOSEN
JPS6243155A (en) * 1985-08-21 1987-02-25 Hitachi Ltd Integrated circuit package
JPS63169056A (en) * 1987-01-05 1988-07-13 Kobe Steel Ltd Lead frame material
JPS63314855A (en) * 1987-06-17 1988-12-22 Shinko Electric Ind Co Ltd Ceramic package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463248A (en) * 1993-05-18 1995-10-31 Kabushiki Kaisha Toshiba Semiconductor package using an aluminum nitride substrate

Also Published As

Publication number Publication date
JP2736451B2 (en) 1998-04-02

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