JP6337775B2 - 配線基板及び配線基板の製造方法 - Google Patents
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
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- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
- H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
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- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09809—Coaxial layout
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
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- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
以下に、配線基板1の構成について説明する(図1参照)。
以下に、配線基板の変形例について説明する(図2参照)。
以下に、同軸構造9の寸法について説明する(図3参照)。
次に、上記した配線基板1の製造方法について説明する(図4乃至図12参照)。
以上に記載した通り、配線基板1、1Aにあっては、構造形成部8に同軸構造9が設けられ、同軸構造9の内側配線部10が絶縁層2、2、・・・と配線層3、3、・・・の積層方向に延びて部品用接続パッド4と回路用接続パッド5に電気的に接続されている。
本技術は、以下のような構成にすることもできる。
Claims (10)
- 交互に積層された複数の絶縁層と複数の配線層とを有すると共に前記配線層同士がそれぞれビアによって接続されたコアレス基板であり、
前記絶縁層と前記配線層の積層方向における一方の面に電子部品が接続される部品用接続パッドが設けられ、
前記積層方向における他方の面に回路基板に接続される回路用接続パッドが設けられ、
一部に同軸構造を有する構造形成部が設けられ、
前記同軸構造は前記積層方向に延びる内側配線部と前記内側配線部の外周面側に絶縁樹脂を介して位置される外側配線部とを有し、
前記絶縁樹脂が前記複数の絶縁層の一つと一体に形成され、
前記内側配線部が前記部品用接続パッドと前記回路用接続パッドに電気的に接続された
配線基板。 - 前記内側配線部の前記積層方向における両端がそれぞれ前記部品用接続パッドと前記回路用接続パッドに接合された
請求項1に記載の配線基板。 - 前記内側配線部の前記積層方向における一端が前記部品用接続パッド又は前記回路用接続パッドの一方に接合され、
前記内側配線部の前記積層方向における他端が前記配線層と前記ビアを介して前記部品用接続パッド又は前記回路用接続パッドの他方に接続された
請求項1に記載の配線基板。 - 前記内側配線部の外径が30μm以上80μm以下にされ、
前記外側配線部の内径が130μm以上350μm以下にされた
請求項1に記載の配線基板。 - 支持体上に複数の絶縁層と複数の配線層とを積層する積層工程と、
一部に同軸構造を設けるための構造形成用スルーホールを形成する第1のスルーホール形成工程と、
前記構造形成用スルーホールの内部に前記同軸構造の一部を構成する外側配線部を形成する外側配線部形成工程と、
前記積層工程で形成された前記複数の絶縁層と複数の配線層の積層の上面に新たな絶縁層となる樹脂を積層するとともに、前記構造形成用スルーホールに前記樹脂を充填し、前記新たな絶縁層と前記外側配線部の内周側の絶縁樹脂を一体に形成する樹脂充填工程と、
前記構造形成用スルーホールに充填された前記樹脂に、電子部品が接続される部品用接続パッドと回路基板に接続される回路用接続パッドに電気的に接続され前記同軸構造の一部を構成する内側配線部を形成するための内側配線用スルーホールを形成する第2のスルーホール形成工程と、
前記内側配線用スルーホールに導電材を充填して前記内側配線部を形成する内側配線部形成工程と、
前記支持体を剥離してコアレス基板とする剥離工程とを備えた
配線基板の製造方法。 - 前記構造形成用スルーホールをレーザー光の照射によって形成した
請求項5に記載の配線基板の製造方法。 - 前記内側配線用スルーホールをレーザー光の照射によって形成した
請求項5に記載の配線基板の製造方法。 - 前記絶縁層と前記配線層の積層方向における一方の面に電子部品が接続される部品用接続パッドが設けられ、
前記積層方向における他方の面に回路基板に接続される回路用接続パッドが設けられ、
前記内側配線部の前記積層方向における両端がそれぞれ前記部品用接続パッドと前記回路用接続パッドに接合された
請求項5に記載の配線基板の製造方法。 - 前記絶縁層と前記配線層の積層方向における一方の面に電子部品が接続される部品用接続パッドが設けられ、
前記積層方向における他方の面に回路基板に接続される回路用接続パッドが設けられ、
前記内側配線部の前記積層方向における一端が前記部品用接続パッド又は前記回路用接続パッドの一方に接合され、
前記内側配線部の前記積層方向における他端が前記配線層とビアを介して前記部品用接続パッド又は前記回路用接続パッドの他方に接続された
請求項5に記載の配線基板の製造方法。 - 前記内側配線部の外径が30μm以上80μm以下にされ、
前記外側配線部の内径が130μm以上350μm以下にされた
請求項5に記載の配線基板の製造方法。
Applications Claiming Priority (3)
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JP2012191377 | 2012-08-31 | ||
JP2012191377 | 2012-08-31 | ||
PCT/JP2013/072020 WO2014034443A1 (ja) | 2012-08-31 | 2013-08-16 | 配線基板及び配線基板の製造方法 |
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JPWO2014034443A1 JPWO2014034443A1 (ja) | 2016-08-08 |
JP6337775B2 true JP6337775B2 (ja) | 2018-06-06 |
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US (1) | US10187971B2 (ja) |
JP (1) | JP6337775B2 (ja) |
KR (1) | KR102134933B1 (ja) |
CN (1) | CN104604345A (ja) |
WO (1) | WO2014034443A1 (ja) |
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JP6332680B2 (ja) * | 2014-06-13 | 2018-05-30 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
WO2016099980A1 (en) * | 2014-12-17 | 2016-06-23 | Applied Materials, Inc. | Triaxial cable sensor and wearable devices |
CN106163083B (zh) * | 2016-06-30 | 2017-08-15 | 广州番禺运升电路版有限公司 | 一种印刷电路板及其制造方法 |
KR102518426B1 (ko) | 2016-09-09 | 2023-04-05 | 삼성디스플레이 주식회사 | 표시 장치 |
JP7084245B2 (ja) * | 2018-08-02 | 2022-06-14 | 日本ルメンタム株式会社 | プリント回路基板、光モジュール、及び光伝送装置 |
CN112310041B (zh) * | 2019-07-29 | 2023-04-18 | 群创光电股份有限公司 | 电子装置及其制造方法 |
JP7362380B2 (ja) * | 2019-09-12 | 2023-10-17 | キヤノン株式会社 | 配線基板及び半導体装置 |
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- 2013-08-16 JP JP2014532922A patent/JP6337775B2/ja active Active
- 2013-08-16 US US14/422,992 patent/US10187971B2/en active Active
- 2013-08-16 WO PCT/JP2013/072020 patent/WO2014034443A1/ja active Application Filing
- 2013-08-16 CN CN201380043943.6A patent/CN104604345A/zh active Pending
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JPWO2014034443A1 (ja) | 2016-08-08 |
CN104604345A (zh) | 2015-05-06 |
WO2014034443A1 (ja) | 2014-03-06 |
US10187971B2 (en) | 2019-01-22 |
KR102134933B1 (ko) | 2020-07-16 |
KR20150048105A (ko) | 2015-05-06 |
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