JP2016207958A - 配線基板及び配線基板の製造方法 - Google Patents
配線基板及び配線基板の製造方法 Download PDFInfo
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- JP2016207958A JP2016207958A JP2015091513A JP2015091513A JP2016207958A JP 2016207958 A JP2016207958 A JP 2016207958A JP 2015091513 A JP2015091513 A JP 2015091513A JP 2015091513 A JP2015091513 A JP 2015091513A JP 2016207958 A JP2016207958 A JP 2016207958A
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- layer
- wiring
- insulating layer
- wiring layer
- insulating
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
Description
以下、図1〜図9に従って第1実施形態を説明する。
図1(a)に示すように、配線基板10は、配線層11と、絶縁層21と、配線層12と、絶縁層22と、配線層13と、絶縁層23と、絶縁層24と、配線層14とが順次積層された構造を有している。このように、本実施形態の配線基板10は、一般的なビルドアップ法を用いて作製される配線基板(支持基材としてのコア基板の両面又は片面に所要数のビルドアップ層を順次形成して積層したもの)とは異なり、支持基材を含まない、所謂「コアレス基板」の形態を有している。
配線層14は、絶縁層24の上面24Aに積層されている。配線層14は、配線基板10の最外層(ここでは、最上層)の配線層である。一部の配線層14(第3配線層)は、貫通孔VH3,VH4に充填されたビア配線を介して配線層13と電気的に接続されている。すなわち、一部の配線層14は、絶縁層23,24を厚さ方向に貫通するビア配線を介して配線層13と電気的に接続されている。残りの配線層14(第6配線層)は、貫通孔VH5に充填されたビア配線を介して電極端子32と電気的に接続されている。配線層14は、例えば、貫通孔VH3,VH4に充填されたビア配線、又は貫通孔VH5に充填されたビア配線と一体に形成されている。配線層14は、絶縁層24の上面24A上で平面方向(厚さ方向と断面視で直交する方向)に引き回されていてもよい。さらに、このような配線層14により、配線層13に接続される配線層14と、電極端子32に接続される配線層14とが相互に電気的に接続されていてもよい。配線層14の厚さは、例えば、10〜20μm程度とすることができる。
半導体装置50は、配線基板10と、1つ又は複数の半導体チップ51と、アンダーフィル樹脂55とを有している。半導体チップ51は、配線基板10にフリップチップ実装されている。すなわち、半導体チップ51の回路形成面(ここでは、下面)に配設された接続端子52を、接合部材53を介して配線基板10のパッドP1に接合することにより、半導体チップ51は、接続端子52及び接合部材53を介してパッドP1(配線層11)と電気的に接続されている。
図4(a)に示すように、支持体60の上面にキャリア付金属箔61が貼着された構造体を準備する。支持体60は、例えば、ガラス、アラミド、LCP繊維の織布や不織布などの補強材に、エポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含浸させたプリプレグである。キャリア付金属箔61は、キャリア層62と、キャリア層62の上面に剥離層(図示略)を介して積層された極薄の金属箔63とを有している。キャリア層62は、金属箔63の取り扱いを容易にするための支持材として設けられている。キャリア層62は、例えば、厚さが15〜70μm程度の銅箔である。金属箔63は、例えば、厚さが0.5〜5μm程度の銅箔である。
次いで、金属層70をエッチングにより除去する。例えば、絶縁層22,23をエッチングマスクとして、金属層70を等方性エッチングにより除去する。この等方性エッチングにより、エッチングが金属層70の面内方向に進行するサイドエッチ現象によって、絶縁層22に被覆された金属層70も除去される。これにより、図7(c)に示すように、開口部22Xの内壁面を構成する絶縁層22の下端部に凹部22Yが形成される。このとき、本工程のエッチング処理の処理条件(処理時間等)によって、図7(d)に示すように、絶縁層22に被覆されていた金属層70(図7(b)参照)が完全に除去される場合と、図7(e)に示すように、絶縁層22に被覆されていた金属層70の一部が残る場合とがある。すなわち、絶縁層22に被覆されていた金属層70の一部が除去されて凹部22Yが形成されていれば、金属層70の一部が除去されずに残ってもよい。なお、金属層70の一部が残る場合には、その金属層70の側面と、絶縁層22の下面22Bと、絶縁層21の上面21Aとによって囲まれた空間が凹部22Yとなる。
次に、半導体装置50の製造方法について説明する。
図9(c)に示す工程では、柱状の接続端子52を有する半導体チップ51を準備する。接続端子52は、公知の製造方法により製造することが可能であるため、図示は省略して詳細な説明を割愛するが、例えば以下のような方法で製造される。
(1)絶縁層21上に積層された2層の絶縁層22,23をキャビティ形成用の絶縁層とし、それら絶縁層22,23の中に配線層13を内蔵し、絶縁層23の上面23Aには配線層を形成せずに、その上面23Aにキャビティ充填用の絶縁層24を形成した。そして、絶縁層24の上面24Aに、絶縁層22,23を厚さ方向に貫通するビア配線を介して配線層13と電気的に接続される配線層14を形成した。これにより、絶縁層21,22,23,24の厚さのばらつきを抑制しつつも、配線基板10全体の薄型化に寄与することができる。
以下、図10〜図12に従って第2実施形態を説明する。この実施形態の配線基板10Aは、チップ搭載面に配線層15が積層された点が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。なお、先の図1〜図9に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
まず、図4(a)〜図8(c)に示した工程と同様の工程を実施することにより、図11(a)に示した構造体を製造する。
以上説明した実施形態によれば、第1実施形態の(1)〜(8)の効果に加えて以下の効果を奏することができる。
以下、図13〜図16に従って第3実施形態を説明する。この実施形態の配線基板10Bは、積層された配線層の層数が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。なお、先の図1〜図12に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
まず、図4(a)及び図4(b)に示した工程と同様の工程を実施することにより、図14(a)に示す構造体を製造する。続いて、図14(b)に示す工程では、図4(c)及び図4(d)に示した工程と同様に、金属箔63の上面63Aに、配線層11の表面全面を被覆する絶縁層21と、その絶縁層21の上面21A全面を被覆する金属箔66とを順に積層する。次いで、金属箔66上に、所定パターンのレジスト層80を形成する。レジスト層80は、チップキャパシタ30(図13参照)の搭載領域に形成され、開口部22X,23X(図13参照)よりも一回り大きい平面形状に形成される。レジスト層80の材料としては、例えば、次工程のエッチング処理に対して耐エッチング性がある材料を用いることができる。例えば、レジスト層80の材料としては、感光性のドライフィルムレジスト又は液状のフォトレジスト(例えば、ノボラック系樹脂やアクリル系樹脂等のドライフィルムレジストや液状レジスト)等を用いることができる。
以上説明した本実施形態によれば、上記第1実施形態と同様の効果を奏することができる。
以下、図17に従って第4実施形態を説明する。この実施形態の配線基板10Cは、チップ搭載面に配線層15が積層された点が上記第3実施形態と異なっている。以下、第3実施形態との相違点を中心に説明する。なお、先の図1〜図16に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
まず、図14(a)〜図15(d)に示した工程と同様の工程を実施することにより、図17(a)に示した構造体を製造する。
(他の実施形態)
なお、上記各実施形態は、これを適宜変更した以下の態様にて実施することもできる。
例えば図18に示すように、上記第2実施形態の配線基板10A(図10(a)参照)における貫通孔VH5及びその貫通孔VH5を充填するビア配線を省略してもよい。この場合の配線基板10Dでは、外部接続端子面に設けられた配線層14とチップキャパシタ30とを接続するビア配線は形成されずに、チップ搭載面に設けられた配線層15とチップキャパシタ30とを接続するビア配線のみが形成される。すなわち、配線基板10Dでは、チップキャパシタ30の電極端子32の上面と下面のうち下面側のみにビア配線が形成される。なお、上記第4実施形態の配線基板10Cについても同様に変更することができる。
例えば図19に示すように、複数(ここでは、2つ)のチップキャパシタ30を配線基板10E内に内蔵するようにしてもよい。この配線基板10Eは、図1(a)に示した配線基板10に内蔵するチップキャパシタ30を2つに変更した配線基板である。この配線基板10Eの絶縁層22,23には、内蔵されるチップキャパシタ30と同じ数(ここでは、2つ)の開口部22X,23Xが形成されている。
・図19及び図20に示した変形例では、内蔵されるチップキャパシタ30と同じ数の開口部22X,23Xを形成したが、1つの開口部22X,23X(1つのキャビティ)に複数のチップキャパシタ30を配置するようにしてもよい。
・上記各実施形態及び上記各変形例では、配線基板10,10A〜10Eに、2つの電極端子32を有するチップキャパシタ30を内蔵するようにした。これに限らず、例えば、3つ以上の電極端子32を有するキャパシタなどの電子部品を配線基板10,10A〜10Eに内蔵するようにしてもよい。
・上記各実施形態の配線基板10,10A〜10Eでは、キャビティ形成用の絶縁層を2層の絶縁層22,23で構成するようにした。これに限らず、キャビティ形成用の絶縁層を3層以上の絶縁層で構成するようにしてもよい。
・上記各実施形態では、単数個取り(一個取り)の製造方法に具体化したが、多数個取りの製造方法に具体化してもよい。
半導体パッケージ101は、配線基板110と、配線基板110に実装された一つ又は複数の半導体チップ120と、半導体チップ120と配線基板110とを電気的に接続するボンディングワイヤ121と、半導体チップ120等を封止する封止樹脂123とを有している。
半導体チップ120は、以上説明した配線基板110にワイヤボンディング実装されている。詳述すると、半導体チップ120は、コア基板111の上面に接着層122により接着されている。そして、半導体チップ120の電極(図示略)は、ボンディングワイヤ121を介してパッドP5と電気的に接続されている。なお、半導体チップ120の実装の形態は特に限定されず、例えば半導体チップ120を配線基板110にフリップチップ実装するようにしてもよい。
配線基板10Eの接続パッドP2上には、はんだボール104が接合されている。はんだボール104は、配線基板10Eと半導体パッケージ101との間に介在して設けられ、その一端が接続パッドP2に接合され、他端が接続パッドP4に接合されている。はんだボール104としては、例えば、導電性コアボール(銅コアボールなど)や樹脂コアボールの周囲をはんだで覆った構造を有するはんだボールを用いることができる。なお、はんだボール104としては、導電性コアボールや樹脂コアボールを省略したはんだボールを用いることもできる。
11 配線層(第1配線層)
12 配線層(第4配線層)
13 配線層(第2配線層)
14 配線層(第3配線層、第6配線層)
15 配線層(第5配線層、第7配線層)
21 絶縁層(第1絶縁層)
22 絶縁層(第2絶縁層)
22X,23X 開口部
22Y 凹部
23 絶縁層(第3絶縁層)
24 絶縁層(第4絶縁層)
35 接着層
60 支持体
61 キャリア付金属箔
62 キャリア層
63 金属箔
70 金属層
VH5 貫通孔(第1貫通孔)
VH6 貫通孔(第2貫通孔)
Claims (10)
- 第1配線層と、
前記第1配線層上に積層された第1絶縁層と、
前記第1絶縁層の上面に積層された第2絶縁層と、前記第2絶縁層の上面に積層された第3絶縁層とを含む複数層の絶縁層と、
前記複数層の絶縁層を貫通して前記第1絶縁層の上面の一部を露出する開口部と、
前記開口部から露出する前記第1絶縁層の上面に搭載された電子部品と、
前記開口部を充填し、前記複数層の絶縁層の中の最上層の絶縁層の上面全面及び前記電子部品を被覆する第4絶縁層と、
前記第1配線層と電気的に接続され、前記複数層の絶縁層に内蔵されるとともに前記最上層の絶縁層により被覆された第2配線層と、
前記最上層の絶縁層及び前記第4絶縁層を貫通するビア配線を介して前記第2配線層と電気的に接続され、前記第4絶縁層の上面に積層された第3配線層と、を有することを特徴とする配線基板。 - 前記複数層の絶縁層は、前記第2絶縁層及び前記第3絶縁層からなり、
前記開口部は、前記第2絶縁層及び前記第3絶縁層を厚さ方向に貫通して形成され、
前記第1絶縁層を貫通するビア配線を介して前記第1配線層と電気的に接続され、前記第1絶縁層の上面に積層された第4配線層と、
前記第2絶縁層を貫通するビア配線を介して前記第4配線層と電気的に接続され、前記第2絶縁層の上面に積層された前記第2配線層と、を有し、
前記第3配線層は、前記第3絶縁層及び前記第4絶縁層を貫通するビア配線を介して前記第2配線層と電気的に接続されていることを特徴とする請求項1に記載の配線基板。 - 前記複数層の絶縁層は、前記第2絶縁層及び前記第3絶縁層からなり、
前記開口部は、前記第2絶縁層及び前記第3絶縁層を厚さ方向に貫通して形成され、
前記第1絶縁層及び前記第2絶縁層を貫通するビア配線を介して前記第1配線層と電気的に接続され、前記第2絶縁層の上面に積層された前記第2配線層を有し、
前記第3配線層は、前記第3絶縁層及び前記第4絶縁層を貫通するビア配線を介して前記第2配線層と電気的に接続されていることを特徴とする請求項1に記載の配線基板。 - 前記第1配線層は、最下層の配線層であり、
前記第1絶縁層は、前記第1配線層の上面及び側面を被覆し、前記第1配線層の下面を露出するように形成されていることを特徴とする請求項1〜3のいずれか一項に記載の配線基板。 - 前記第1配線層の下面に直に積層され、前記第1配線層と直接接続された第5配線層を有することを特徴とする請求項1〜4のいずれか一項に記載の配線基板。
- 前記第4絶縁層を貫通する第1貫通孔に充填されたビア配線を介して前記電子部品と電気的に接続され、前記第4絶縁層の上面に積層された第6配線層と、
前記第1絶縁層を貫通する第2貫通孔に充填されたビア配線を介して前記電子部品と電気的に接続され、前記第1絶縁層の下面及び前記第1配線層の下面の少なくとも一方の面に積層された第7配線層と、を有し、
前記第1貫通孔は、前記電子部品側の開口部に対して前記第4絶縁層の上面側の開口部が拡開されたテーパ状に形成され、
前記第2貫通孔は、前記電子部品側の開口部に対して前記第1絶縁層の下面側の開口部が拡開されたテーパ状に形成されていることを特徴とする請求項1〜5のいずれか一項に記載の配線基板。 - 第1配線層を形成する工程と、
前記第1配線層上に第1絶縁層を積層する工程と、
前記第1絶縁層の上面に第2絶縁層を形成する工程と、
前記第2絶縁層の上面に、前記第1配線層と電気的に接続される第2配線層を形成する工程と、
前記第2絶縁層の上面に、前記第2配線層を被覆する第3絶縁層を形成する工程と、
前記第2絶縁層及び前記第3絶縁層を厚さ方向に貫通する開口部を形成する工程と、
前記開口部から露出する前記第1絶縁層の上面に電子部品を搭載する工程と、
前記開口部を充填し、前記第3絶縁層の上面全面及び前記電子部品を被覆する第4絶縁層を形成する工程と、
前記第4絶縁層の上面に、前記第4絶縁層及び前記第3絶縁層を貫通するビア配線を介して前記第2配線層と電気的に接続される第3配線層を形成する工程と、
を有することを特徴とする配線基板の製造方法。 - 前記第1絶縁層を形成する工程の後に、前記第1絶縁層の上面に、前記第1絶縁層を厚さ方向に貫通するビア配線を介して前記第1配線層と電気的に接続される第4配線層を形成する工程を有し、
前記第2絶縁層を形成する工程では、前記第4配線層を被覆する前記第2絶縁層を形成し、
前記第2配線層を形成する工程では、前記第2絶縁層を貫通するビア配線を介して前記第4配線層と電気的に接続される前記第2配線層を形成することを特徴とする請求項7に記載の配線基板の製造方法。 - 前記第2配線層を形成する工程では、前記第1絶縁層及び前記第2絶縁層を貫通するビア配線を介して前記第1配線層と電気的に接続される前記第2配線層を形成することを特徴とする請求項7に記載の配線基板の製造方法。
- 前記第1配線層を形成する工程では、支持基板の上面に前記第1配線層を形成し、
前記第1絶縁層を形成する工程では、前記支持基板の上面に、前記第1配線層の上面及び側面を被覆する前記第1絶縁層を形成し、
前記第4絶縁層を形成する工程の後に、
前記支持基板を除去する工程と、
前記第4絶縁層を貫通して前記電子部品の一部を露出する第1貫通孔を形成するとともに、前記第1絶縁層を貫通して前記電子部品の一部を露出する第2貫通孔を形成する工程と、
前記第4絶縁層の上面に、前記第1貫通孔を充填するビア配線を介して前記電子部品と電気的に接続される第6配線層を形成するとともに、前記第1絶縁層の下面及び前記第1配線層の下面の少なくとも一方の面に、前記第2貫通孔を充填するビア配線を介して前記電子部品と電気的に接続される第7配線層を形成する工程と、を有することを特徴とする請求項7〜9のいずれか一項に記載の配線基板の製造方法。
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US10779406B2 (en) | 2018-02-21 | 2020-09-15 | Shinko Electric Industries Co., Ltd. | Wiring substrate |
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US10879188B2 (en) | 2018-04-23 | 2020-12-29 | Shinko Electric Industries Co., Ltd. | Wiring substrate |
CN110875258A (zh) * | 2018-08-30 | 2020-03-10 | 京瓷株式会社 | 电子元件安装用基板、电子装置以及电子模块 |
JP2020035898A (ja) * | 2018-08-30 | 2020-03-05 | 京セラ株式会社 | 電子素子実装用基板、電子装置、および電子モジュール |
JP7210191B2 (ja) | 2018-08-30 | 2023-01-23 | 京セラ株式会社 | 電子素子実装用基板、電子装置、および電子モジュール |
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JP7265877B2 (ja) | 2019-02-06 | 2023-04-27 | 新光電気工業株式会社 | 配線基板 |
JP2021022674A (ja) * | 2019-07-29 | 2021-02-18 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
US11019725B2 (en) | 2019-07-29 | 2021-05-25 | Shinko Electric Industries Co., Ltd. | Wiring substrate |
JP7247046B2 (ja) | 2019-07-29 | 2023-03-28 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
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