JP4580867B2 - 半導体装置の製造方法、半導体ウエハおよび半導体装置 - Google Patents
半導体装置の製造方法、半導体ウエハおよび半導体装置 Download PDFInfo
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- JP4580867B2 JP4580867B2 JP2005505818A JP2005505818A JP4580867B2 JP 4580867 B2 JP4580867 B2 JP 4580867B2 JP 2005505818 A JP2005505818 A JP 2005505818A JP 2005505818 A JP2005505818 A JP 2005505818A JP 4580867 B2 JP4580867 B2 JP 4580867B2
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Description
きず、表面を平坦化するためには配線間隔を高々2倍までのような一定の範囲内にすることが必要であると教示する。チップ領域のみでなく、スクライブ領域にもダミー配線を配置することにより、ウエハ全面で平坦な表面を有する絶縁層を形成することが可能になる。
と同一材料のパターンである。配線がデュアルダマシン配線である場合、ダミー配線は同一構造を有する必要はなく、シングルダマシン構造を有してもよい。
(a)半導体ウエハの平面構成におけるチップ領域とダイシング領域のそれぞれの上方に、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に形成した多層配線構造を配置する工程と、
(b)前記多層配線構造を覆って、パッシベーション層を形成する工程と、
(c)前記ダイシング領域と前記チップ領域との間に、溝を上方から、少なくとも前記パッシベーション層を貫通して形成する工程と、
を含み、
前記半導体ウエハの平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される
半導体装置の製造方法
が提供される。
半導体基板と、
前記半導体基板の平面構成におけるチップ領域とダイシング領域のそれぞれの上方に形成され、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に積層した多層配線構造と、
前記多層配線構造を覆って形成された、パッシベーション層と、
前記ダイシング領域と前記チップ領域の間において、上方から、少なくとも前記パッシベーション層を貫通して形成された溝と、
を含み、
前記半導体基板の平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される
半導体ウエハ
が提供される。
半導体基板と、
前記半導体基板のチップ領域とスクライブ領域のそれぞれの上方に形成された、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に積層した多層配線構造と、
前記多層配線構造を覆って形成された、パッシベーション層と、
前記スクライブ領域において、上方から、少なくとも前記パッシベーション層を貫通して形成された溝と、
を含み、
前記半導体基板の平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される
半導体装置
が提供される。
よって各チップC1,C2が分離される。カバー層は応力を内臓するので、カバー層が存在する状態でダイシングを行うと、ダイシングの衝撃により、絶縁層の界面で剥離が生じやすい。例えば、図に示すように、ダイシング時の衝撃により、チップC1のカバー層の最上絶縁層ISがその下の層間絶縁膜IL4との界面で剥離し、剥離がチップ内部に向う。カバー層の界面のみでなく、下方の層間絶縁膜の界面でも剥離は生じる。剥離はチップ周辺に留まらず、回路領域内部まで侵入し易い。剥離がチップ内部に達すると、チップは不良となり、歩留まりを低下させる。多層配線の層間絶縁膜に低誘電率(low−k)材料を用いると、その界面で剥離が生じ易くなる。
見出された。カバー層PS,ISは、パッドP上で除去されてパッドを露出すると共に、チップ領域Cを取り囲むスクライブ領域SCの外側部でループ状に除去されて溝Gを形成している。
力の集中により角部から回路領域内まで、剥離が生じ得る。溝を角部を落とした平面形状とすることにより、応力の集中を避け、剥離をさらに有効にブロックすることができる。
その上に層間絶縁膜IL2を成膜する。ダマシン用凹部を形成し、第2配線W2,第2ダミー配線DW2を含む第2配線層を埋め込む。さらに第3エッチストッパ層ES3、第3層間絶縁膜IL3を成膜し、ダマシン用凹部を形成して第3配線W3、第3ダミー配線DW3を含む第3配線層を埋め込む。
も良い。
れる。
される領域にダミー配線を配置しておくと、ダミー配線が飛び散ることになる。エッチングされ得る深さまで、溝形成領域にはダミー配線を配置しないことにより、ダミー配線の飛び散りは生じない。
パッシベーション層PSを成膜した後に行われるエッチングは、パッド開口用のエッチ
ングに限らない。パッド開口とは独立のエッチング工程がある場合、その別のエッチング工程を用いて溝を形成することもできる。溝形成用のエッチング工程を設けてもよい。
絶縁膜IL3にまで達している。しかしながら、スクライブ領域において第3配線層のダミー配線は配置されていないため、溝Gがダミー配線を飛び散らせることはない。チップ領域においてはダミー配線が配置されているため、必要な平坦性は確保できる。スクライブ領域において第3配線のダミー配線を省略したことによる平坦性の劣化は、最小限に留めることができる。なお、チップ領域においてもさほどの平坦性が必要ない場合は、第3配線層のダミー配線をチップ領域においても省略してもよい。
形成され、銅配線による第1配線層W1が埋め込まれる。
る。なお、第1配線層から第4配線層を収納する層間絶縁膜はSiLK等の有機絶縁層で形成される。
トッパ層ES8、層間絶縁膜IL8、配線層W8による第8配線層を形成する。第5配線層から第8配線層までを収容する層間絶縁膜IL5〜IL8は、SiOCで形成される。
である。中央の黒い部分dcがダイシングを行なってウエハがなくなった領域である。ダイシング領域の上方に白く見える領域を介して細い溝Gが見える。図中左側領域には、溝に対応する位置から下方の部分Zが一部消失している。ダイシングされた領域から剥離が生じ、溝まで達し、上方にクラックが走り、表面層が消失したと考えられる。溝の上方に見える黒い筋状の部分は耐湿シールリングSRである。さらに上方の大きな矩形領域はパッドPである。
を除去する半導体装置の製造方法に有効である。
Claims (24)
- (a)半導体ウエハの平面構成におけるチップ領域とダイシング領域のそれぞれの上方に、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に形成した多層配線構造を配置する工程と、
(b)前記多層配線構造を覆って、パッシベーション層を形成する工程と、
(c)前記ダイシング領域と前記チップ領域との間に、溝を上方から、少なくとも前記パッシベーション層を貫通して形成する工程と、
を含み、
前記半導体ウエハの平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される半導体装置の製造方法。 - 前記配線層は銅配線層である請求項1記載の半導体装置の製造方法。
- さらに、
(d)前記工程(c)の後、前記ダイシング領域において、前記半導体ウエハをダイシングする工程、
を含む請求項1記載の半導体装置の製造方法。 - 前記最上配線層はアルミニウム配線層である請求項1記載の半導体装置の製造方法。
- 前記多層配線構造の最上配線層以外の配線層はダマシン構造の銅配線層である請求項4記載の半導体装置の製造方法。
- 前記銅配線層の上の層間絶縁膜は、銅の拡散を防止できる銅拡散防止層と、その上の絶縁層を含む請求項5記載の半導体装置の製造方法。
- 前記多層配線構造の最上配線層は、パッドを含み、前記工程(c)は前記パッシベーション層を選択的に除去して前記パッドを露出させると共に、前記溝の領域で前記パッシベーション層とその下の層間絶縁膜とを選択的に除去するエッチング工程を含む請求項1記載の半導体装置の製造方法。
- 前記溝は、チップ領域の各角部の外側で角を落とした概略矩形形状を有する請求項1記載の半導体装置の製造方法。
- 前記溝の幅は、0.5μm〜10μmの範囲である請求項1記載の半導体装置の製造方法。
- 半導体基板と、
前記半導体基板の平面構成におけるチップ領域とダイシング領域のそれぞれの上方に形成され、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に積層した多層配線構造と、
前記多層配線構造を覆って形成された、パッシベーション層と、
前記ダイシング領域と前記チップ領域の間において、上方から、少なくとも前記パッシベーション層を貫通して形成された溝と、
を含み、
前記半導体基板の平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される半導体ウエハ。 - 前記溝の幅は、0.5μm〜10μmの範囲である請求項10記載の半導体ウエハ。
- 前記多層配線構造の最上配線層は、パッドを含み、
さらに、前記パッシベーション層を貫通して前記パッドを露出するパッド用開口を含み、
前記溝は、前記パッシベーション層を貫通し、その下の層間絶縁膜内に到達する請求項10記載の半導体ウエハ。 - さらに、前記各チップ領域において、前記多層配線構造の外側に配置され、前記層間絶縁膜を貫通して、前記配線層と同一層により形成されたループ状の耐湿リングを有する請求項10記載の半導体ウエハ。
- 前記多層配線構造は、複数層の下層構造と、前記下層構造より上方に配置された複数層の上層構造を含み、前記層間絶縁膜のおのおのは、銅の拡散を防止できる銅拡散防止層と、その上の絶縁層を含み、前記下層構造の絶縁層と前記上層構造の絶縁層の材料が異なる請求項10記載の半導体ウエハ。
- 前記溝は、チップ領域の各角部の外側で角を落とした概略矩形形状を有する請求項10記載の半導体ウエハ。
- 半導体基板と、
前記半導体基板のチップ領域とスクライブ領域のそれぞれの上方に形成された、配線とダミー配線とを含む配線層と、層間絶縁膜とを交互に積層した多層配線構造と、
前記多層配線構造を覆って形成された、パッシベーション層と、
前記スクライブ領域において、上方から、少なくとも前記パッシベーション層を貫通して形成された溝と、
を含み、
前記半導体基板の平面構成における溝を形成する領域において、前記多層配線構造の少なくとも最上配線層には前記ダミー配線が配置されず、その下方の配線層には前記ダミー配線が配置され、
前記溝の底面は、前記下方の配線層のダミー配線よりも上方に位置するよう形成される半導体装置。 - 前記溝の幅は、0.5μm〜10μmの範囲である請求項16記載の半導体装置。
- 前記多層配線構造の最上配線層は、パッドを含み、
さらに、前記パッシベーション層を貫通して前記パッドを露出するパッド用開口を含み、
前記溝は、前記パッシベーション層を貫通し、その下の層間絶縁膜内に到達する請求項16記載の半導体装置。 - さらに、前記各チップ領域において、前記多層配線構造の外側に配置され、前記層間絶縁膜を貫通して、前記配線層と同一層により形成されたループ状の耐湿リングを有する請求項16記載の半導体装置。
- 前記多層配線構造は、複数層の下層構造と、前記下層構造より上方に配置された複数層の上層構造を含み、前記層間絶縁膜のおのおのは、銅の拡散を防止できる銅拡散防止層と、その上の絶縁層を含み、前記下層構造の絶縁層と前記上層構造の絶縁層の材料が異なる請求項16記載の半導体装置。
- 前記溝は、チップ領域の各角部の外側で角を落とした概略矩形形状を有する請求項16記載の半導体装置。
- 前記溝の外側で、前記多層配線構造の層間絶縁膜が一部欠落している請求項16記載の半導体装置。
- 前記層間絶縁膜が欠落している部分の表面は、前記溝の底面より低い請求項22記載の半導体装置。
- 前記層間絶縁膜が欠落している部分の底面は層間絶縁膜の界面を含み、側面は前記界面から前記溝に達する劈開面を含む請求項23記載の半導体装置。
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JPH02188942A (ja) * | 1989-01-17 | 1990-07-25 | Fujitsu Ltd | 多層配線構造を備えた半導体装置の製造方法 |
JPH03129855A (ja) * | 1989-10-16 | 1991-06-03 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH0945766A (ja) * | 1995-07-28 | 1997-02-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH09199449A (ja) * | 1996-01-19 | 1997-07-31 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH10335333A (ja) * | 1997-03-31 | 1998-12-18 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびに設計方法 |
JP2002270608A (ja) * | 2001-03-09 | 2002-09-20 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2004079596A (ja) * | 2002-08-12 | 2004-03-11 | Renesas Technology Corp | 半導体装置 |
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JP2737979B2 (ja) * | 1989-02-10 | 1998-04-08 | 三菱電機株式会社 | 半導体装置 |
US5136354A (en) * | 1989-04-13 | 1992-08-04 | Seiko Epson Corporation | Semiconductor device wafer with interlayer insulating film covering the scribe lines |
JP3066609B2 (ja) | 1991-03-11 | 2000-07-17 | 富士通株式会社 | 半導体ウエハ |
JPH06338563A (ja) * | 1993-05-31 | 1994-12-06 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH08172062A (ja) * | 1994-12-16 | 1996-07-02 | Oki Electric Ind Co Ltd | 半導体ウエハ及び半導体ウエハの製造方法 |
US6365958B1 (en) * | 1998-02-06 | 2002-04-02 | Texas Instruments Incorporated | Sacrificial structures for arresting insulator cracks in semiconductor devices |
JP2000340529A (ja) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | 半導体装置 |
WO2001009932A1 (fr) * | 1999-07-30 | 2001-02-08 | Nippon Sheet Glass Co., Ltd. | Procede de decoupage de plaquette de semi-conducteur en puces et structure de rainure formee dans la zone de decoupage |
JP4307664B2 (ja) * | 1999-12-03 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001176899A (ja) * | 1999-12-21 | 2001-06-29 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2001196372A (ja) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置 |
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2003
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2004
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH02188942A (ja) * | 1989-01-17 | 1990-07-25 | Fujitsu Ltd | 多層配線構造を備えた半導体装置の製造方法 |
JPH03129855A (ja) * | 1989-10-16 | 1991-06-03 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH0945766A (ja) * | 1995-07-28 | 1997-02-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH09199449A (ja) * | 1996-01-19 | 1997-07-31 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH10335333A (ja) * | 1997-03-31 | 1998-12-18 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびに設計方法 |
JP2002270608A (ja) * | 2001-03-09 | 2002-09-20 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2004079596A (ja) * | 2002-08-12 | 2004-03-11 | Renesas Technology Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
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WO2004097916A1 (ja) | 2004-11-11 |
KR100690493B1 (ko) | 2007-03-09 |
CN100385627C (zh) | 2008-04-30 |
US20130280889A1 (en) | 2013-10-24 |
US8513776B2 (en) | 2013-08-20 |
WO2004097917A1 (ja) | 2004-11-11 |
KR20050050114A (ko) | 2005-05-27 |
CN1701418A (zh) | 2005-11-23 |
US9105706B2 (en) | 2015-08-11 |
US20050269702A1 (en) | 2005-12-08 |
JPWO2004097917A1 (ja) | 2006-07-13 |
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