JP5041088B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5041088B2 JP5041088B2 JP2011090703A JP2011090703A JP5041088B2 JP 5041088 B2 JP5041088 B2 JP 5041088B2 JP 2011090703 A JP2011090703 A JP 2011090703A JP 2011090703 A JP2011090703 A JP 2011090703A JP 5041088 B2 JP5041088 B2 JP 5041088B2
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Description
W1>2×W2+n×W3
が成立する場合、配線510内を流れる電流密度が許容限界値になると、パッド505内において、閉じた線511と交差する方向に流れる電流密度が許容値を超えてしまう。
半導体基板と、
前記半導体基板の上に形成された絶縁性材料からなる第1の絶縁膜と、
前記第1の絶縁膜の上に形成された導電材料からなるパッド部と、
前記パッド部に電気的に連続し、第1の幅W1を有する配線部と、
前記第1の絶縁膜の上の、前記パッド部の外周線から第2の幅W2より内側の第1の領域であって、前記パッド部の内部に配置された複数の第2の絶縁膜と
を有し、
前記配線部と前記パッド部との境界線に最も近い前記第2の絶縁膜を連ねる直線のうち、前記配線部を前記パッド部内に延長した領域と重なる部分が、前記パッド部の導電材料と交差する長さをL3としたとき、W1≦2×W2+L3を満たす半導体装置が提供される。
第1の枠状領域27aの幅L1は、間隔P2以上である。
(付記1) (a)表面上に半導体素子が形成された半導体基板の上に、絶縁材料からなる第1の層間絶縁膜を形成する工程と、
(b)前記第1の層間絶縁膜の上に、絶縁材料からなる第1の層内絶縁膜を形成する工程と、
(c)前記第1の層内絶縁膜に凹部を形成する工程であって、該凹部は、パッド部と、該パッド部に連続する配線部とを含み、該パッド部は、該配線部の幅よりも広い幅を有し、該パッド部内に複数の凸部が残されており、該パッド部の外周を外周線とし第1の幅を有する枠状の第1の枠状領域のうち、前記配線部を該パッド部内に延長した領域と重なる配線近傍領域における凹部の面積比が、前記第1の枠状領域の内周線を外周線とし第2の幅を有する枠状の第2の枠状領域における凹部の面積比よりも大きくなるように前記凸部が配置されるように凹部を形成する工程と、
(d)前記凹部内を埋め込むように、前記半導体基板上に導電性材料からなる第1の膜を形成する工程と、
(e)前記第1の膜の上層部を除去し、前記凹部内に残った該第1の膜からなる第1のパッドを形成する工程と
を有する半導体装置の製造方法。
(付記2) 前記工程(e)の後、さらに、
(f)前記第1の層内絶縁膜及び残された前記第1の膜の上に、絶縁材料からなる第2の層間絶縁膜を形成する工程と、
(g)前記第2の層間絶縁膜にビアホールを形成する工程であって、基板の法線に平行な視線で見たとき、該ビアホールが前記第1のパッドに内包されるように前記ビアホールを形成する工程と、
(h)前記第2の層間絶縁膜の上に、前記ビアホール内を経由して前記第1のパッドに接続された第2のパッドを形成する工程と
を有する付記1に記載の半導体装置の製造方法。
(付記3) 前記工程(h)の後、さらに、
(i)前記第2のパッドに導電性の針を接触させて、前記半導体素子の検査を行う工程を含む付記2に記載の半導体装置の製造方法。
(付記4) 前記工程(i)の後、さらに、
(j)前記第2のパッドの内側を通過するように、前記半導体基板をスクライビングする工程を含む付記3に記載の半導体装置の製造方法。
(付記5) 前記第1の枠状領域内に、前記凸部が配置されていない付記1乃至4のいずれかに記載の半導体装置の製造方法。
(付記6) 前記第2の枠状領域よりも内側の中央領域には前記凸部が残されておらず、
さらに、前記工程(e)の後、前記第1の層内絶縁膜及び残された前記第1の膜の上に、絶縁材料からなる第2の層間絶縁膜を形成する工程と、
前記第2の層間絶縁膜にビアホールを形成する工程であって、基板の法線に平行な視線で見たとき、該ビアホールが前記中央領域に内包されるように前記ビアホールを形成する工程と、
前記第2の層間絶縁膜の上に、前記ビアホール内を経由して前記第1のパッドに接続された第2のパッドを形成する工程と、
前記第2のパッドに、導線をワイヤボンディングする工程であって、基板の法線に平行な視線でみたとき、前記導線と前記第2のパッドとの接触部が前記ビアホールの外側まで広がるようにボンディングを行う工程と
を有する付記1に記載の半導体装置の製造方法。
(付記7) 半導体基板と、
前記半導体基板の上に形成された絶縁性材料からなる第1の層間絶縁膜と、
前記第1の層間絶縁膜の上に形成された第1の層内絶縁膜であって、該第1の層内絶縁膜の底面まで達する凹部が設けられており、該凹部は、パッド部と、該パッド部に連続する配線部とを含み、該パッド部は、該配線部の幅よりも広く、該パッド部内に複数の凸部が残されており、該パッド部の外周を外周線とし第1の幅を有する枠状の第1の枠状領域のうち、前記配線部を該パッド部内に延長した領域と重なる配線近傍領域における凹部の面積比が、前記第1の枠状領域の内周線を外周線とし第2の幅を有する枠状の第2の枠状領域における凹部の面積比よりも大きくなるように前記凸部が配置されている前記第1の層内絶縁膜と、
前記凹部のパッド部内に埋め込まれた第1のパッドと、
前記凹部の配線部内に埋め込まれた配線と
を有する半導体装置。
(付記8) 前記第1の層内絶縁膜、前記第1のパッド、及び前記配線の上に形成され、基板の法線に平行な視線で見たとき、前記第1のパッドと部分的に重なるように配置されたビアホールが設けられている第2の層間絶縁膜と、
前記第2の層間絶縁膜の上に形成され、前記ビアホール内を経由して前記第1のパッドに接続された第2のパッドと
を有する付記7に記載の半導体装置。
(付記9) 前記配線近傍領域内に前記凸部が配置されていない付記7または8に記載の半導体装置。
(付記10) 前記第2の枠状領域よりも内側の中央領域内に前記凸部が配置されていない付記7乃至9のいずれかに記載の半導体装置。
(付記11) 基板の法線に平行な視線で見たとき、前記ビアホールが前記第1のパッドに内包されている付記7乃至10のいずれかに記載の半導体装置。
(付記12) 前記第2の枠状領域内に、前記凸部が第1の方向に第1のピッチで規則的に配置されており、前記第1の枠状領域の前記第1の方向に関する幅が、該第1のピッチ以上である付記7乃至11のいずれかに記載の半導体装置。
(付記13) さらに、前記パッドにワイヤボンディングされた導線を有し、前記第2の枠状領域よりも内側の中央領域内に前記凸部が配置されておらず、前記ビアホールが前記中央領域内に配置されており、基板の法線に平行な視線で見たとき、前記第2のパッドと前記導線との接触部が前記ビアホールの外側まで広がっている付記8に記載の半導体装置。
5 素子分離絶縁膜
6 MOSFET
10、30、40、101 層間絶縁膜
11、35、45、108 ビアホール
12A、26、36、47、51、52、115 バリアメタル層
12B、37、46 プラグ
20 配線層
21、103 層内絶縁膜
22、31、41、100 エッチングストッパ膜
23 中層膜
24 上層膜
25 配線
27、50 パッド
60 配線
70 被覆膜
71 開口
80、105 レジストパターン
109 樹脂
112 凹部
116 導電膜
Claims (4)
- 半導体基板と、
前記半導体基板の上に形成された絶縁性材料からなる第1の絶縁膜と、
前記第1の絶縁膜の上に形成された導電材料からなるパッド部と、
前記パッド部に電気的に連続し、第1の幅W1を有する配線部と、
前記第1の絶縁膜の上の、前記パッド部の外周線から第2の幅W2より内側の第1の領域であって、前記パッド部の内部に配置された複数の第2の絶縁膜と
を有し、
前記配線部と前記パッド部との境界線に最も近い前記第2の絶縁膜を連ねる直線のうち、前記配線部を前記パッド部内に延長した領域と重なる部分が、前記パッド部の導電材料と交差する長さをL3としたとき、W1≦2×W2+L3を満たす半導体装置。 - 前記第1の領域内に、前記第2の絶縁膜が等間隔で配置されている請求項1に記載の半導体装置。
- 前記パッド部内の前記第1の領域外に、前記第2の絶縁膜が配置されておらず、かつ前記等間隔よりも大きな幅を有する領域が含まれている請求項2に記載の半導体装置。
- 前記パッド部の前記外周線から前記第2の幅W2の領域と、前記配線部を前記パッド部内に延長した領域とが重なる領域であって前記配線部と接する領域に、前記第2の絶縁膜が配置されないことを特徴とする請求項1に記載の半導体装置。
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