JP5259211B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5259211B2 JP5259211B2 JP2008032666A JP2008032666A JP5259211B2 JP 5259211 B2 JP5259211 B2 JP 5259211B2 JP 2008032666 A JP2008032666 A JP 2008032666A JP 2008032666 A JP2008032666 A JP 2008032666A JP 5259211 B2 JP5259211 B2 JP 5259211B2
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Description
図1は本実施の形態1における半導体チップCHP(半導体装置)の構成を示した平面図である。本実施の形態1における半導体チップCHPは、LCDドライバである。図1において、半導体チップCHPは、例えば細長い長方形状(矩形形状)に形成された半導体基板1Sを有しており、その主面には、例えば液晶表示装置を駆動するLCDのドライバが形成されている。このLCDドライバは、LCDを構成するセルアレイの各画素に電圧を供給して液晶分子の向きを制御する機能を有しており、ゲート駆動回路、ソース駆動回路、液晶駆動回路、グラフィックRAM(Random Access Memory)および周辺回路などを有している。これらの機能は、半導体基板1Sに形成される半導体素子および配線によって実現されている。まず、この半導体チップCHPの表面構成について説明する。
前記実施の形態1では、図7および図8に示すように、異なる層に形成されているパターンP1aとパターンP3を平面的に重なるように配置し(図7参照)、かつ、異なる層に形成されているパターンP1bとパターンP2を平面的に重なるように配置している(図8参照)。これに対し、本実施の形態2では、異なる層に形成されているパターンP1a、P1b、P2を平面的に重なるように配置し、かつ、パターンP3とは平面的に重ならないように配置する例について説明する。
2 ゲート絶縁膜
3 ポリシリコン膜
4 低濃度n型不純物拡散領域
5 サイドウォール
6 高濃度n型不純物拡散領域
7 窒化シリコン膜
8 酸化シリコン膜
9 酸化シリコン膜
10 酸化シリコン膜
11 酸化シリコン膜
12 窒化シリコン膜
13 開口部
14 UBM膜
15 レジスト膜
16 開口部
17 金膜
20 ガラス基板
20a 電極
21 ガラス基板
22 絶縁層
23 金属粒子
24 表示部
25 液晶表示装置
ACF 異方性導電フィルム
AM アライメントマーク
BG 背景領域
BP1 バンプ電極
BP2 バンプ電極
C カメラ
CHP 半導体チップ
FPC フレキシブルプリント基板
G ゲート電極
GR ガードリング
GR1 配線
GR2 配線
GR3 配線
L1 第1層配線
L2 第2層配線
L3 第3層配線
MK1 マーク
MK2 マーク
MK3 マーク
P1a パターン
P1b パターン
P2 パターン
P3 パターン
PLG1 プラグ
PLG2 プラグ
PLG3 プラグ
PWL p型ウェル
STI 素子分離領域
Claims (16)
- 半導体チップを備え、
前記半導体チップは、前記半導体チップを実装基板に搭載するときの位置決めに使用されるアライメントマークが形成されているアライメントマーク形成領域と、集積回路が形成されている集積回路形成領域とを含み、
前記アライメントマーク形成領域では、
(a)前記アライメントマークが形成されたマーク領域と、
(b)前記マーク領域を囲む背景領域とを有し、
前記集積回路形成領域では、
(c)半導体基板に形成された複数の素子分離領域と、
(d)前記複数の素子分離領域で区画された活性領域に形成され、且つ、ゲート電極を有するMISFETと、
(e)前記MISFET上を含む前記半導体基板上に形成された配線が形成され、前記配線は複数層にわたって形成されており、前記配線のうち最上層配線と前記アライメントマークは同層で形成されている半導体装置であって、
前記背景領域の下層には複数の第1パターンが形成されており、
前記複数の第1パターンは、複数の層に形成され、
前記複数の層に形成された前記複数の第1パターンは、前記集積回路形成領域で前記最上層配線よりも下層に形成される複数層の前記配線と同層で形成され、
前記第1パターンの下層には、さらに、前記集積回路形成領域に形成された前記MISFETのゲート電極と同層で形成された複数の第2パターンが形成され、
前記第2パターンの下層には、さらに、前記集積回路形成領域に形成された前記素子分離領域と同層で形成された複数の第3パターンが形成され、
前記アライメントマーク形成領域は、前記集積回路を形成しない領域であり、
前記複数の第1パターン、前記複数の第2パターン及び前記複数の第3パターンは、それぞれ、前記集積回路を構成していないことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の第2パターンは、ドット状に形成されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記複数の第2パターンは、前記背景領域の下層だけでなく前記マーク領域の下層にも形成されていることを特徴とする半導体装置。 - 請求項3記載の半導体装置であって、
前記ゲート電極及び前記複数の第2パターンは、ポリシリコン膜から形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の第3パターンは、ドット状に形成されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記複数の第3パターンは、前記背景領域の下層だけでなく前記マーク領域の下層にも形成されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記素子分離領域及び前記複数の第3パターンは、前記半導体基板に形成された溝内に絶縁膜を埋め込んだ構造をしていることを特徴とする半導体装置。 - 請求項1〜7の何れか1項に記載の半導体装置であって、
前記複数の第1パターンは、ドット状に形成されていることを特徴とする半導体装置。 - 請求項8記載の半導体装置であって、
前記複数の第1パターンは、前記背景領域の下層だけでなく前記マーク領域の下層にも形成されていることを特徴とする半導体装置。 - 請求項9記載の半導体装置であって、
前記配線及び前記複数の第1パターンは、金属膜から形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の層に形成されている前記複数の第1パターンは、平面的に重なるように配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の層に形成されている前記複数の第1パターンは、平面的に重ならないように配置されていることを特徴とする半導体装置。 - 請求項1〜12の何れか1項に記載の半導体装置であって、
前記集積回路形成領域の前記最上層配線上にはバンプ電極が形成されていることを特徴とする半導体装置。 - 請求項13記載の半導体装置であって、
前記半導体チップと前記実装基板とは、異方性導電フィルムを介して前記半導体チップに形成されている前記バンプ電極と、前記実装基板に形成されている配線を圧接することにより電気的に接続されていることを特徴とする半導体装置。 - 請求項1〜14の何れか1項に記載の半導体装置であって、
前記半導体チップは、液晶表示装置用のLCDドライバであることを特徴とする半導体装置。 - 請求項1〜15の何れか1項に記載の半導体装置は、更に、
前記集積回路形成領域の複数層の前記配線と同層で形成されているガードリングを含み、
前記ガードリングは、平面的に前記アライメントマーク形成領域及び前記集積回路形成領域を内包するように、前記半導体チップの外縁に形成されており、
前記アライメントマーク形成領域は、平面的に前記ガードリングと前記集積回路形成領域との間に形成されており、
前記アライメントマーク形成領域と前記ガードリングとの間には、前記集積回路形成領域は設けられていないことを特徴とする半導体装置。
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