JP2012064713A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2012064713A JP2012064713A JP2010206920A JP2010206920A JP2012064713A JP 2012064713 A JP2012064713 A JP 2012064713A JP 2010206920 A JP2010206920 A JP 2010206920A JP 2010206920 A JP2010206920 A JP 2010206920A JP 2012064713 A JP2012064713 A JP 2012064713A
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- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 61
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 12
- 238000001459 lithography Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 10
- 238000005498 polishing Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】実施形態の半導体装置の製造方法は、基板1上に所望の配線厚みに対応する厚みのエッチングストッパー膜2を形成し、酸化膜3を形成し、マスク材4を形成し、マスク材に配線の形状の溝パターンを形成し、溝パターンが形成されたマスク材をマスクとして酸化膜に溝パターンが形成されるようにエッチングする。溝パターンが形成された酸化膜をマスクとして、溝パターンが形成されるようにエッチングストッパー膜を貫通するまでエッチングし、エッチングストッパー膜および酸化膜に形成された溝パターンを埋め込み、酸化膜の上面を覆いつくすようにCu膜5を形成し、エッチングストッパー膜をストッパーとして、その上面が露出するまでCu膜及び酸化膜にCMPを行う。
【選択図】図1
Description
図1は、本実施形態にかかる半導体装置の製造方法を示す断面図を図1(a)〜(g)に工程順に示したものである。
Claims (5)
- 半導体基板上に、Cu配線に対する所望の厚みに対応する厚みのエッチングストッパー膜を形成する工程と、
前記エッチングストッパー膜の上にシリコン酸化膜を形成する工程と、
前記シリコン酸化膜の上にマスク材を形成する工程と、
リソグラフィーにより前記マスク材に前記Cu配線の形状の溝パターンを形成する工程と、
前記溝パターンが形成された前記マスク材をエッチングマスクとして、前記シリコン酸化膜に前記溝パターンが形成されるようにエッチングする工程と、
前記溝パターンが形成された前記シリコン酸化膜をエッチングマスクとして、前記エッチングストッパー膜に前記溝パターンが形成されるように前記エッチングストッパー膜を貫通するまでエッチングする工程と、
前記エッチングストッパー膜および前記シリコン酸化膜に形成された前記溝パターンを埋め込み、前記シリコン酸化膜の上面を覆いつくすようにCu膜を形成する工程と、
前記エッチングストッパー膜をCMPストッパーとして、前記エッチングストッパー膜の上面が露出するまで前記Cu膜及び前記シリコン酸化膜にCMPを行う工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記CMPを行う工程の後に、絶縁膜であるキャップ材を成膜する工程を
さらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記キャップ材はSiNあるいはSiCNである
ことを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記エッチングストッパーはSiNあるいはSiCNである
ことを特徴とする請求項1〜3のいずれか1項に記載の半導体装置の製造方法。 - 前記半導体基板は下層配線を有し、
前記Cu膜を形成する工程は、前記溝パターンを埋め込んだ前記Cu膜が前記下層配線と接続するように前記Cu膜を形成する
ことを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010206920A JP2012064713A (ja) | 2010-09-15 | 2010-09-15 | 半導体装置の製造方法 |
US13/230,106 US20120061837A1 (en) | 2010-09-15 | 2011-09-12 | Method of manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (1)
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---|---|---|---|
JP2010206920A JP2012064713A (ja) | 2010-09-15 | 2010-09-15 | 半導体装置の製造方法 |
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Publication Number | Publication Date |
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JP2012064713A true JP2012064713A (ja) | 2012-03-29 |
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JP2010206920A Pending JP2012064713A (ja) | 2010-09-15 | 2010-09-15 | 半導体装置の製造方法 |
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US (1) | US20120061837A1 (ja) |
JP (1) | JP2012064713A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016186975A (ja) * | 2015-03-27 | 2016-10-27 | 東レエンジニアリング株式会社 | Ledモジュールおよびledモジュールの製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112086348B (zh) * | 2020-08-31 | 2022-11-29 | 上海华力微电子有限公司 | 双重图形氧化硅芯轴制备方法 |
Citations (8)
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JPH05182966A (ja) * | 1991-12-27 | 1993-07-23 | Sony Corp | 多層配線形成方法 |
JP2002009058A (ja) * | 2000-06-26 | 2002-01-11 | Tokyo Electron Ltd | エッチング方法 |
JP2002334926A (ja) * | 2001-03-23 | 2002-11-22 | Texas Instruments Inc | 微細構造のための金属化を容易にする犠牲層の使用 |
JP2003077920A (ja) * | 2001-09-04 | 2003-03-14 | Nec Corp | 金属配線の形成方法 |
JP2004014828A (ja) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004193544A (ja) * | 2002-05-08 | 2004-07-08 | Nec Electronics Corp | 半導体装置、および半導体装置の製造方法 |
JP2004281936A (ja) * | 2003-03-18 | 2004-10-07 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2010171064A (ja) * | 2009-01-20 | 2010-08-05 | Panasonic Corp | 半導体装置及びその製造方法 |
Family Cites Families (10)
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US6849557B1 (en) * | 1997-04-30 | 2005-02-01 | Micron Technology, Inc. | Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide |
US6541367B1 (en) * | 2000-01-18 | 2003-04-01 | Applied Materials, Inc. | Very low dielectric constant plasma-enhanced CVD films |
US6294460B1 (en) * | 2000-05-31 | 2001-09-25 | Advanced Micro Devices, Inc. | Semiconductor manufacturing method using a high extinction coefficient dielectric photomask |
US6350700B1 (en) * | 2000-06-28 | 2002-02-26 | Lsi Logic Corporation | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
JP2003045964A (ja) * | 2001-07-30 | 2003-02-14 | Nec Corp | 半導体装置及びその製造方法 |
US6812043B2 (en) * | 2002-04-25 | 2004-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a carbon doped oxide low-k insulating layer |
JP2004071777A (ja) * | 2002-08-06 | 2004-03-04 | Fujitsu Ltd | 有機絶縁膜の作製方法、半導体装置の製造方法、及びtft基板の製造方法 |
WO2004097916A1 (ja) * | 2003-04-30 | 2004-11-11 | Fujitsu Limited | 半導体装置の製造方法、半導体ウエハおよび半導体装置 |
US7999391B2 (en) * | 2006-02-06 | 2011-08-16 | Nec Corporation | Multilayered wiring structure, and method for manufacturing multilayered wiring |
US8102051B2 (en) * | 2007-06-22 | 2012-01-24 | Rohm Co., Ltd. | Semiconductor device having an electrode and method for manufacturing the same |
-
2010
- 2010-09-15 JP JP2010206920A patent/JP2012064713A/ja active Pending
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2011
- 2011-09-12 US US13/230,106 patent/US20120061837A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05182966A (ja) * | 1991-12-27 | 1993-07-23 | Sony Corp | 多層配線形成方法 |
JP2002009058A (ja) * | 2000-06-26 | 2002-01-11 | Tokyo Electron Ltd | エッチング方法 |
JP2002334926A (ja) * | 2001-03-23 | 2002-11-22 | Texas Instruments Inc | 微細構造のための金属化を容易にする犠牲層の使用 |
JP2003077920A (ja) * | 2001-09-04 | 2003-03-14 | Nec Corp | 金属配線の形成方法 |
JP2004193544A (ja) * | 2002-05-08 | 2004-07-08 | Nec Electronics Corp | 半導体装置、および半導体装置の製造方法 |
JP2004014828A (ja) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004281936A (ja) * | 2003-03-18 | 2004-10-07 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2010171064A (ja) * | 2009-01-20 | 2010-08-05 | Panasonic Corp | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016186975A (ja) * | 2015-03-27 | 2016-10-27 | 東レエンジニアリング株式会社 | Ledモジュールおよびledモジュールの製造方法 |
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