JP3664725B2 - 半導体装置用多層回路基板の製造方法 - Google Patents
半導体装置用多層回路基板の製造方法 Download PDFInfo
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- JP3664725B2 JP3664725B2 JP2004274134A JP2004274134A JP3664725B2 JP 3664725 B2 JP3664725 B2 JP 3664725B2 JP 2004274134 A JP2004274134 A JP 2004274134A JP 2004274134 A JP2004274134 A JP 2004274134A JP 3664725 B2 JP3664725 B2 JP 3664725B2
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- 239000004065 semiconductor Substances 0.000 title claims description 134
- 238000004519 manufacturing process Methods 0.000 title claims description 49
- 238000000034 method Methods 0.000 title claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 107
- 239000002184 metal Substances 0.000 claims description 107
- 229910000679 solder Inorganic materials 0.000 claims description 42
- 239000002131 composite material Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 27
- 239000000853 adhesive Substances 0.000 claims description 19
- 230000001070 adhesive effect Effects 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 12
- 239000004744 fabric Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 7
- 239000010419 fine particle Substances 0.000 claims description 7
- 239000004760 aramid Substances 0.000 claims description 4
- 229920003235 aromatic polyamide Polymers 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000002048 anodisation reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 158
- 239000010949 copper Substances 0.000 description 80
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 79
- 229910052802 copper Inorganic materials 0.000 description 79
- 239000011347 resin Substances 0.000 description 42
- 229920005989 resin Polymers 0.000 description 42
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 26
- 239000004020 conductor Substances 0.000 description 20
- 229910052759 nickel Inorganic materials 0.000 description 13
- 239000011651 chromium Substances 0.000 description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
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- Y10T29/49117—Conductor or circuit manufacturing
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Description
次いで、ヴィア128と導体配線102とに相当する部分以外のシードレイヤ142’をエッチングして除去することにより、図14Fに示ように、絶縁層104の表面にヴィア128及び導体配線102を形成する。
2枚の金属板を向き合わせて一体化して複合金属板を作製し、
開口部を有する絶縁層を上記複合金属板の両面に形成し、
当該開口部の底面に露出した当該金属板の部分に凹部を形成し、
当該凹部又は当該凹部と当該開口部内にはんだを充填して、それにより半導体素子に接続するための上記バンプ状のパッドを形成し、
続いて配線層と絶縁層を交互に形成する工程を必要な回数実施して、所定数の配線層と絶縁層を有する多層回路基板本体を作製し、
上記複合金属板を分離して、上記金属板の片面に上記多層回路基板本体を備えた中間体を得、
この中間体から上記金属板をエッチングにより除去して、上記バンプ状のパッドが突出した半導体素子搭載面を露出させることを含む、半導体装置用多層回路基板の製造方法にある。
複合金属板を分離する前に、前記多層回路基板本体の最外層の絶縁層上に、その上に位置する外部接続端子用パッドを露出させる貫通孔を備えた絶縁層を、貫通孔の内壁面を含めて全面を絶縁処理した金属板を前記多層回路基板本体の最外層の絶縁層に接合することにより形成することができる。半導体素子搭載領域の周囲に金属板の一部を枠体として残す場合、多層回路基板の外部接続端子装着面に位置するこの絶縁処理した金属板は、半導体素子搭載面の枠体とともに多層回路基板本体を挟み込み、それにより製造工程で多層回路基板本体に生じがちな反りを防止でき、そしてまた最終的に得られる多層回路基板の強度の向上にも寄与する。
多層回路基板本体の最外層の絶縁層への絶縁処理した金属板の接合は、接着剤を使って行うことができる。好ましくは、この接着剤は、接合後に多層回路基板本体の最外層の絶縁層と絶縁処理した金属板との間に、当該接着剤が絶縁処理金属板の貫通孔内にはみ出すのを防止できる間隙を形成し得る径の絶縁性微粒子を含有する。
本発明の方法では、複合金属板の両面に形成した絶縁層の前記開口部を、絶縁層表面の径に比べ底部の径が小さい開口部として形成し、当該開口部の底部に露出した金属板をエッチングして、上記開口部に通じる箇所の径が当該開口部の底面の径と等しいかそれより大きい空洞を、前記凹部として当該金属板に形成し、そして当該空洞及び開口部内にはんだを充填することにより、半導体素子接続用の前記バンプ状のパッドを形成することもできる。
この場合のはんだの充填は、空洞を形成した金属板を給電層として使用する電解めっきにより、あるいははんだペーストを用いて、行うことができる。
多層回路基板本体の外部接続端子装着面側の最外層の絶縁層は、ガラスクロスプリプレグ又はアラミドを含有したプリプレグにより形成してもよい。
前記複合金属板を分離する前に、前記多層回路基板本体の最外層の絶縁層上に、その上に位置する外部接続端子用パッドを露出させる貫通孔を備えた絶縁層をソルダレジストにより形成してもよい。
一つの態様として、多層回路基板本体を作製するのに使用した金属板としての銅板を、上述のように部分的に除去するのでなく、その全てを除去することができる。
更に、本発明では、両面に多層回路基板本体を形成した複合金属板を分離することにより、1枚の金属板の一面側に多層回路基板本体を形成した2個の中間体を同時に得ることができ、単一の金属板を使用して多層回路基板本体を形成する場合に比較して生産効率にも優れている。
11 銅板
12 ニッケル膜
14 複合金属板
20 多層回路基板本体
20a 絶縁性樹脂層
22 凹部
24 はんだ層
26 導体配線
28 貫通孔
30 絶縁処理金属板
32 接着剤
33 外部接続端子用パッド
34 中間体
36 アルマイト層
37 絶縁性微粒子
38 はんだボール
39 半導体素子
40 ソルダレジスト
50、50’ 半導体装置用多層回路基板
Claims (12)
- 複数組の配線層と絶縁層とから形成した多層回路基板本体であって、半導体素子を搭載するための面と外部接続端子用のもう一方の面とを有し、半導体素子搭載面には搭載しようとする半導体素子にそれを通して多層回路基板が接続するバンプ状のパッドが設けられ、外部接続端子用の面には外部の電気回路にそれを通して多層回路基板が接続するパッドが設けられた多層回路基板本体を有する半導体装置用多層回路基板の製造方法であって、
2枚の金属板を向き合わせて一体化して複合金属板を作製し、
開口部を有する絶縁層を上記複合金属板の両面に形成し、
当該開口部の底面に露出した当該金属板の部分に凹部を形成し、
当該凹部又は当該凹部と当該開口部内にはんだを充填して、それにより半導体素子に接続するための上記バンプ状のパッドを形成し、
続いて配線層と絶縁層を交互に形成する工程を必要な回数実施して、所定数の配線層と絶縁層を有する多層回路基板本体を作製し、
上記複合金属板を分離して、上記金属板の片面に上記多層回路基板本体を備えた中間体を得、
この中間体から上記金属板をエッチングにより除去して、上記バンプ状のパッドが突出した半導体素子搭載面を露出させることを含む、半導体装置用多層回路基板の製造方法。 - 前記複合金属板の両面に形成した絶縁層の前記開口部を、絶縁層表面の径に比べ底部の径が小さい開口部として形成し、当該開口部の底部に露出した金属板をエッチングして、上記開口部に通じる箇所の径が当該開口部の底面の径と等しいかそれより大きい空洞を、前記凹部として当該金属板に形成し、そして当該空洞及び開口部内にはんだを充填することにより、半導体素子接続用の前記バンプ状のパッドを形成する、請求項1記載の方法。
- 前記はんだの充填を、前記金属板を給電層として使用する電解めっきにより行う、請求項1又は2記載の方法。
- 前記はんだの充填をはんだペーストを用いて行う、請求項1又は2記載の方法。
- 前記露出した半導体素子搭載面に枠体を接合することを更に含む、請求項1記載の方法。
- 前記金属板の除去を部分的に行い、半導体素子搭載面の半導体素子搭載領域の周囲に前記金属板の一部を枠体として残す、請求項1記載の方法。
- 前記複合金属板を分離する前に、前記多層回路基板本体の最外層の絶縁層上に、その上に位置する外部接続端子用パッドを露出させる貫通孔を備えた絶縁層を、貫通孔の内壁面を含めて全面を絶縁処理した金属板を前記多層回路基板本体の最外層の絶縁層に接合することにより形成する、請求項1記載の方法。
- 前記全面を絶縁処理した金属板として、陽極酸化により表面に絶縁処理を施したアルミニウム製の板を使用する、請求項7記載の方法。
- 前記接合を接着剤を使用して行う、請求項7記載の方法。
- 前記接着剤が、接合後に前記多層回路基板本体の最外層の絶縁層と前記絶縁処理した金属板との間に、当該接着剤が前記貫通孔内にはみ出すのを防止できる間隙を形成し得る径の絶縁性微粒子を含有している、請求項9記載の方法。
- 前記多層回路基板本体の最外層の絶縁層をガラスクロスプリプレグ又はアラミドを含有したプリプレグにより形成する、請求項1記載の方法。
- 前記複合金属板を分離する前に、前記多層回路基板本体の最外層の絶縁層上に、その上に位置する外部接続端子用パッドを露出させる貫通孔を備えた絶縁層をソルダレジストにより形成する、請求項1記載の方法。
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TW200301554A (en) | 2003-07-01 |
JPWO2003039219A1 (ja) | 2005-02-24 |
US6988312B2 (en) | 2006-01-24 |
JP3664720B2 (ja) | 2005-06-29 |
WO2003039219A1 (fr) | 2003-05-08 |
CN1481658A (zh) | 2004-03-10 |
JP2005005742A (ja) | 2005-01-06 |
US20040074088A1 (en) | 2004-04-22 |
JP2005005743A (ja) | 2005-01-06 |
CN1224305C (zh) | 2005-10-19 |
TWI222201B (en) | 2004-10-11 |
JP3637969B2 (ja) | 2005-04-13 |
KR20040030478A (ko) | 2004-04-09 |
KR100516795B1 (ko) | 2005-09-26 |
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