JP5269563B2 - 配線基板とその製造方法 - Google Patents
配線基板とその製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
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Description
(a)エッチングにより除去可能な支持体上に表面めっき層と外部接続用パッドを順次形成する工程、
(b)当該外部接続用パッドの外周縁を、表面めっき層の外周縁よりパッド中心に向け後退させる加工を施す工程、
(c)当該外部接続用パッドを形成した支持体上に所定数の絶縁層と配線層を形成する工程、
(d)上記支持体を除去する工程、
を含む配線基板製造方法により製造することができる。
この例では、表面めっき層の表面と配線基板の表面が同一平面にある配線基板を、その製造方法とともに説明する。
ここでは、表面めっき層の表面と配線基板の表面が同一平面にある配線基板を、そのもう一つの製造方法とともに説明する。
〔実施例3〕
ここでは、表面めっき層が配線基板の凹部に位置している配線基板の例を、その製造方法とともに説明する。なお、以下の実施例で使用する部材の材質や寸法、処理方法などは、特に断らない限り、実施例1、2で説明したとおりである。
ここでは、表面めっき層が配線基板の凹部に位置している配線基板のもう一つの例を、その製造方法とともに説明する。
ここでは、表面めっき層が配線基板の凹部に位置している配線基板の別の例を、その製造方法とともに説明する。
ここでは、表面めっき層が配線基板表面から突出している配線基板の例を、その製造方法とともに説明する。
ここでは、表面めっき層が配線基板表面から突出している配線基板のもう一つの例を、その製造方法とともに説明する。
2 表面めっき層
10、30、40、50、60、70、80 配線基板
11、31、41、51、61、71、81 支持体
13、33、43、53、63、73、83 表面めっき層
14、34、44、54、64、74、84 外部接続用パッド
15、35、45、55、65、75、85 絶縁層
16a、36a、46a、56a、66a、76a、86a ビア
16b、36b、46b、56b、66b、76b、86b 配線層
17、37、47、57、67、77、87 外部接続用パッド
18、38、48、58、68、78、88 ソルダレジスト層
19、39、49、59、69、79、89 表面めっき層
Claims (11)
- 所定数の配線層と各配線層の間の絶縁層を有し、且つ、外部の回路に接続するための、表面めっき層を備えた外部接続用パッドを有する配線基板であって、
当該配線基板の一方の面における外部接続用パッドの外周縁が、表面めっき層の外周縁より、パッド中心に向け後退していること、
前記一方の面における前記表面めっき層の表面が前記配線基板の表面と同じ平面に位置すること、
前記一方の面における前記外部接続用パッドが、当該配線基板に半導体素子又はその他の電子部品を搭載するためのパッドであること、
前記一方の面となる絶縁層内に、表面めっき層を備えた外部接続用パッドが埋設され、それにより表面めっき層を備えた外部接続用パッドの外周縁と裏面が当該絶縁層に取り囲まれていること、
前記一方の面となる絶縁層の裏面に設けられた配線パターンと一体に形成されて当該配線パターンに接続するとともに、前記表面めっき層を備えた外部接続用パッドの裏面に接続しているビアを有すること、
前記ビアが、前記表面めっき層を備えた外部接続用パッドの裏面に接続する部分よりも前記配線パターンに接続する部分の径が大きい円錐台形状であること、
を特徴とする配線基板。 - 前記外部接続用パッドが前記表面めっき層を介して半導体素子をバンプによりフリップチップ接続するためのパッドである、請求項1記載の配線基板。
- 前記表面めっき層の材料が、(1)NiとAuの組み合わせ、(2)NiとPdとAuの組み合わせ、(3)Sn、及び(4)SnとAgとの組み合わせ、のうちの一つである、請求項1又は2記載の配線基板。
- 当該配線基板の他方の面に、当該配線基板を別の基板に実装するためのパッドが設けられている、請求項1〜3のいずれか一つに記載の配線基板。
- 所定数の配線層と各配線層の間の絶縁層を有し、且つ、外部の回路に接続するための、表面めっき層を備えた外部接続用パッドを有する配線基板であり、配線基板の一方の面における外部接続用パッドの外周縁が、表面めっき層の外周縁より、パッド中心に向け後退していて、前記一方の面における前記表面めっき層の表面が前記配線基板の表面と同じ平面に位置し、前記一方の面における前記外部接続用パッドが、当該配線基板に半導体素子又はその他の電子部品を搭載するためのパッドであり、前記一方の面となる絶縁層内に、表面めっき層を備えた外部接続用パッドが埋設され、それにより表面めっき層を備えた外部接続用パッドの外周縁と裏面が当該絶縁層に取り囲まれており、当該配線基板は、前記一方の面となる絶縁層の裏面に設けられた配線パターンと一体に形成されて当該配線パターンに接続するとともに、前記表面めっき層を備えた外部接続用パッドの裏面に接続しているビアを有し、前記ビアが、前記表面めっき層を備えた外部接続用パッドの裏面に接続する部分よりも前記配線パターンに接続する部分の径が大きい円錐台形状である配線基板を製造する方法であって、
(a)エッチングにより除去可能な支持体上に表面めっき層と外部接続用パッドを順次形成する工程、
(b)当該外部接続用パッドの外周縁を、表面めっき層の外周縁よりパッド中心に向け後退させる加工を施す工程、
(c)前記支持体上に、前記外部接続用パッドを覆う絶縁層を形成する工程、
(d)工程(c)で形成した絶縁層にビア孔を形成し,当該ビア孔は、当該絶縁層の表面における開口部の径が前記外部接続用パッドを露出させる底部における径より大きい円錐台形状の孔として形成する工程、
(e)前記外部接続用パッドに接続するビアと、工程(c)で形成した絶縁層上に当該ビアと一体に形成された配線パターンとからなる配線層を形成する工程、
(f)工程(e)で配線層を形成した支持体上に所定数の絶縁層と配線層を形成する工程、
(g)上記支持体を除去する工程、
を含むことを特徴とする配線基板製造方法。 - 前記工程(a)における前記表面めっき層と外部接続用パッドの形成を、前記支持体上に開口部を有するマスクパターンを設け、当該開口部に露出する前記支持体に電解めっきを施して行う、請求項5記載の配線基板製造方法。
- 前記工程(b)を、前記マスクパターンを使用する外部接続用パッドの選択エッチングにより行い、前記マスクパターンをその後除去する、請求項6記載の配線基板製造方法。
- 前記工程(a)において前記外部接続用パッドを前記支持体の材料と異なる材料で形成し、そして前記工程(a)後に前記マスクパターンを除去してから、前記工程(b)を前記外部接続用パッドの選択エッチングにより行う、請求項6記載の配線基板製造方法。
- 前記外部接続用パッドを前記表面めっき層を介して半導体素子をバンプによりフリップチップ接続するためのパッドとして形成する、請求項5〜8のいずれか一つに記載の配線基板製造方法。
- 前記表面めっき層の材料が、(1)NiとAuの組み合わせ、(2)NiとPdとAuの組み合わせ、(3)Sn、及び(4)SnとAgとの組み合わせ、のうちの一つである、請求項5〜9のいずれか一つに記載の配線基板製造方法。
- 前記配線基板の他方の面に、当該配線基板を別の基板に実装するためのパッドを設ける、請求項5〜10のいずれか一つに記載の配線基板製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008305154A JP5269563B2 (ja) | 2008-11-28 | 2008-11-28 | 配線基板とその製造方法 |
US12/626,025 US8183467B2 (en) | 2008-11-28 | 2009-11-25 | Wiring board and method of producing the same |
US13/427,235 US8754336B2 (en) | 2008-11-28 | 2012-03-22 | Wiring board and method of producing the same |
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JP2008305154A JP5269563B2 (ja) | 2008-11-28 | 2008-11-28 | 配線基板とその製造方法 |
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JP2013097979A Division JP5701333B2 (ja) | 2013-05-07 | 2013-05-07 | 配線基板とその製造方法 |
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KR20160010960A (ko) * | 2014-07-21 | 2016-01-29 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP6358431B2 (ja) | 2014-08-25 | 2018-07-18 | 新光電気工業株式会社 | 電子部品装置及びその製造方法 |
KR102340053B1 (ko) * | 2015-06-18 | 2021-12-16 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 제조 방법 |
JP2017050313A (ja) * | 2015-08-31 | 2017-03-09 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
WO2020090601A1 (ja) * | 2018-10-30 | 2020-05-07 | 凸版印刷株式会社 | 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法 |
US11164814B2 (en) * | 2019-03-14 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
JP7266454B2 (ja) * | 2019-04-25 | 2023-04-28 | 新光電気工業株式会社 | 配線基板、積層型配線基板、及び配線基板の製造方法 |
US20220069489A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
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