JP5578962B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- JP5578962B2 JP5578962B2 JP2010143862A JP2010143862A JP5578962B2 JP 5578962 B2 JP5578962 B2 JP 5578962B2 JP 2010143862 A JP2010143862 A JP 2010143862A JP 2010143862 A JP2010143862 A JP 2010143862A JP 5578962 B2 JP5578962 B2 JP 5578962B2
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- insulating layer
- layer
- wiring
- opening
- insulating
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- 229920005989 resin Polymers 0.000 claims description 59
- 239000011347 resin Substances 0.000 claims description 59
- 239000000945 filler Substances 0.000 claims description 55
- 239000000203 mixture Substances 0.000 claims description 33
- 230000003014 reinforcing effect Effects 0.000 claims description 14
- 230000003746 surface roughness Effects 0.000 claims description 8
- 239000000835 fiber Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 49
- 239000010949 copper Substances 0.000 description 43
- 229910052751 metal Inorganic materials 0.000 description 41
- 239000002184 metal Substances 0.000 description 41
- 239000004065 semiconductor Substances 0.000 description 40
- 239000010931 gold Substances 0.000 description 39
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 31
- 239000011521 glass Substances 0.000 description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 29
- 239000004744 fabric Substances 0.000 description 29
- 239000000463 material Substances 0.000 description 28
- 238000005422 blasting Methods 0.000 description 27
- 229910052802 copper Inorganic materials 0.000 description 26
- 239000000758 substrate Substances 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 20
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 17
- 239000003822 epoxy resin Substances 0.000 description 16
- 229920000647 polyepoxide Polymers 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000010586 diagram Methods 0.000 description 13
- 238000003672 processing method Methods 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000003365 glass fiber Substances 0.000 description 7
- 239000002245 particle Substances 0.000 description 7
- 239000006061 abrasive grain Substances 0.000 description 6
- 239000007864 aqueous solution Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 150000003949 imides Chemical class 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000011342 resin composition Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000005995 Aluminium silicate Substances 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- IDCBOTIENDVCBQ-UHFFFAOYSA-N TEPP Chemical compound CCOP(=O)(OCC)OP(=O)(OCC)OCC IDCBOTIENDVCBQ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 235000012211 aluminium silicate Nutrition 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- NLYAJNPCOHFWQQ-UHFFFAOYSA-N kaolin Chemical compound O.O.O=[Al]O[Si](=O)O[Si](=O)O[Al]=O NLYAJNPCOHFWQQ-UHFFFAOYSA-N 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 229920001778 nylon Polymers 0.000 description 1
- 235000011837 pasties Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
第1の実施の形態では、本発明を、半導体チップを搭載することにより半導体パッケージとなる配線基板に適用する例を示す。
始めに、第1の実施の形態に係る配線基板の構造について説明する。図2は、第1の実施の形態に係る配線基板を例示する断面図である。図2を参照するに、第1の実施の形態に係る配線基板10は、第1配線層11、第1絶縁層12、第2配線層13、第2絶縁層14、第3配線層15、第3絶縁層16、第4配線層17、第4絶縁層18が順次積層された構造を有する。
続いて、第1の実施の形態に係る配線基板の製造方法について説明する。図3〜図10は、第1の実施の形態に係る配線基板の製造工程を例示する図である。
第1の実施の形態では、最上層の絶縁層を含む全ての絶縁層の材料として同一組成の非感光性の絶縁性樹脂を用い、かつ、全ての絶縁層が同一組成のフィラーを30vol%以上65vol%以下含有するようにし、全ての絶縁層の熱膨張係数を12ppm/℃以上35ppm/℃以下の範囲に調整する例を示した。第2の実施の形態では、更に、外部接続端子側の最上層の絶縁層(第4絶縁層)の下側に隣接する絶縁層(第3絶縁層)にガラスクロス等の補強部材を設ける例を示す。以下、第1の実施の形態と同一構成部分の説明は極力省略し、第1の実施の形態と異なる部分を中心に説明する。
第1の実施の形態では、最上層の絶縁層を含む全ての絶縁層の材料として同一組成の非感光性の絶縁性樹脂を用い、かつ、全ての絶縁層が同一組成のフィラーを30vol%以上65vol%以下含有するようにし、全ての絶縁層の熱膨張係数を12ppm/℃以上35ppm/℃以下の範囲に調整する例を示した。第3の実施の形態では、更に、外部接続端子側の最上層の絶縁層(第4絶縁層)にガラスクロス等の補強部材を設ける例を示す。以下、第1の実施の形態と同一構成部分の説明は極力省略し、第1の実施の形態と異なる部分を中心に説明する。
始めに、第3の実施の形態に係る配線基板の構造について説明する。図13は、第3の実施の形態に係る配線基板を例示する断面図である。図13を参照するに、第3の実施の形態に係る配線基板50は、開口部18xを有する第4絶縁層18が開口部58xを有する第4絶縁層58に置換され、第4配線層17に凹部17xが設けられている点が、第1の実施の形態に係る配線基板10(図2参照)と相違する。
続いて、第3の実施の形態に係る配線基板の製造方法について説明する。図15〜図17は、第3の実施の形態に係る配線基板の製造工程を例示する図である。
第4の実施の形態では、第1の実施の形態に係る配線基板10(図2参照)に半導体チップを搭載した半導体パッケージの例を示す。以下、第1の実施の形態と同一構成部分の説明は極力省略し、第1の実施の形態と異なる部分を中心に説明する。
[実施例1〜4]
図2において第1絶縁層12と第2絶縁層14との間に更に絶縁層と配線層を各6層交互に積層形成した、全部で10層の絶縁層と配線層を有する配線基板(配線基板Aとする)について、反りのシミュレーションを実行した。
比較例1では、実施例1〜4と同様の構造の配線基板Aにおいて、各絶縁層のフィラーの含有量を23vol%とすることにより熱膨張係数を約45ppm/℃に調整した。
比較例2では、配線基板Aの外部接続端子側の最上層の絶縁層のみをエポキシ系樹脂を主成分とする感光性の絶縁性樹脂(熱膨張係数は60〜65ppm/℃)とし、その他の絶縁層(エポキシ系樹脂を主成分とする非感光性の絶縁性樹脂)のフィラーの含有量を23vol%とすることにより熱膨張係数を約45ppm/℃に調整した。
図19A及び図19Bは、配線基板Aの反りの方向を説明する図である。図19A及び図19Bに示す配線基板Aにおいて、一点鎖線で示す面が半導体チップ搭載面とする。図19Aに示すように、半導体チップ搭載面が凸状に反った場合の反りの量Tをプラスとし、図19Bに示すように、半導体チップ搭載面が凹状に反った場合の反りの量Tをマイナスとして、表1にシミュレーション結果を示す。
11 第1配線層
11a 第1層
11b 第2層
12 第1絶縁層
12x 第1ビアホール
13 第2配線層
14 第2絶縁層
14x 第2ビアホール
15 第3配線層
16、46 第3絶縁層
16x、46x 第3ビアホール
17 第4配線層
17x 凹部
18、58 第4絶縁層
18x、22x、23x、58x 開口部
21 支持体
22、23 レジスト層
49 ガラスクロス
49a、49b ガラス繊維束
70 半導体パッケージ
71 半導体チップ
72 本体
73 電極パッド
74 バンプ
75 アンダーフィル樹脂
Claims (7)
- 複数の配線層と、同一組成の非感光性の絶縁性樹脂から構成された複数の絶縁層とが交互に積層され、
前記複数の絶縁層は、
配線基板の第1の主面を形成する第1の絶縁層と、
前記第1の主面の反対面である配線基板の第2の主面を形成する第2の絶縁層と、
前記第2の絶縁層の前記第2の主面とは反対側に隣接する第3の絶縁層と、を有し、
前記複数の配線層は、
前記第1の絶縁層に埋設され、表面が前記第1の絶縁層から露出する第1の電極パッドと、
前記第3の絶縁層の前記第2の絶縁層側に設けられ、前記第2の絶縁層の開口部から露出する第2の電極パッドと、を有し、
各絶縁層は、同一組成のフィラーを含有し、
前記各絶縁層の前記フィラーの含有量は、何れも55vol%以上65vol%以下の範囲にあり、
前記各絶縁層の熱膨張係数は、何れも12ppm/℃以上17ppm/℃以下の範囲にある配線基板。 - 前記第2の電極パッドのピッチは、前記第1の電極パッドのピッチよりも広く、
前記第2の絶縁層は、補強部材を備えている請求項1記載の配線基板。 - 前記第2の電極パッドのピッチは、前記第1の電極パッドのピッチよりも広く、
前記第3の絶縁層は、補強部材を備えている請求項1記載の配線基板。 - 前記補強部材は、繊維束を格子状に織り込んだ構造を有する請求項2又は3項記載の配線基板。
- 前記開口部の側壁の断面は凹型R形状であり、
前記開口部の底部に露出する前記第2の電極パッド部分に凹部が設けられている請求項1乃至3の何れか一項記載の配線基板。 - 前記凹部の側壁の断面は凹型R形状であり、
前記凹部の側壁の最外縁部は、前記開口部の側壁の最内縁部と一致している請求項5記載の配線基板。 - 前記開口部の側壁の面粗度は、前記第2の絶縁層の前記第2の主面側の面の面粗度よりも大きい請求項5又は6記載の配線基板。
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