DE69118928D1 - Halbleiterspeicheranordnung und Datenverarbeitungsanordnung und deren Verwendung - Google Patents

Halbleiterspeicheranordnung und Datenverarbeitungsanordnung und deren Verwendung

Info

Publication number
DE69118928D1
DE69118928D1 DE69118928T DE69118928T DE69118928D1 DE 69118928 D1 DE69118928 D1 DE 69118928D1 DE 69118928 T DE69118928 T DE 69118928T DE 69118928 T DE69118928 T DE 69118928T DE 69118928 D1 DE69118928 D1 DE 69118928D1
Authority
DE
Germany
Prior art keywords
data processing
semiconductor memory
processing device
memory device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69118928T
Other languages
English (en)
Other versions
DE69118928T2 (de
Inventor
Hiroshi Kayamoto
Masahiko Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE69118928D1 publication Critical patent/DE69118928D1/de
Application granted granted Critical
Publication of DE69118928T2 publication Critical patent/DE69118928T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69118928T 1990-01-24 1991-01-23 Halbleiterspeicheranordnung und Datenverarbeitungsanordnung und deren Verwendung Expired - Fee Related DE69118928T2 (de)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP1410390 1990-01-24
JP1410290 1990-01-24
JP1704290 1990-01-26
JP1704190 1990-01-26
JP13322690 1990-05-23
JP15941490 1990-06-18
JP240691A JP3228759B2 (ja) 1990-01-24 1991-01-14 半導体記憶装置及びデータ処理装置

Publications (2)

Publication Number Publication Date
DE69118928D1 true DE69118928D1 (de) 1996-05-30
DE69118928T2 DE69118928T2 (de) 1996-10-10

Family

ID=27563188

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118928T Expired - Fee Related DE69118928T2 (de) 1990-01-24 1991-01-23 Halbleiterspeicheranordnung und Datenverarbeitungsanordnung und deren Verwendung

Country Status (5)

Country Link
US (1) US5377138A (de)
EP (1) EP0439154B1 (de)
JP (1) JP3228759B2 (de)
KR (1) KR100215734B1 (de)
DE (1) DE69118928T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3459017B2 (ja) * 1993-02-22 2003-10-20 直 柴田 半導体装置
CN1124612C (zh) * 1995-07-21 2003-10-15 精工爱普生株式会社 半导体存储器装置及其字线升压方法
KR100565941B1 (ko) 1997-06-16 2006-03-30 가부시키가이샤 히타치세이사쿠쇼 반도체집적회로장치
KR100486222B1 (ko) * 1997-12-12 2005-08-01 삼성전자주식회사 반도체 메모리 장치의 워드 라인 풀업 드라이버 제어 회로
KR100268908B1 (ko) * 1998-04-22 2000-10-16 김영환 에스더블유엘(swl) 강유전체 메모리 장치 및 그 구동회로
JPH11328973A (ja) * 1998-05-20 1999-11-30 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US6545923B2 (en) * 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
JP4895439B2 (ja) * 2001-06-28 2012-03-14 ルネサスエレクトロニクス株式会社 スタティック型メモリ
KR100510484B1 (ko) * 2002-01-24 2005-08-26 삼성전자주식회사 워드라인 방전방법 및 이를 이용하는 반도체 메모리장치
US7936615B2 (en) 2007-02-27 2011-05-03 Samsung Electronics Co., Ltd. Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
JP6543133B2 (ja) * 2015-08-19 2019-07-10 株式会社東芝 電力供給装置及びその制御方法
CN109300499B (zh) * 2018-09-26 2021-08-24 京东方科技集团股份有限公司 数据存储电路及数据读写方法、阵列基板、显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189782A (en) * 1978-08-07 1980-02-19 Rca Corporation Memory organization
JPS57172587A (en) * 1981-04-17 1982-10-23 Hitachi Ltd Voltage boosting circuit of memory circuit
US4536859A (en) * 1981-08-31 1985-08-20 Sharp Kabushiki Kaisha Cross-coupled inverters static random access memory
JPS58169958A (ja) * 1982-03-31 1983-10-06 Fujitsu Ltd Ｍｉｓスタテイツク・ランダムアクセスメモリ
JPH077599B2 (ja) * 1984-05-25 1995-01-30 株式会社日立製作所 半導体集積回路装置
JPS61104394A (ja) * 1984-10-22 1986-05-22 Mitsubishi Electric Corp 半導体記憶装置
JPS6273490A (ja) * 1985-09-25 1987-04-04 Seiko Epson Corp ワ−ド線昇圧回路
JPH01166399A (ja) * 1987-12-23 1989-06-30 Toshiba Corp スタティック型ランダムアクセスメモリ
KR930002385B1 (en) * 1988-08-30 1993-03-29 Fujitsu Ltd Semiconductor memory circuit which is able to program
US5047979A (en) * 1990-06-15 1991-09-10 Integrated Device Technology, Inc. High density SRAM circuit with ratio independent memory cells

Also Published As

Publication number Publication date
KR910014948A (ko) 1991-08-31
JPH04212788A (ja) 1992-08-04
KR100215734B1 (ko) 1999-08-16
EP0439154A3 (en) 1992-08-19
EP0439154A2 (de) 1991-07-31
DE69118928T2 (de) 1996-10-10
US5377138A (en) 1994-12-27
EP0439154B1 (de) 1996-04-24
JP3228759B2 (ja) 2001-11-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee