CN1893053A - 插件结构及其制造方法、晶片级堆叠结构和封装结构 - Google Patents

插件结构及其制造方法、晶片级堆叠结构和封装结构 Download PDF

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CN1893053A
CN1893053A CNA2006100549476A CN200610054947A CN1893053A CN 1893053 A CN1893053 A CN 1893053A CN A2006100549476 A CNA2006100549476 A CN A2006100549476A CN 200610054947 A CN200610054947 A CN 200610054947A CN 1893053 A CN1893053 A CN 1893053A
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substrate
chip
plug
cavity
unit
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李康旭
金玖星
权容载
马金希
韩成一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1893053A publication Critical patent/CN1893053A/zh
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Abstract

本发明涉及一种制造芯片嵌入型插件的方法，其可以包括：在硅衬底上形成至少一个凹腔，形成多个穿入所述硅衬底的通路，提供具有多个输入/输出焊盘的集成电路芯片，以及形成连接于所述输入/输出焊盘和通路的重布线导体。使用所述插件，可以在晶片的层次上组成具有不同种类的芯片的堆叠结构。

Description

插件结构及其制造方法、晶片级堆叠结构和封装结构
技术领域
本发明涉及一种半导体封装结构和技术，尤其是涉及一种用于不管芯片尺寸而叠置不同种类集成电路芯片的结构和技术。
背景技术
随着数字网络信息时代的到来，电子产品在不断地迅速发展。例如，多媒体产品、数字家电产品和个人数字产品在迅速发展并将继续迅速发展下去。在如此快速发展的形势下，电子工业必须以有竞争力的成本制造出可靠、轻便、紧凑、高速、多功能和高性能的电子产品。***封装(system-in-package)(SIP)结构和技术已发展到能满足这样的需求。
***封装技术将不同种类的芯片组装在单一封装内，以改进电性能、缩小尺寸和减少制造成本。例如，在单一封装内包括300MHz CPU、1Gb NAND闪存(“与非”型闪存)及256Mb DRAM的***封装已面世。***封装为各种电子产品，例如游戏机、手机、数字式手提摄像机和个人数字助理，提供多种多样的多媒体功能，同时能缩小封装尺寸并减少在数据传输中可能出现的电磁波干扰现象。
参见图1，传统***封装10包括印刷电路板11(PCB)和多个不同种类的芯片12a、12b、12c及12d。用粘合剂15将芯片12a、12b及12c叠置于印刷电路板11的上表面，并用键合线(bonding wire)13将之与印刷电路板11电连接。位于印刷电路板11下表面的芯片12d以凸点14与印刷电路板11电连接。模制树脂16密封芯片12a、12b和12c以及键合线13。底层填充树脂17密封芯片12d和凸点14。外部连接端子，如焊球18，布于印刷电路板11的下表面。
在***封装10中，用键合线13和凸点14将不同种类的芯片12a至12d与印刷电路板11连接。键合线13和凸点14的使用会导致较长的连接，并可能限制***性能和增加封装尺寸。
参见图2，***封装20包括印刷电路板21和多个不同种类的芯片22a、22b和22c。叠置于印刷电路板21上表面的芯片22a、22b、22c利用通路(through via)23和重布线(rerouting line)24彼此电连接。嵌有无源器件的衬底25位于芯片22c和印刷电路板21之间，以补偿芯片22c和印刷电路板21之间的焊盘节距之差。嵌有无源器件的衬底25具有通路23和凸点26。该衬底25以凸点26与印刷电路板21相连接。印刷电路板21下表面上的焊球27为封装连接点。
***封装20具有利用通路23和重布线24直接互连的不同种类的芯片22a至22c。如此使用通路23和重布线24导致较短的互连，并且改进了***性能，同时减小了封装尺寸。但是，***封装20需要针对连接不同尺寸芯片22a、22b和22c时使用的通路23和重布线24的复杂布线。举例来说，如果较大的芯片22b将要叠置于较小的芯片22c上，则***封装20会具有不切实际或过于复杂的堆叠结构。
由于传统***封装10和20具有不同种类和不同尺寸的芯片，所以晶片级堆叠技术可能难以用在***封装10和20上。在这种情况下，***封装10和20就失去了利用晶片级堆叠技术来降低成本的机会。
发明内容
本发明的一示例性实施例提供一种用于不管芯片尺寸而叠置不同种类芯片的改进技术。
本发明的另一示例性实施例提供一种具有改进的***性能、改进的芯片互连和缩小的封装尺寸的***封装(SIP)。
本发明的又一个示例性实施例提供一种形成不同种类芯片的堆叠结构的晶片级技术。
根据本发明的一个示例性实施例，一种芯片嵌入型插件结构(chip-embedded interposer structure)包括：具有上表面和下表面的衬底；至少一个形成于所述衬底的所述上表面上的凹腔(cavity)；具有多个输入/输出(I/O)焊盘(pad)的集成电路芯片，该集成电路芯片至少部分位于所述凹腔内；多个穿入所述衬底的通路；以及连接于所述输入/输出焊盘和所述通路的重布线导体(rerouting conductor)。
所述衬底可以是晶片。所述凹腔可以形成于所述衬底的上表面并彼此充分隔开。所述通路可形成于所述凹腔之间的区域中。
所述凹腔的深度可小于所述衬底的厚度。所述凹腔的尺寸可大于所述集成电路芯片的尺寸。在所述凹腔和所述集成电路芯片之间可设置粘合材料。所述通路可以延伸到所述衬底的所述下表面。所述通路可以是充填入所述衬底的通孔中的金属材料。绝缘层可以设在所述通孔和金属材料之间。可在所述衬底的上表面和所述重布线导体之间设置保护层。
一种用于制造芯片嵌入型插件的方法可以包括：提供具有上表面和下表面的衬底；在所述衬底的所述上表面上形成多个通路；在所述衬底的所述上表面上形成至少一个凹腔；将集成电路芯片嵌入所述凹腔，所述芯片具有多个输入/输出焊盘；形成与所述输入/输出焊盘和所述通路连接的重布线导体；以及减薄该衬底从而暴露所述通路的一部分。
提供该衬底可以包括提供晶片形的硅衬底。形成所述通路可以包括在所述衬底中形成通孔并用金属材料充填所述通孔。形成通路可以进一步包括在所述通孔内壁上形成绝缘层。
形成所述凹腔可以包括：在部分所述衬底上形成掩模图案；借助所述掩模图案选择性蚀刻所述衬底的上表面；以及去除所述掩模图案。嵌入所述集成电路芯片可以包括将粘合材料涂覆于所述凹腔内，并将所述集成电路芯片与所述凹腔对准，从而将所述集成电路芯片设置在所述凹腔内。
形成所述重布线导体可以包括：将光致抗蚀剂涂覆于所述衬底上；构图该光致抗蚀剂，从而使输入/输出焊盘与所述通路相连；在图案化的光致抗蚀剂中形成金属材料；以及去除所述光致抗蚀剂。形成所述重布线导体可以进一步包括在所述衬底上涂覆保护层，并构图所述保护层从而暴露所述输入/输出焊盘和所述通路。减薄所述衬底可以包括：接触式工艺，其用于去除所述衬底的部分下表面，从而减小所述衬底的厚度；以及非接触式工艺，其用于去除所述衬底的部分下表面，从而暴露所述通路的一部分。
一种晶片级堆叠结构可以包括下插件和至少一个上插件。每一插件可以包括：具有第一表面和第二表面的衬底；至少一个形成于所述衬底的所述第一表面上的凹腔；具有多个输入/输出焊盘的集成电路芯片；多个穿入所述衬底的通路；以及连接至输入/输出焊盘和所述通路的重布线导体。所述上插件的所述集成电路芯片的尺寸可与所述下插件的集成电路芯片的尺寸不同，所述上插件的所述重布线导体可以连接至所述下插件的所述通路。
相应于所述上插件的所述集成电路芯片的所述凹腔相对于与所述下插件的所述集成电路芯片相应的所述凹腔可以具有不同的尺寸。所述下插件的所述通路可自所述衬底的第二表面伸出。所述晶片级堆叠结构可进一步包括设置在所述下插件下方的嵌有无源器件的衬底。
一种封装结构可以包括封装衬底、下插件和至少一个上插件。每一插件可以包括：具有第一表面和第二表面的衬底；至少一个形成于所述衬底的所述第一表面上的凹腔；有多个输入/输出焊盘的集成电路芯片；多个穿入所述衬底的通路；以及连接至输入/输出焊盘和所述通路的重布线导体。所述上插件的所述集成电路芯片相对于所述下插件的集成电路芯片可具有不同尺寸，所述上插件的所述重布线导体可与所述下插件的所述通路相连，所述下插件的所述重布线导体可以连接于所述封装衬底。
所述封装结构还可在所述封装衬底和所述下插件之间包括嵌有无源器件的衬底。
附图说明
参照以下结合附图给出的详细说明，本发明的示例性实施例将易于被理解，其中相同附图标记表示相同的结构元件。
图1(现有技术)是传统***封装的一示例的剖面图。
图2(现有技术)是传统***封装的另一示例的剖面图。
图3A至3F是根据本发明一示例性实施例的芯片嵌入型插件及相关制造方法的剖面图。
图4A至4C是根据本发明一示例性实施例的利用所述插件而包括不同种类芯片的晶片级堆叠结构及相关制造方法的剖面图。
图5是根据本发明一示例性实施例的使用所述插件的封装结构的剖面图。
应当注意，这些图是要说明本发明示例性实施例的方法和器件的一般特性。但是，这些图未按比例尺绘制，且可能未精确反映任何所给实施例的特性，且不应被解释为定义或限制本发明范围内示例性实施例的数值范围或性质。各种各样的实施例中示出的元件的空间关系和相对尺寸可以缩小、放大或重新排列，从而提高针对相应说明的图的清晰性。因此，这些图不应当被解释为准确反映按本发明示例性实施例制造的实际器件可能包含的相应结构元件的相对尺寸和位置。为了图示说明的简单和清楚，一些元件的尺寸相对于其它元件被夸大。
具体实施方式
下面，将参照附图更充分地说明本发明的示例性、非限定实施例。但本发明可以以许多不同的形式加以实施，而且不应被解释为限于此处提及的特定示例性实施例。此外，所公开的实施例给出了详尽且完全的公开，且将把本发明传达给本领域技术人员。因此，本发明的原理和特征可用在各种各样的实施例中而不脱离本发明的范围。
公知结构和工艺不被详细说明或示出，从而避免使本发明实施例不清楚。相同的附图标记用于各附图的相同和相应的部件。
图3A至3F是根据本发明一示例性实施例的芯片嵌入型插件100及相关制造方法的剖面图。
参看3A，如硅衬底110的半导体衬底，可以是具有上表面111和下表面112的晶片形。虽然此示例性实施例示出了晶片形的硅衬底110，但在这点上，衬底110的材料和形状不必受限。
硅衬底110，例如可以在通常的晶片制造工艺中使用的硅衬底，可以是普通硅片，一开始其中未形成有特定的附加元件或结构。因此，硅衬底110的直径和厚度可以与通常晶片的直径和厚度相似。例如，硅衬底110的直径可以是8英寸或12英寸，厚度可以为约700微米至约800微米(μm)。
参看图3B，多个通路(或通孔)120可在硅衬底110内形成。通路120可以从硅衬底110的上表面111延伸至预定深度，但这里不必延伸到硅衬底110的下表面112。考虑到下面更充分讨论的芯片堆叠上的互连，通路120的布置可以基于最大芯片的尺寸。
通孔121可以用激光工艺或干蚀刻工艺在硅衬底110内形成。如氮化硅的绝缘层122可以形成于通孔121的内壁上。绝缘层122使通路120相对于硅衬底110电隔离，由此防止电流泄露。通孔121可以借助电镀工艺以金属材料填充，从而完成通路120，该金属材料例如是铜、金或钨。
参看图3C，可以在硅衬底110中形成多个凹腔130。凹腔130可以分布于硅衬底110的上表面111上并彼此适当隔开。凹腔130的尺寸可以大于集成电路芯片的尺寸。凹腔形成位置可以与通路形成位置不同。例如，凹腔130可以设置于通路120之间的区域内。
除了凹腔形成位置外，可以在硅衬底110的上表面111上形成掩模图案(未示出)。掩模图案可以由抗蚀剂材料或金属层构成。硅衬底110的上表面111可以借助掩模图案被选择性蚀刻。该选择性蚀刻工艺可以使用等离子体蚀刻法。该掩模图案可以被去除。
参看图3D，具有多个输入/输出焊盘142的集成电路芯片140可以嵌到凹腔130中。
粘合材料143可施加于凹腔130。粘合材料143可包括液体、糊和带型。集成电路芯片140可以与凹腔130对准，从而位于凹腔130中。集成电路芯片140可以利用粘合材料143与硅衬底110接合。集成电路芯片140的高度可以与硅衬底110的上表面111齐平，或由于粘合材料143的缘故而高于硅衬底110的上表面111。
参看图3E，重布线导体150可被形成，从而将输入/输出焊盘142与通路120连接。
具体地，保护层151可形成在硅衬底110上，并被构图从而暴露集成电路芯片140的输入/输出焊盘142和硅衬底110的通路120。例如，保护层151可以由光敏聚酰亚胺材料形成。可以使用溅射工艺在硅衬底110上形成晶种金属层(未示出)。光致抗蚀剂可涂覆于硅衬底110上，并被构图成连接输入/输出焊盘142和通路120。可使用电镀工艺将例如铜的金属材料形成于光致抗蚀剂图案中。随后，可实施光致抗蚀剂去除工艺和晶种金属层蚀刻工艺，从而完成重布线导体150。虽然此示例性实施例示出了保护层151，但在形成重布线导体150时该保护层151可以是可省略的元件。
参看图3F，硅衬底110可被减薄。硅衬底110的减薄可以减小硅衬底110的厚度，并暴露通路120的一部分。例如，如果减薄后的硅衬底110的厚度为约100微米，则凹腔130的深度可以为约50微米。
硅衬底110的减薄可包括接触式工艺和非接触式工艺。接触式工艺可以去除硅衬底110的下表面112的一部分，从而减小硅衬底110的厚度。非接触式工艺可以去除硅衬底110的下表面112的再一部分，从而暴露通路120的一部分。接触式工艺可以包括机械磨削工艺和化学机械抛光工艺。非接触式工艺可以包括旋转湿蚀刻工艺和干蚀刻工艺。于是，可完成其中嵌入有芯片的插件100的制造。
所得插件100可以包括具有上表面111和下表面112的硅衬底110、至少一个形成于硅衬底110的上表面111的凹腔130、具有多个输入/输出焊盘142的集成电路芯片140、穿入硅衬底110的多个通路120、连接至输入/输出焊盘142和通路120的重布线导体150。
图4A至4C是根据本发明示例性实施例的晶片级堆叠结构200及相关制造方法的剖面图，该晶片级堆叠结构借助插件而具有不同种类的芯片。
参看图4A，插件100a、100b和100c各自分别包括嵌在其内的芯片140a、140b和140c。芯片140a、140b和140c可以是具有不同尺寸的不同种类芯片，但将供互连成***封装(SIP)使用。插件100a、100b和100c具有与插件100相同的结构和制造方法，且以相对于先前图示的配置颠倒的配置示出。因此，将略去进一步的说明，例如与插件100一样的说明。
集成电路芯片140a、140b和140c可以具有不同的尺寸，且相应的凹腔130可以具有不同的尺寸。考虑到芯片堆叠时的互连，通路120的布置可以基于最大芯片140a的尺寸来设计。一旦凹腔130的尺寸和通路120的布置被确定，相应地重布线导体150的布置可被确定。
参看图4B，插件100a、100b和100c可垂直叠置，从而形成晶片级堆叠结构200。以下，插件100a可被称为最上层插件，插件100b可被称为中间插件，插件100c可被称为最下层插件。插件100a、100b和100c可以使用例如热压接合法(thermo compression bonding method)彼此机械和电连接。例如，最下层插件100c的通路120可以与中间插件100b的重布线导体150连接。此时，从硅衬底的下表面伸出的通路120可允许通路120与重布线导体150的更容易且更可靠的连接。
为了形成***封装，晶片级堆叠结构200可以与封装衬底相接。此时，最下层插件100c和封装衬底之间的连接焊盘的大节距可能导致差的连接。为了解决该节距问题，晶片级堆叠结构200还可包括衬底210，衬底210具有嵌在其中的无源器件(未示出)。嵌有无源器件的衬底210可以具有通路211和凸点212。在本发明其它实施例中，嵌有无源器件的衬底210不必包括在晶片级堆叠结构200中。
参看图4C，所得晶片级堆叠结构200可以沿划线(scribe line)220分为单独的堆叠结构。该切片工艺可以按与通常晶片切割工艺相似的方式使用切割机或激光。由此，可以由一个晶片级堆叠结构200获得多个封装结构，如封装结构300。
图5是根据本发明一示例性实施例的使用此处所述插件技术的封装结构300的剖面图。
参看图5，作为***封装的封装300可以包括封装衬底230和分别具有不同种类芯片140a、140b和140c的插件100a、100b和100c。芯片140a、140b和140c可以分别包括例如DRAM、NAND闪存和CPU的电路。插件100a、100b和100c中的每一个可以具有用于容放芯片140a、140b和140c的凹腔130、形成于凹腔130附近的通路120和与通路120相连的重布线导体150。芯片140a、140b和140c可以利用通路120和重布线导体150彼此电连接。在最下层插件100c和封装衬底230之间可设置衬底210，该衬底具有嵌在其中的无源器件。外部连接端子，例如焊球240，可以形成于封装衬底230的下表面。
使用通路120和重布线导体150的互连可获得改善的***性能和减小的封装尺寸。通路120不必形成于芯片140a、140b和140c中，而是形成于插件100a、100b和100c中。这可导致通路120和重布线导体150的限制更少的布图，从而利于芯片之间的所需互连。插件100a、100b和100c的统一尺寸可导致稳定的***封装(SIP)结构。
根据本发明的示例性实施例，芯片嵌入型插件允许叠放不同种类的芯片，而不管芯片尺寸。
芯片嵌入型插件提供了采用通路和重布线导体的互连，从而改善了***性能并减小了封装尺寸。
具有形成在其中的通路的芯片嵌入型插件提供了通路和重布线导体的限制更少的布局，从而利于芯片之间的所需互连。
与其它芯片嵌入型插件相比，尺寸较统一的芯片嵌入型插件提供了如此形成的***封装的结构稳定性。
晶片形式的芯片嵌入型插件在晶片层次上组成了堆叠结构，从而减少了制造成本。
虽然以上已经详细介绍了本发明的示例性、非限制实施例，但应理解，对本领域技术人员而言显而易见的、对此处教导的基本发明概念的诸多改变和/或更改仍将落入如所附权利要求所述的本发明的示例性实施例的主旨和范围内。
本申请要求2005年7月8日提交的第2005-61573号韩国专利申请的优先权，其全部内容在此参考引用。

Claims (30)

1.一种芯片嵌入型插件结构，包括：
具有上表面和下表面的衬底；
至少一个形成于所述衬底的所述上表面的凹腔；
集成电路芯片，其具有多个输入/输出焊盘，且至少部分位于该至少一个凹腔内；
多个穿入所述衬底的通路；以及
连接于所述输入/输出焊盘和所述通路的重布线导体。
2.如权利要求1所述的结构，其中所述衬底是硅衬底。
3.如权利要求1所述的结构，其中所述衬底是晶片。
4.如权利要求1所述的结构，其中所述衬底的所述上表面中的该至少一个凹腔相对于相邻凹腔以隔开的关系定位。
5.如权利要求4所述的结构，其中至少一些所述通路位于该至少一个凹腔和该相邻凹腔之间。
6.如权利要求1所述的结构，其中该至少一个凹腔的深度小于所述衬底的厚度。
7.如权利要求1所述的结构，其中该至少一个凹腔的尺寸大于所述集成电路芯片的尺寸。
8.如权利要求7所述的结构，其中当所述集成电路芯片位于该至少一个凹腔中时，粘合剂位于该至少一个凹腔和所述集成电路芯片之间。
9.如权利要求1所述的结构，其中所述通路延伸到所述衬底的所述下表面。
10.如权利要求1所述的结构，其中所述通路中的至少一个包括充填入所述衬底的通孔中的金属材料。
11.如权利要求10所述的结构，包括在所述通孔和所述金属材料之间的绝缘层。
12.如权利要求1所述的结构，包括在所述衬底的所述上表面和所述重布线导体之间的保护层。
13.一种制造芯片嵌入型插件的方法，所述方法包括；
提供具有上表面和下表面的衬底；
在所述衬底的所述上表面形成多个通路；
在所述衬底的所述上表面形成至少一个凹腔；
将集成电路芯片嵌入该至少一个凹腔中，所述芯片具有多个输入/输出焊盘；
形成连接于所述输入/输出焊盘和连接于所述通路的重布线导体；以及
减薄所述衬底，从而在所述衬底的所述下表面暴露所述通路的一部分。
14.如权利要求13所述的方法，其中提供衬底包括提供硅衬底。
15.如权利要求13所述的方法，其中提供所述衬底包括提供晶片形式的衬底。
16.如权利要求13所述的方法，其中形成多个通路包括在所述衬底中形成相应的多个通孔并用金属材料充填所述多个通孔。
17.如权利要求16所述的方法，其中形成多个通路还包括在所述多个通孔的每一个的内壁上形成绝缘层。
18.如权利要求13所述的方法，其中形成至少一个凹腔包括在部分所述衬底上形成掩模图案，利用所述掩模图案选择性蚀刻所述衬底的所述上表面，以及去除所述掩模图案。
19.如权利要求13所述的方法，其中嵌入集成电路芯片包括于所述凹腔内涂覆粘合材料、以及将所述集成电路芯片相对于所述凹腔对准，从而将所述集成电路芯片至少部分地置于所述凹腔中。
20.如权利要求13所述的方法，其中形成所述重布线导体包括将光致抗蚀剂涂覆于所述衬底上、构图该光致抗蚀剂从而将该输入/输出焊盘与所述通路相连、在图案化的光致抗蚀剂中形成金属材料、以及去除所述光致抗蚀剂。
21.如权利要求20所述的方法，其中形成所述重布线导体还包括在所述衬底上涂覆保护层并构图所述保护层，从而露出所述输入/输出焊盘和所述通路。
22.如权利要求13所述的方法，其中减薄所述衬底包括以下工艺中的至少一种：接触式工艺，其去除所述衬底的所述下表面的一部分，从而减小所述衬底的所述厚度；以及非接触式工艺，其去除所述衬底的所述下表面的一部分，从而暴露所述通路的一部分。
23.一种晶片级堆叠结构，包括：
下插件；以及
至少一个上插件，
每一插件包括：
具有第一表面和第二表面的衬底；
至少一个形成于所述衬底的所述第一表面的凹腔；
具有多个输入/输出焊盘的集成电路芯片；
多个穿入所述衬底的通路；以及
连接于所述输入/输出焊盘和所述通路的重布线导体，
其中，所述上插件的所述集成电路芯片相对于所述下插件的所述集成电路芯片具有不同尺寸，所述上插件的所述重布线导体可与所述下插件的所述通路相连。
24.如权利要求23所述的结构，其中所述衬底是硅衬底。
25.如权利要求23所述的结构，其中与所述上插件的所述集成电路芯片相应的所述凹腔相对于与所述下插件的所述集成电路芯片相应的所述凹腔具有不同尺寸。
26.如权利要求23所述的结构，其中所述下插件的所述通路延伸到相应衬底的所述第二表面。
27.如权利要求23所述的结构，还包括设置在所述下插件下方的嵌有无源器件的衬底。
28.一种封装结构，包括：
封装衬底；
下插件；以及
至少一个上插件，
每一插件包括：
具有第一表面和第二表面的衬底；
至少一个形成于所述衬底的所述第一表面的凹腔；
集成电路芯片，其具有多个输入/输出焊盘，且相对于至少一个所述凹腔定位；
多个穿入所述衬底的通路；以及
连接于所述输入/输出焊盘和所述通路的重布线导体，
其中，所述上插件的所述集成电路芯片相对于所述下插件的所述集成电路芯片具有不同尺寸，所述上插件的所述重布线导体与所述下插件的所述通路相连，所述下插件的所述重布线导体连接于所述封装衬底。
29.如权利要求28所述的结构，其中每个衬底包括硅衬底。
30.如权利要求28所述的结构，还包括所述封装衬底和所述下插件之间的嵌有无源器件的衬底。
CNA2006100549476A 2005-07-08 2006-02-27 插件结构及其制造方法、晶片级堆叠结构和封装结构 Pending CN1893053A (zh)

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