CN103474361B - 一种嵌入式有源埋入功能基板的封装工艺及封装结构 - Google Patents

一种嵌入式有源埋入功能基板的封装工艺及封装结构 Download PDF

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Publication number
CN103474361B
CN103474361B CN201310457111.0A CN201310457111A CN103474361B CN 103474361 B CN103474361 B CN 103474361B CN 201310457111 A CN201310457111 A CN 201310457111A CN 103474361 B CN103474361 B CN 103474361B
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layer
metal
chip
package assembling
hole
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CN103474361A (zh
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郭学平
谢慧琴
于中尧
刘丰满
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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National Center for Advanced Packaging Co Ltd
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Priority to US14/311,811 priority patent/US9583418B2/en
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Abstract

本发明公开了一种嵌入式有源埋入功能基板的封装工艺及封装结构，所述封装工艺其包括，形成次级封装组件；自所述次级封装组件的第一主面和第二主面对应所述凸点进行盲孔开窗口并钻盲孔至所述凸点处；在所述次级封装组件上开设通孔，所述通孔贯穿所述次级封装组件；在所述盲孔以及所述通孔内进行化金属作为种子层，然后进行填孔电镀；进行第一外层线路层的制作。本发明解决了以往埋入结构中大功率器件的热管理性能问题，解决了器件的散热，本发明利用基于有机基板工艺进行了其散热结构的设计，能够很好的满足其散热的性能。

Description

一种嵌入式有源埋入功能基板的封装工艺及封装结构
技术领域
本发明涉及半导体封装领域，尤其涉及一种嵌入式有源埋入功能基板的封装工艺及其封装结构。
背景技术
随着信息技术的不断发展，手机和各种电子产品越来越向轻薄短小的方向发展，手机电脑的性能越来越高，体积变得越来越小，对芯片和器件的集成度要求也越来越高。随着大规模集成电路的不断发展和革新，线宽已经接近22纳米，集成度达到空前的水平。对于技术和设备的要求也达到了一个全新的高度。线宽进一步变小的难度越来越大，技术和设备的加工能力的提升难度更大，技术和设备水平的发展趋于减缓。
这种情况下，3D高密度封装受产业界广泛的重视，一个器件中的芯片不再是一个，而是多个，并且不再是只在一层排列，而是堆叠成三维高密度微组装芯片。芯片三维堆叠有效减少了器件的三维尺寸，芯片间的堆叠方式也在不断的改进。从FLIPCHIP到硅基TSV（ThroughSiliconVia）通孔互联技术，器件的三维尺寸变得越来越小。封装工艺也从原来的键合、贴片、塑封，演变成引入前段工艺的RDL、FlipChip、晶圆键合、TSV等等关键工艺技术，使得更芯片密度更大、尺寸更小的封装结构不断涌现。
现有有机基板的有源芯片的埋入技术中所存在限制其大规模量产的关键问题在于，其埋入芯片的良率以及散热可靠性的问题，尤其是对于大功率的器件来说热管理性能制约了其有机基板有源芯片埋入的应用。
发明内容
本部分的目的在于概述本发明的实施例的一些方面以及简要介绍一些较佳实施例。在本部分以及本申请的说明书摘要和发明名称中可能会做些简化或省略以避免使本部分、说明书摘要和发明名称的目的模糊，而这种简化或省略不能用于限制本发明的范围。
鉴于上述和/或现有半导体封装中存在的问题，提出了本发明。
因此，本发明的目的是提出一种嵌入式有源埋入功能基板的封装工艺，解决目前埋入芯片的良率以及散热可靠性的问题。
为解决上述技术问题，本发明提供了如下技术方案：一种嵌入式有源埋入功能基板的封装工艺，包括，提供两个初级封装组件，每个初级封装组件中有机基板的金属槽内封装有芯片,所述初级封装组件具有第一主面和与第一主面相对的第二主面，所述芯片的主侧与所述第二主面同向，且其上设置有连接垫片；将两个初级封装组件的两个第一主面相对的压合形成次级封装组件，压合后两个初级封装组件中的两个有机基板夹持封装于所述有机基板的金属槽内的芯片；自所述次级封装组件的两个外侧面对应所述芯片上的连接垫片进行盲孔开窗口并开设盲孔至所述芯片上的连接垫片处；在所述次级封装组件上开设通孔，所述通孔贯穿所述次级封装组件；对所述盲孔、所述通孔以及次级封装组件的两个外侧面进行化金属作为种子层，然后进行填孔电镀；进行第一外层线路层的制作。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：所述提供两个初级封装组件，其中每个初级封装组件的制作工艺包括，提供一有机基板并在有机基板的一侧形成金属槽，所述金属槽的尺寸与待封装的芯片的尺寸相适应；将所述芯片的主侧贴装于所述金属槽内；在与所述芯片的主侧相对的另一侧进行金属制作以封装所述芯片；进行区域金属蚀刻，所述区域金属蚀刻是对有电气连通的通孔的位置的金属进行蚀刻。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：在进行第一外层线路层的制作后，还包括，在所述第一外层线路层的两个表面进行外层线路介质层的压合；互连所述外层线路介质层上的介质层盲孔并进行第二外层线路层的制作。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：在进行第二外层线路层的制作后，还包括，在所述第二外层线路层进行外层阻焊层的制作；进行后续的芯片的组装或植球。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：所述有机基板包括有机层以及夹持所述有机层的分别位于所述有机层的两个金属层，在有机基板第一主面形成金属槽之前，其还包括，对所述有机基板的两个金属层进行增金属工艺，使得增金属后所述有机基板的两个金属层增厚。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：所述将两个初级封装组件的两个第一主面相对的压合形成次级封装组件后，其还包括，将所述次级封装组件的两个外侧面上的金属进行减薄。
作为本发明所述嵌入式有源埋入功能基板的封装工艺的一种优选方案，其中：所述在所述次级封装组件上开设通孔后，其还包括，蚀刻所述次级封装组件的两个外侧面上的金属。
本发明的另目的是提供一种新型封装结构，该封装结构解决了在有机基板有源器件中的热管理的散热问题，另外还可以使所埋入器件之间进行电磁屏蔽。
为解决上述技术问题，本发明提供了如下技术方案：一种封装结构，包括，次级封装组件，所述次级封装组件包括两个相对压合的初级封装组件，所述初级封装组件包括有机基板以及封装于所述有机基板的金属槽内的芯片；盲孔，自所述次级封装组件的两个外侧面对应所述芯片上的连接垫片进行设置且所述盲孔内填充有第一电镀介质；通孔，所述通孔贯穿所述次级封装组件且所述通孔内填充有第一电镀介质；第一外层线路层，所述第一外层线路层能够进行后续的芯片的组装或植球。
作为本发明所述封装结构的一种优选方案，其中：该封装结构还包括，外层线路介质层，所述外层线路介质层压合在所述第一外层线路层的两个表面上；介质层盲孔，所述介质层盲孔设置于所述外层线路介质层且所述介质层盲孔内填充有第二电镀介质；第二外层线路层，所述第二外层线路层能够进行后续的芯片的组装或植球。
作为本发明所述封装结构的一种优选方案，其中：该封装结构还包括，阻焊层，所述阻焊层设置于所述第二外层线路层上。
本发明相对于现有技术而言主要优势有以下几点：
（1）有机基板工艺成熟和材料工艺成本低适合于大规模化量产的需要，本发明的实施工艺全部基于有机基板的工艺方法和材料开展的，能够满足功能基板的可靠性等要求；
（2）本发明的主要优势在于解决了以往埋入结构中大功率器件的热管理性能问题，解决了器件的散热，本发明利用基于有机基板工艺进行了其散热结构的设计，能够很好的满足其散热的性能；
（3）本发明提供的封装结构中包含有两层的多芯片的埋入，适用于***级集成封装，满足了其现在封装***中的小型化集成化要求，另外在芯片的之间有金属屏蔽层，减少了其芯片之间的电磁干扰提高***模块的电磁兼容的性能。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1～图11为本发明所述一种嵌入式有源埋入功能基板的封装工艺的各步骤得到的产品的示意图；
图12为本发明中的嵌入式有源埋入功能基板的封装工艺在一个实施方式中的流程示意图；
图13为本发明中的嵌入式有源埋入功能基板的封装工艺在另一个实施方式中的流程示意图；
图14为本发明中的嵌入式有源埋入功能基板的封装工艺在再一个实施方式中的流程示意图；
同时，其中，
图7为本发明所述嵌入式有源埋入功能基板的封装工艺制作的封装结构的第一实施例的剖面示意图；
图9为本发明所述嵌入式有源埋入功能基板的封装工艺制作的封装结构的第二实施例的剖面示意图；
图10为本发明所述嵌入式有源埋入功能基板的封装工艺制作的封装结构的第三实施例的剖面示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
另，本发明中提出的术语“第一主面”、“第二主面”、“主侧”或“一侧”以及“表面”等指示方位或位置关系为基于附图所示的方位或位置关系，基于此种理解，若针对特定部件或组件“面”或“侧”的减薄或增厚，亦可以指代基于此特定部件或组件“面”或“侧”的延伸，而不是要求本发明必须以特定的方位构造和操作，因此不能理解为对本发明的限制。
本发明一个实施方式中提出了一种嵌入式有源埋入功能基板的封装工艺700，请参考图12所示，该封装工艺包括如下步骤：
步骤710，如图1所示，并参见图1a，提供两个初级封装组件，每个初级封装组件中有机基板101的金属槽103内封装有芯片102,所述初级封装组件具有第一主面S1和与第一主面S1相对的第二主面S2，所述芯片102的主侧M与所述第二主面S2同向，且其上设置有连接垫片102a。
具体的，参见图1a～图1d以及图1，所述初级封装组件的形成方法包括：
步骤一，结合图1a和图1b，提供一有机基板101，并在有机基板101的一侧形成金属槽103，所述金属槽103的尺寸与待封装的芯片102的尺寸相适应，即金属槽103的长宽高与芯片102的长宽高相匹配。
需要指出的是，所述有机基板101包括了有机层以及夹持所述有机层的分别位于所述有机层的两个金属层。在这一实施方式中，在有机基板101的一侧进行图像曝光，并进行金属层金属的蚀刻，制作出贴装芯片102以及电气连接过孔的图形，主要是在贴装芯片102以及有电气过孔的位置将铜蚀刻干净，在制作过程中要对用于曝光的资料进行处理，并根据工艺条件进行图像的补偿。这一实施方式是基于有机基板101上的金属层厚度足够，例如，所述金属层的厚度大于待封装的芯片102厚度和贴片胶（用以贴装芯片102）的厚度之和，那么，如此就可以直接在所述有机基板101的一侧形成金属槽103，以安装芯片102。
步骤二，如图1b所示，将所述芯片102的主侧M贴装于所述金属槽103内。具体为，用贴片胶（填孔胶）进行芯片102的主侧M上设置的连接垫片102a的贴装，并且要求贴片胶充满芯片102的底部以及芯片102的边缘；另外为了能够后续的有机基板101工艺过程进行化金属在芯片102背面进行处理，一方面可以进行金属化处理，金属化的材料可以为金、铜、镍等能够化铜的金属，或者是进行非金属化处理，可以在其芯片102的背面进行旋涂胶。
步骤三，参见图1c，在与所述芯片102的主侧M相对的另一侧进行金属制作以封装所述芯片102。具体为，在芯片102的主侧M对应的一面表面进行化金属，化金属层一般在1μm之下，然后进行整个面的电镀，要求电镀后的金属层厚大于50μm。
步骤四，如图1d所示，进行区域金属蚀刻E，所述区域金属蚀刻E是对有电气连通的通孔的位置的金属进行蚀刻。区域金属蚀刻E要求将对有电气连通的通孔的位置的金属蚀刻干净，得到初级封装组件。对比图1c与图1d可知，图1d在有电气连通的通孔的位置进行了区域金属蚀刻E，将此位置的金属蚀刻掉。
步骤720，如图2所示，将两个初级封装组件的两个第一主面S1相对的压合形成次级封装组件100，压合后两个初级封装组件中的两个有机基板101夹持封装于所述有机基板101的金属槽103内的芯片102。
具体为，将同样的初级封装组件应用半固化片或ABF（AjinomotoBondFilm）等进行压合。其中，若应用半固化片比如PP（Prepreg，是多层板生产中的主要材料之一，主要由树脂和增强材料组成）时候，要先在对应芯片102贴装的位置进行机械开窗，然后再进行高温压合；假如采用的为ABF，则需要足够厚的ABF直接进行真空层压。
上述步骤710以及步骤720实现了在一个实施方式中形成次级封装组件100的方式。
在另一个实施方式中，形成次级封装组件100的方式可以为：
第一步，如图2a所示，提供一有机基板101，若有机基板101上的金属层厚度不足以形成金属槽103以封装所述芯片102，那么，如图2a所示，本实施例中所采用的有机基板101可以为双面覆铜芯（Core）板或者是半固化片和铜箔压合形成的双面覆铜板。然后，参见图2b，图2b为对双面覆铜芯（Core）板或者是半固化片和铜箔压合形成的双面覆铜板进行双面的全板电镀，电镀的厚度大于待封装的芯片102厚度，并且要求具有比较好的均匀性。在采用点胶倒装贴芯片的方式进行芯片的封装时，电镀的厚度大于芯片厚度和贴片胶的厚度之和，即要求其电镀的金属的厚度与芯片102与贴片胶的厚度和相近，精度误差控制在20μm以下。如图2a和图2b所示，图2b相对于图2a，所述有机基板101的金属层进行增金属工艺后，覆金属层明显加厚。
第二步，如图2c所示，在增金属工艺后的有机基板101的一侧形成金属槽103，所述金属槽103的尺寸与待封装的芯片102的尺寸相适应，即金属槽103的长宽高与芯片102的长宽高相匹配。
第三步，如图2d所示，将所述芯片102的主侧M贴装于所述金属槽103内。即用贴片胶（填孔胶）进行芯片102的主侧M上设置的连接垫片102a的贴装，并且要求贴片胶充满芯片102的底部以及芯片102的边缘。
第四步，如图2e所示，在与所述芯片102的主侧M相对的另一侧进行金属制作以封装所述芯片102。
第五步，如图2f所示，进行区域金属蚀刻E，所述区域金属蚀刻E是对有电气连通的通孔的位置的金属进行蚀刻，以形成一侧金属层较厚的初级封装组件，所述一侧金属层较厚的初级封装组件具有第一主面S1和与第一主面S1相对的第二主面S2。
第六步，如图2g所示，将两个一侧金属层较厚的初级封装组件的两个第一主面S1相对的压合形成两个外侧较厚的次级封装组件。
第七步，参见图2以及图2g，将所述两个外侧较厚的次级封装组件的两个外侧面（即第二主面S2）上的金属进行减薄，以形成最终适合后续工序的次级封装组件100。
具体为，将对应的芯片102背面的外层金属进行蚀刻减薄至2.5μm～3.5μm，要求对金属的厚度的一直性比较高，主要为了能够更好的控制激光钻孔的参数。
步骤730，如图3所示，并参见图4，自所述次级封装组,100的两个外侧面对应所述芯片102上的连接垫片102a进行盲孔开窗口201并开设盲孔202至所述芯片102上的连接垫片102a处。具体为，进行激光开孔的开窗口201，主要是为了能够更好的对激光盲孔202进行控制，达到比较好的一致性，通过激光钻孔机在对应的开窗口201的位置进行盲孔202的制作，要求盲孔202小于芯片102上连接垫片102a的尺寸，并且能够将精度控制在盲孔202落在连接垫片102a上的要求的范围之内。
步骤740，如图5所示，在所述次级封装组件100上开设通孔301，所述通孔301贯穿所述次级封装组件100。具体为，应用机械钻孔进行电气连通的通孔301以及用于散热的散热通孔301的制作，一方面要求电气连通的通孔301制作在上面图形制作的预留空间内，另一方面要求散热通孔301要求与埋入芯片102内部的金属层进行连通更好的起到散热的作用。
步骤750，如图6a和图6b所示，对所述盲孔202、所述通孔301以及次级封装组件100的两个外侧面进行化金属作为种子层，然后进行填孔电镀。
这一工艺过程包括两步：
第一步，刻蚀掉所述次级封装组件100上的金属层。也即在所述盲孔202以及所述通孔301内进行化金属作为种子层，如图6a所示。
第二步，参见图6a和图6b，将所述盲孔202以及所述通孔301内非导电的基材上，通过金属化处理来完成双面或多层印制线路板各层间导线的连接，即通过PTH（platedthroughhole，镀通孔工艺）进行填孔电镀。填孔电镀后，盲孔202以及通孔301内皆填充有第一电镀介质401。即对盲孔202、通孔301以及两个外侧表面进行电镀，对盲孔202以及通孔301孔壁进行化铜作为电镀的种子层，要求孔内能够有比较均匀的铜层。
步骤760，如图7所示，进行第一外层线路层的制作。形成能够进行后续的芯片的组装或植球的第一外层线路层。具体为，通过曝光显影蚀刻进行第一外层线路层的制作。
本发明的另一个实施方式中提出了另一种嵌入式有源埋入功能基板的封装工艺800，请参考图13所示，该封装工艺除了包括了上一实施方式封装工艺700外还包括如下步骤：
步骤810，如图8所示，在所述第一外层线路层的两个表面进行外层线路介质层501的压合。具体为，应用半固化片或ABF（AjinomotoBondFilm）板等进行压合。
步骤820，如图9所示，互连所述外层线路介质层上的介质层盲孔并进行第二外层线路层的制作。即进行第二外层线路的激光介质层盲孔、化金属以及图形电镀等工艺步骤进行第二外层线路的制作。具体为，先通过激光钻外层线路介质层501的介质层盲孔。所述介质层盲孔与所述盲孔202内的电镀介质401相连通；然后进行外层线路介质层501的介质层盲孔填孔电镀。填孔电镀后，介质层盲孔内以及外层线路介质层501表面上皆填充有第二电镀介质；最后，进行第二外层线路层的制作。形成能够进行后续的芯片的组装或植球的第二外层线路层。
本发明的另一个实施方式中提出了另一种嵌入式有源埋入功能基板的封装工艺900，请参考图14所示，该封装工艺除了包括了上一实施方式封装工艺700以及封装工艺800外还包括如下步骤：
步骤910，如图10所示，在所述第二外层线路层进行外层阻焊层601的制作。具体为，进行外层阻焊层601绿油的制作，该绿油可以为油墨也可以为干膜型的绿油阻焊。
步骤920，如图11所示，进行后续的芯片的组装或植球。即进行微组装，以上述步骤制作的功能基板作为封装基板进行后续的芯片的组装或植球等。
第一实施例，通过封装工艺700制作的封装结构，参见图7并结合图1～图6a和图6b，该封装结构包括了次级封装组件100、盲孔202、通孔301以及第一外层线路层，而次级封装组件100包括两个相对压合的初级封装组件，所述初级封装组件包括有机基板101以及封装于所述有机基板101的金属槽103内的芯片102；所述盲孔202自所述次级封装组件的两个外侧面对应所述芯片102上的连接垫片102a进行设置且所述盲孔202内填充有第一电镀介质401；所述通孔301贯穿所述次级封装组件100且所述通孔301内填充有第一电镀介质401，同时第一电镀介质401覆盖所述次级封装组件100的两个外侧面；所述第一外层线路层能够进行后续的芯片的组装或植球。
第二实施例，通过封装工艺700和封装工艺800制作的封装结构，参见图9并结合图1～图8，该封装结构除了包括根据封装工艺700制作的相应封装结构外，还包括，外层线路介质层501、介质层盲孔以及第二外层线路层，所述外层线路介质层501压合在所述第一外层线路层的两个表面上；所述介质层盲孔设置于所述外层线路介质层501且所述介质层盲孔内以及外层线路介质层501表面上皆填充有第二电镀介质；所述第二外层线路层能够进行后续的芯片的组装或植球。
第三实施例，通过封装工艺700、封装工艺800以及封装工艺900制作的封装结构，参见图10并结合图1～图9，该封装结构除了包括根据封装工艺700和封装工艺800制作的相应封装结构外，还包括，阻焊层801，所述阻焊层801设置于所述第二外层线路层上。
应说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (6)

1.一种嵌入式有源埋入功能基板的封装工艺，其特征在于：包括，
提供两个初级封装组件，每个初级封装组件中有机基板的金属槽内封装有芯片,所述初级封装组件具有第一主面和与第一主面相对的第二主面，所述芯片的主侧与所述第二主面同向，且其上设置有连接垫片；
将两个初级封装组件的两个第一主面相对的压合形成次级封装组件，压合后两个初级封装组件中的两个有机基板夹持封装于所述有机基板的金属槽内的芯片；
自所述次级封装组件的两个外侧面对应所述芯片上的连接垫片进行盲孔开窗口并开设盲孔至所述芯片上的连接垫片处；
在所述次级封装组件上开设通孔，所述通孔贯穿所述次级封装组件；
对所述盲孔、所述通孔以及次级封装组件的两个外侧面进行化金属作为种子层，然后进行填孔电镀；
进行第一外层线路层的制作；
所述提供两个初级封装组件，其中每个初级封装组件的制作工艺包括，
提供一有机基板并在有机基板的一侧形成金属槽，所述金属槽的尺寸与待封装的芯片的尺寸相适应；
将所述芯片的主侧贴装于所述金属槽内；
在与所述芯片的主侧相对的另一侧进行金属制作以封装所述芯片；
进行区域金属蚀刻，所述区域金属蚀刻是对有电气连通的通孔的位置的金属进行蚀刻。
2.根据权利要求1所述的嵌入式有源埋入功能基板的封装工艺，其特征在于：在进行第一外层线路层的制作后，还包括，
在所述第一外层线路层的两个表面进行外层线路介质层的压合；
互连所述外层线路介质层上的介质层盲孔并进行第二外层线路层的制作。
3.根据权利要求2所述的嵌入式有源埋入功能基板的封装工艺，其特征在于：在进行第二外层线路层的制作后，还包括，
在所述第二外层线路层进行外层阻焊层的制作；
进行后续的芯片的组装或植球。
4.根据权利要求1所述的嵌入式有源埋入功能基板的封装工艺，其特征在于：
所述有机基板包括有机层以及夹持所述有机层的分别位于所述有机层的两个金属层，在有机基板第一主面形成金属槽之前，其还包括，
对所述有机基板的两个金属层进行增金属工艺，使得增金属后所述有机基板的两个金属层增厚。
5.根据权利要求1所述的嵌入式有源埋入功能基板的封装工艺，其特征在于：所述将两个初级封装组件的两个第一主面相对的压合形成次级封装组件后，其还包括，
将所述次级封装组件的两个外侧面上的金属进行减薄。
6.根据权利要求1所述的嵌入式有源埋入功能基板的封装工艺，其特征在于：所述在所述次级封装组件上开设通孔后，其还包括，
蚀刻所述次级封装组件的两个外侧面上的金属。
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