WO2017143782A1 - 埋入硅基板扇出型3d封装结构 - Google Patents

埋入硅基板扇出型3d封装结构 Download PDF

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Publication number
WO2017143782A1
WO2017143782A1 PCT/CN2016/101437 CN2016101437W WO2017143782A1 WO 2017143782 A1 WO2017143782 A1 WO 2017143782A1 CN 2016101437 W CN2016101437 W CN 2016101437W WO 2017143782 A1 WO2017143782 A1 WO 2017143782A1
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Prior art keywords
silicon substrate
fan
package structure
groove
embedded
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PCT/CN2016/101437
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English (en)
French (fr)
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于大全
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华天科技（昆山）电子有限公司
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Priority to EP16891230.1A priority Critical patent/EP3422398A4/en
Priority to KR1020187024776A priority patent/KR20180121893A/ko
Priority to JP2018544551A priority patent/JP2019512168A/ja
Publication of WO2017143782A1 publication Critical patent/WO2017143782A1/zh
Priority to US16/109,955 priority patent/US10559525B2/en

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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to the field of electronic packaging technology, and in particular to a buried silicon substrate fan-out type 3D package structure.
  • Wafer-level fan-out package which re-distributes the wafer and wafer-level rewiring, and I/O fills the package surface through the rewiring surface array to expand the I/O pitch to meet the next level of interconnection. Pitch requirements.
  • the material of the reconstituted wafer is mainly a molding compound, or an organic material such as a prepreg for substrate encapsulation, which realizes the plastic sealing of the fan-out structure of the functional chip, and finally cuts into a single package.
  • wafer-level fan-out packaging is considered to be an advanced packaging technology with a large number of I/Os and good integration flexibility.
  • the technical requirements for three-dimensional stacking have been proposed for fan-out packages.
  • the PoP package is integrated with a microprocessor chip and a memory chip, and the PoP package is in a BGA package.
  • the molding compound to form a micro-processed 3D fan-out type package structure, it can replace the PoP package shape. It can achieve higher density and smaller size interconnections.
  • it can be completed directly in the foundry or packaging plant without the need for substrate materials.
  • the current problem with the fan-out package is that the mold is used to reconstruct the wafer, and the processing of the mold plastic wafer is greatly different from that of the conventional silicon wafer.
  • Photolithography, development, exposure, fabrication of fine metal lines, and ball placement on silicon wafers are very mature.
  • the molding compound itself is very unsuitable for the above process, especially for the foundry. Therefore, in order to develop a fan-out process based on a molded plastic wafer, many process challenges must be overcome, and customized equipment is needed to solve the rounding of the molding compound which is easy to warp.
  • the handling of the sheets and the fine line preparation problems on the surface of the molding compound is large, which brings reliability problems. It has been reported that the fan-out structure is not suitable for the package of ultra-high 12 ⁇ 12 mm 2 ; Large chips, heat dissipation from molding compounds are also a problem.
  • Patent No. ZL201210243958.4 discloses a fan-out type wafer-level functional chip packaging method, including a functional chip, a metal microstructure, a high-density wiring layer, a silicon cavity, a bonding layer, and a solder bump.
  • the metal microstructure is formed on the functional chip by sputtering, photolithography, electroplating, etc., and the functional chip is flipped on the high-density wiring layer, and formed on the silicon cavity by optical masking, etching, or the like.
  • a concave silicon cavity the silicon cavity is buckled in the silicon cavity, the high-density wiring layer and the silicon cavity are bonded by a bonding layer, and heating is performed to cure the encapsulation layer and the bonding layer.
  • the invention has a complicated process and high cost, and is not suitable for a thin packaging process.
  • Patent No.: ZL201110069815.1 discloses a fan-out system packaging method, comprising the steps of: providing a carrier plate, forming a release film on the carrier plate, forming a protective layer on the release film, forming in the protective layer Rewiring the metal layer, forming a wiring encapsulation layer electrically connected to the rewiring metal layer on the protective layer, forming a wire bonding encapsulation layer on the wiring encapsulation layer, electrically connecting each group of encapsulation layers, removing the carrier plate and the release film
  • the rewiring metal in the first protective layer is exposed, and a metal solder ball is formed on the bare rewiring metal.
  • the patented technical solution can reduce the resistance, inductance and interference between functional chips in the system.
  • Patent Document No. ZL201110032264.1 discloses a highly integrated wafer fan-out package structure, comprising: a packaged unit, consisting of a functional chip and a passive device, the packaged unit having a functional surface; The opposite side of the functional surface of the package unit is formed with a sealing layer that encapsulates and cures the packaged unit, and the surface of the sealing layer corresponds to a groove provided between the packaged units.
  • Chinese patent 201110032519.7 discloses a highly integrated wafer fan-out packaging method comprising the following steps: (1) forming a glue layer on a carrier board; (2) functional surface of a packaged unit composed of a functional chip and a passive device.
  • the side of the carrier chip with the functional chip and the passive device is formed into a sealing layer for curing, and the surface of the sealing layer corresponds to a groove between the packaged units (4) removing the carrier and the glue layer.
  • the present invention provides a fan-out type 3D package structure embedded in a silicon substrate, which uses a silicon substrate instead of a molding compound or other non-silicon material as a fan-out substrate, and solves the problem that the molded plastic material is reconstructed by the wafer.
  • a series of problems such as warpage, mismatch in thermal expansion coefficient; use of a mature process on silicon to prepare high-density wiring; vertical conductive vias can be fabricated on silicon substrates in a variety of ways to achieve three-dimensional vertical interconnection.
  • a fan-out type 3D package structure embedded in a silicon substrate comprising a silicon substrate and at least one functional chip, the silicon substrate having at least one groove, the functional chip functioning upwardly embedded in the groove,
  • the functional chip is bonded to the groove by a polymer, and at least one conductive through hole penetrating the silicon substrate is formed outside the groove position on the silicon substrate, and at least one of the conductive through hole and the functional chip is formed.
  • the upper pads are electrically connected; the front and back sides of the silicon substrate have an electrical lead-out structure.
  • the functional chip is an integrated circuit chip or a MEMS chip.
  • the vertical cross-sectional shape of the groove is rectangular or trapezoidal, and the depth of the groove is not greater than the thickness of the silicon substrate.
  • an axial direction of the conductive via is perpendicular to a front surface of the silicon substrate.
  • the metal filled in the conductive via is one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold.
  • the metal filled in the conductive via is one of low melting point solder tin, tin silver, tin copper, tin gold, tin indium, and tin silver copper.
  • the conductive via is filled with a conductive paste.
  • the conductive via is electrically insulated from the silicon substrate.
  • the electrical lead-out structure is one of a solder ball, a metal bump, and a conductive paste.
  • At least one layer of metal wiring is formed on the front and back surfaces of the silicon substrate.
  • the invention provides a buried-out type 3D package structure of a silicon substrate.
  • the functional chip is embedded in the groove of the silicon substrate with the same material through the organic polymer adhesion, on the front surface of the silicon substrate.
  • the region not including the groove is provided with a vertical conductive via hole through which the functional chip can be electrically exported to the back surface of the silicon substrate, and metal wiring and solder balls can be prepared on the front and back surfaces of the silicon substrate.
  • the advantages of this structure are as follows: First, because the thermal expansion coefficient between the silicon substrate and the chip is close, the package structure has good reliability; secondly, the structure can realize interconnection of 3D package; again, using a silicon substrate, fine lines can be fabricated High-density wiring can meet the needs of high-density interconnections; finally, the package structure can be more easily miniaturized and thinned.
  • FIG. 1 is a plan view showing a buried functional chip when a silicon substrate is a wafer according to the present invention
  • FIG. 2 is a schematic cross-sectional view showing a first insulating layer formed by embedding a chip on a front surface of a wafer;
  • FIG. 3 is a schematic structural view of forming a silicon blind via lithography/etching on a first insulating layer according to the present invention
  • FIG. 4 is a schematic view showing a structure in which a second insulating layer is formed in a first insulating layer and a silicon blind via hole, and a die pad is exposed by photolithography/etching;
  • FIG. 5 is a schematic view showing the structure of forming a first metal rewiring on a silicon blind via filler metal and a surface according to the present invention
  • FIG. 6 is a schematic structural view showing a first passivation layer formed on a first metal rewiring and opening a corresponding passivation layer opening on a metal wiring according to the present invention
  • FIG. 7 is a schematic view showing the structure of the silicon substrate in the blind hole after thinning the back surface of the silicon substrate;
  • FIG. 8 is a schematic structural view showing the third insulating layer on the back side of the thinned silicon wafer wafer and exposing the first metal rewiring in the silicon blind via hole according to the present invention
  • FIG. 9 is a schematic structural view of the present invention for performing rewiring on a third insulating layer to form a metal connecting the conductive vias;
  • FIG. 10 is a schematic structural view showing a second passivation layer on a second metal rewiring and opening a corresponding passivation layer opening on the metal wiring;
  • Figure 11 is a schematic view showing the structure of forming solder balls on the openings of the first and second metal rewiring passivation layers on the first and back sides of the silicon substrate wafer according to the present invention.
  • a buried silicon substrate fan-out type 3D package structure includes a silicon substrate 1 and at least one functional chip 2.
  • the silicon substrate 1 encloses other surfaces of the functional chip that do not have a functional surface through the recess 103.
  • the functional chip 2 and the silicon substrate 1 have a bonding layer.
  • the silicon substrate 1 has a plurality of vertical conductive vias 104 near the recess. At least one pad 201 on the functional chip 2 is electrically connected to the conductive via 104, and an electrical lead-out structure 7 is formed on the front surface 101 and the back surface 102 of the silicon substrate 1.
  • the functional chip is buried therein, and at least one conductive via is formed in a region where the front surface of the silicon substrate does not include a recess, and the functional chip is passed through the conductive via.
  • the electrical conductivity of the solder pad is led to the back surface of the silicon substrate, and solder balls are formed on the front and back surfaces of the silicon substrate, and the external chip or the printed circuit board can pass through the solder balls on the front and back sides of the silicon substrate and the functional chip embedded in the silicon substrate.
  • the vertical cross-sectional shape of the groove is rectangular or trapezoidal, and the depth of the groove is not greater than the thickness of the silicon substrate.
  • the conductive via is axially perpendicular to the front side of the silicon substrate.
  • the metal filled in the conductive via may be one or more of a metal material such as titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, and is realized by physical vapor deposition, electroplating, or the like. It is also possible to fill a low melting point solder such as tin, tin silver, tin copper, tin gold, tin indium, tin silver copper or the like.
  • the conductive via hole may also be filled with a conductive paste, a through hole may be formed, and then the conductive paste is printed and filled.
  • the conductive via is filled with titanium or copper metal, wherein titanium is an adhesion layer.
  • the method for fabricating a silicon substrate fan-out type 3D package structure of the present invention comprises the following steps:
  • the shape of the groove may be A trapezoid, a rectangle or the like may be used to indicate the shape of the groove, the upper opening of the groove being larger than the bottom of the groove, the depth being comparable to the thickness of the packaged chip, and the size of the groove being such that the chip is placed therein.
  • the silicon substrate is a wafer, and the wafer is formed with a plurality of grooves arranged in an array, and the sidewalls of the grooves are vertical, as shown in FIG.
  • the functional chip 2 with the pad surface of the functional chip facing outward, the pad surface of the functional chip being close to the front surface of the silicon substrate, and having a gap between the functional chip and the sidewall of the groove The gap is filled by the polymer.
  • the functional chip can be attached into the groove of the silicon substrate through the adhesive or dry film.
  • the connection method used in the present embodiment is to bond with the adhesive, the functional chip and the The gap between the sidewalls of the groove is filled and bonded by the first insulating layer 401.
  • a first insulating layer 401 is laid over the gap on the pad surface of the functional chip and the front surface of the silicon substrate; the front surface of the silicon substrate does not include a groove.
  • At least one silicon blind via 105 having a certain depth is formed in the region; in a specific implementation, the opening of the silicon blind via is preset on the first insulating layer by a photolithography process, and the photolithography process mainly includes photoresist Coating, exposure, development, etc.
  • the opening is deeply etched to form a silicon blind hole having a certain depth
  • the etching can be divided into dry etching and wet etching, and dry etching is a new type, which uses plasma (plasma) ) to perform etching processing of semiconductor materials.
  • plasma plasma
  • the present invention forms a silicon blind via having a certain depth by dry etching.
  • a second insulating layer 402 is laid over the first insulating layer and the silicon blind vias, and the pad 201 of the functional chip is exposed; the second insulating layer is insulated from the first insulating layer.
  • the material of the layers can be the same or similar.
  • the pads of the lower functional chips of the first and second insulating layers are exposed by etching or photolithography; preferably, the method of filling the second insulating layer in the silicon blind vias is prepared by spraying.
  • the silicon blind hole is filled with metal and on the surface of the insulating layer.
  • the metal material may be one of copper, nickel, a target, and gold.
  • the method of forming the metal redistribution may be one of electroplating, electroless plating, vacuum evaporation, and physical vapor deposition.
  • the metal filling in the silicon blind hole can fill the hole or only fill a part; in this embodiment, the blind hole is not filled with metal for cost reasons;
  • the material of the metal rewiring in the silicon blind via is made of titanium or copper.
  • a first passivation layer 601 is formed on the first metal rewiring, and a first passivation layer is opened at a first metal rewiring preset pad position to prepare a pad;
  • the back surface of the silicon substrate is ground and thinned to expose the metal in the silicon blind hole;
  • the thinning process of the silicon substrate may be one of grinding, dry or wet etching. Or a combination of the two;
  • a third insulating layer 403 is laid on the back surface of the silicon substrate, and the metal in the silicon blind via is exposed by a process such as photolithography, development, exposure, etc., and the third insulating layer is laid on the third insulating layer.
  • a second passivation layer 602 is formed on the second metal rewiring, and a second passivation layer is opened at a second metal rewiring preset pad position to prepare a pad;
  • an electrically derived structure 7 is formed at the pads on the front and back sides of the silicon substrate. Electrically derived structures can be either solder balls or metal bumps Etc., solder balls are preferred in this embodiment.
  • the solder ball is formed by forming a solder ball on the front side; then forming a solder ball on the back surface of the silicon substrate.
  • the forming process of the first metal redistribution and the second metal redistribution comprises depositing a seed metal layer on the insulating layer, coating, photolithography, exposure, development, electroplating, degumming, seed layer etching .
  • a seed metal layer is deposited on the entire surface of the insulating layer, a metal redistribution pattern is exposed on the seed metal layer, and a metal line is formed on the exposed metal redistribution pattern by electroplating/lithography, and finally, the pattern is removed.
  • the seed metal layer forms a metal rewiring.
  • a vertical via interconnect structure is fabricated on a silicon substrate.
  • the holes may be laser ablated through holes and then an insulating layer, a seed layer, a plating fill, or a liquid metal solder fill, or a conductive paste print fill. Preferably, it is filled by electroplating metal.
  • (2) etching a groove on the silicon substrate to embed the functional chip into the groove.
  • the metal wiring is connected to the vertical conductive via; preparing a passivation layer, opening a passivation layer at a predetermined pad position, preparing a pad, printing a solder ball, or preparing a metal bump. (5) Cutting to form the final individual package.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种埋入硅基板扇出型3D封装结构，功能芯片（2）嵌入到硅基板（1）正面（101）上的凹槽（103）内，在硅基板正面凹槽外的区域制备有垂直导电通孔（104），通过导电通孔，功能芯片可以把电性导出至硅基板的背面（102），在硅基板的正面和背面可以制备有再布线（5）和焊球（7）。由于硅基板和芯片之间的热膨胀系数接近，封装结构具有良好的可靠性；该结构可以进行3D封装互连。

Description

埋入硅基板扇出型3D封装结构 技术领域
本发明涉及电子封装技术领域，具体是涉及一种埋入硅基板扇出型3D封装结构。
背景技术
在当前的半导体行业中，电子封装已经成为行业发展的一个重要方向，几十年封装技术的发展，使高密度、小尺寸的封装要求成为封装的主流方向。
晶圆级扇出封装，其通过重构圆片和圆片级再布线方式，把I/O通过再布线面阵列布满封装表面，以便于扩大I/O节距，满足下一级互连的节距要求。目前，重构圆片的材料主要是模塑料，或者用于基板封装的半固化片等有机材料，实现功能芯片扇出结构的塑封，最终切割成单颗封装体。
目前，通过多年的研发和产业化推动，晶圆级扇出封装被认为是一种I/O数较多、集成灵活性好的先进封装技术。随着智能手机的发展，对扇出型封装提出了三维堆叠的技术需求。比如原来利用PoP封装集成微处理器芯片和存储芯片，其PoP下封装体是利用BGA封装形式。现在通过在模塑料上制作垂直通孔形成微处理3D扇出型封装结构，可以取代PoP下封装形 式，可以做到更高密度，更小尺寸的互连。而且在产业链角度来看，直接在代工厂或封装厂就可以完成，无需基板材料。
随着电子产品向更薄、更轻、更高引脚密度、更低成本、***集成方面发展，采用单颗功能芯片封装技术已经逐渐无法满足产业需求，而扇出晶圆级封装技术的出现为封装行业想低成本封装发展提供了契机。这样，扇出晶圆级技术目前正在发展成为下一代主要的封装技术。
但是目前的扇出型封装突出的问题是使用模塑料来重构晶圆，对模塑料晶圆进行工艺加工与传统硅圆片的制成存在巨大的差异。在硅片上进行光刻，显影，曝光，制作精细金属线路，植球等非常成熟。但模塑料本身非常不适合进行上述工艺，特别是代工厂，因此为开发基于模塑料圆片的扇出工艺要克服很多工艺挑战，需要定制化的相关设备，以解决易于翘曲的模塑料圆片的拿持以及在模塑料表面的精细线路制备难题。进一步地，从结构本身来看，模塑料与硅的热膨胀系数差别较大，会带来可靠性问题，已有报道说明扇出型结构不适合超高12×12mm2的封装；对于功耗较大的芯片，模塑料的散热也是一个问题。
专利号为ZL201210243958.4专利文献，公开了一种扇出型圆片级功能芯片封装方法，包括功能芯片、金属微结构、高密度布线层、硅腔体、键合层和焊球凸点，在功能芯片上通过溅射、光刻、电镀等工艺形成金属微结构，将功能芯片倒装在高密度布线层上，用光学掩膜、刻蚀等方法在硅腔体上形成下 凹的硅腔，所述硅腔体将功能芯片扣置在硅腔体内，所述高密度布线层与硅腔体通过键合层键合，加热使包封料层和键合层固化成形。但该发明工艺复杂，成本高，不适合薄型封装工艺。
专利号为：ZL201110069815.1的专利文献，公开了一种扇出***封装方法，包括以下步骤：提供载板，在载板上形成剥离膜，在剥离膜上形成保护层，在保护层中形成再布线金属层，在保护层上形成与再布线金属层导通的布线封装层，在布线封装层上形成引线键合封装层，各组封装层之间相互电连接，去除载板及剥离膜，裸露出第一保护层中的再布线金属，在裸露的再布线金属上形成金属焊球。该专利的技术方案可以降低***内电阻、电感以及功能芯片间的干扰因素。
专利号为ZL201110032264.1的专利文献，公开了一种高集成度晶圆扇出封装结构，包括：被封装单元，由功能芯片及无源器件组成，所述被封装单元具有功能面；与被封装单元的功能面相对的另一面形成有封料层，所述封料层对被封装单元进行封装固化，所述封料层表面对应于被封装单元之间设有凹槽。中国专利201110032519.7公开了一种高集成度晶圆扇出封装方法，包括步骤如下：(1)在载板上形成胶合层；(2)将由功能芯片和无源器件组成的被封装单元的功能面贴于所述胶合层上；(3)将载板贴有功能芯片和无源器件的一面形成封料层，进行封装固化，所述封料层表面对应于被封装单元之间设有凹槽；(4)去除所述载板和胶合层。以上专利可以避免封料层在晶圆封装的后续制程中出现翘曲变形，提高晶圆封装成 品的质量。
上述现有技术虽然对封装方法进行了改进，但并未解决扇出晶圆级工艺中的工艺复杂、成本高的问题，不适合三维集成。
发明内容
为了解决上述技术问题，本发明提出一种埋入硅基板扇出型3D封装结构，使用硅基板取代模塑料或者其他非硅材料作为扇出的基体，解决了模塑料材料重构圆片带来的一系列问题，如翘曲，热膨胀系数不匹配；利用硅基上成熟的工艺来制备制作高密度布线；可以采用多种方法在硅基上制作垂直导电通孔，以实现三维垂直互连。
本发明的技术方案是这样实现的：
一种埋入硅基板扇出型3D封装结构，包括一硅基板和至少一功能芯片，所述硅基板具有至少一个凹槽，所述功能芯片功能面向上嵌入在所述凹槽中，所述功能芯片与所述凹槽之间通过聚合物粘结，所述硅基板上凹槽位置外形成有至少一个穿透硅基板的导电通孔，至少有一个所述导电通孔与所述功能芯片上的焊垫电连接；所述硅基板正面和背面均具有电性导出结构。
进一步的，所述功能芯片是集成电路芯片或MEMS芯片。
进一步的，所述凹槽的竖直截面形状为矩形或梯形，且所述凹槽的深度不大于所述硅基板的厚度。
进一步的，所述导电通孔的轴向垂直所述硅基板的正面。
进一步的，所述导电通孔内填充的金属为钛、钽、铬、钨、铜、铝、镍、金中的一种或几种。
进一步的，所述导电通孔内填充的金属为低熔点焊料锡、锡银、锡铜、锡金、锡铟和锡银铜中的一种。
进一步的，所述导电通孔内由导电胶填充。
进一步的，所述导电通孔与所述硅基板之间电绝缘。
进一步的，所述电性导出结构为焊球、金属凸点、导电胶中的一种。
进一步的，所述硅基板正面和背面形成有至少一层金属布线。
本发明的有益效果是：本发明提供一种埋入硅基板扇出型3D封装结构，该封装结构中，功能芯片通过有机聚合物粘连嵌入到材质相同的硅基板凹槽中，在硅基板正面不包含凹槽的区域制备有垂直导电通孔，通过导电通孔，功能芯片可以把电性导出至硅基板的背面，在硅基板的正面和背面可以制备有金属布线和焊球。这个结构的优点有：首先，由于硅基板和芯片之间的热膨胀系数接近，封装结构具有良好的可靠性；其次，该结构可以进行实现3D封装互连；再次，采用硅基板，可以制作细线条，高密度布线，可以满足高密度互连的需要；最后，该封装结构可以更容易实现小型化，薄型化。
附图说明
图1为本发明硅基板为晶圆时埋入功能芯片的俯视图；
图2为本发明在晶圆正面埋入芯片，并于其上制备第一绝缘层的剖面示意图；
图3为本发明在第一绝缘层上通过光刻/刻蚀形成硅盲孔的结构示意图；
图4为本发明在第一绝缘层及硅盲孔内制备第二绝缘层，并通过光刻/刻蚀暴露出芯片焊垫的结构示意图；
图5为本发明在硅盲孔填充金属和表面上形成第一金属重布线的结构示意图；
图6为本发明在第一金属重布线上形成第一钝化层并在金属布线上打开相应钝化层开口的结构示意图；
图7为本发明对硅基板圆片背面减薄，暴露出硅盲孔内金属的结构示意图；
图8为本发明在减薄后的硅晶圆圆片背面铺设第三绝缘层，并暴露出硅盲孔内的第一金属重布线的结构示意图；
图9为本发明在第三绝缘层上进行重布线，形成连接导电通孔金属的结构示意图；
图10为本发明在第二金属重布线上铺设第二钝化层，并在金属布线上打开相应钝化层开口的结构示意图；
图11为本发明在硅基板圆片第一、背面的第一、第二金属重布线钝化层开口上形成焊球的结构示意图。
结合附图，作以下说明：
1-硅基板，101-正面，102-背面，103-凹槽，104-硅导电通孔，105-硅盲孔，2-功能芯片，201-焊垫，3-粘结层，4- 绝缘层，401-第一绝缘层，402-第二绝缘层，403-第三绝缘层5-金属重布线，501-第一金属重布线，502-第二金属重布线，6-钝化层，601-第一钝化层，602-第二钝化层，7-电性导出结构
具体实施方式
为了能够更清楚地理解本发明的技术内容，特举以下实施例详细说明，其目的仅在于更好理解本发明的内容而非限制本发明的保护范围。实施例附图的结构中各组成部分未按正常比例缩放，故不代表实施例中各结构的实际相对大小。
如图11所示，一种埋入硅基板扇出型3D封装结构，包括一硅基板1和至少一功能芯片2。所述硅基板1通过凹槽103包封功能芯片不含功能面的其它表面，功能芯片2与硅基板1之间有粘结层，硅基板1上凹槽附近有若干垂直的导电通孔104，所述功能芯片2上至少有一个焊垫201与导电通孔104电连接，在硅基板1正面101和背面102形成电性导出结构7。这样，通过在与功能芯片材质相同的硅基板正面上制作凹槽，将功能芯片埋入其中，并在硅基板正面不包含凹槽的区域制作至少一个导电通孔，通过导电通孔将功能芯片焊垫的电性导出至硅基板的背面，并在硅基板的正面和背面形成焊球，外界芯片或者印刷电路板可通过硅基板正面和背面的焊球与硅基板中埋入的功能芯片电性相连，实现3D封装中所需实现的特定功能；能够有效的解决目前应用模塑料扇出封装造成的热膨胀 系数不匹配，模塑料重构晶圆的翘曲带来的工艺加工困难等问题，同时本发明的所有操作都只在硅基板进行，工艺成熟，适合高密度互连和封装小型化。
优选的，所述凹槽的竖直截面形状为矩形或梯形，且所述凹槽的深度不大于所述硅基板的厚度。
优选的，所述导电通孔的轴向垂直所述硅基板的正面。
所述导电通孔内填充的金属可以是金属材料如钛、钽、铬、钨、铜、铝、镍、金中一种或几种，通过物理汽相沉积，电镀填充等方式实现。也可以填充低熔点焊料，如锡，锡银，锡铜，锡金，锡铟，锡银铜等中的一种。所述导电通孔内也可以由导电胶填充，可以制作通孔，然后印刷填充导电胶。优选的，所述导电通孔内填充的是钛、铜金属，其中钛是粘附层。
作为一种优选实施例，本发明埋入硅基板扇出型3D封装结构的制作方法，包括如下步骤：
A.提供一与功能芯片材质相同的硅基板1，所述硅基板具有正面101和与其相对的背面102，在所述硅基板的正面刻蚀形成至少一个凹槽103；凹槽的形状可以是梯形，矩形或其他可以用来表示凹槽的形状，凹槽的上开口大于凹槽底部，深度与所封装芯片的厚度相当，并且所述凹槽尺寸可以满足芯片放置于内。
优选的，所述硅基板为晶圆，所述晶圆上形成有若干排布成阵列的凹槽，凹槽侧壁垂直，参见图1所示。
B.参见图2，在所述凹槽内通过粘附层3贴装至少一个 功能芯片2，并使所述功能芯片的焊垫面朝外，所述功能芯片的焊垫面接近所述硅基板的正面，且所述功能芯片与所述凹槽的侧壁之间具有间隙；间隙由聚合物填充，具体实施时，功能芯片可通过粘结胶或者干膜贴装到硅基板凹槽内，本实施采用的连接方式是利用粘结胶进行粘结，功能芯片与所述凹槽的侧壁之间间隙由第一绝缘层401填充粘结。
C.参见图3，在所述间隙内、所述功能芯片的焊垫面上及所述硅基板的正面上整面铺设一层第一绝缘层401；在硅基板的正面不包含凹槽的区域中形成至少一个具有一定深度的硅盲孔105；具体实施时，可先利用光刻工艺在第一绝缘层上预设硅盲孔的位置暴露出开口，光刻工艺主要包括光刻胶的涂布，曝光，显影等操作。然后，对该开口进行深度刻蚀，形成具有一定深度的硅盲孔，刻蚀可以分为干法刻蚀和湿法刻蚀，干法刻蚀是一类较新型，其利用电浆(plasma)来进行半导体材料的蚀刻加工。作为一种优选实施，本发明通过干法刻蚀形成具有一定深度的硅盲孔。
D.参见图4，在第一绝缘层上及所述硅盲孔内整面铺设一层第二绝缘层402，并暴露出所述功能芯片的焊垫201；第二绝缘层与第一绝缘层的材质可以相同，也可以近似。通过刻蚀或者光刻工艺使第一、第二绝缘层下功能芯片的焊垫暴露出来；优选的，硅盲孔中填充第二绝缘层的方式是采用喷涂方式制备。
E.参见图5，在硅盲孔填充金属，并在表面的绝缘层上 铺设第一金属重布线501，并使所述第一金属重布线与所述功能芯片的焊垫电连接，所述第一金属重布线上形成有焊盘；具体实施时，每层金属重布线的金属材质可以是铜、镍、靶、金中的一种，形成金属重布线的方法可以为电镀、化学镀、真空蒸镀法、物理汽相沉积中的一种。硅盲孔内的金属填充可以填满孔也可以只填充一部分；本实施例考虑到成本原因，盲孔不填满金属；
优选的，硅盲孔内的金属重布线的材质为钛、铜。
F.参见图6，在所述第一金属重布线上面制作一层第一钝化层601，在第一金属重布线预设焊盘位置打开第一钝化层，制备焊盘；
G.参见图7，对所述硅基板背面进行研磨减薄，使所述硅盲孔中的金属暴露出来；硅基板减薄的工艺可以是研磨、干法或湿法刻蚀中的一种或者两种相结合；
H.参见图8和图9，在所述硅基板背面铺设第三绝缘层403，通过光刻、显影，曝光等工艺使所述硅盲孔中金属暴露出来，在第三绝缘层上铺设第二金属重布线502，并使其与导电通孔电连接；
I.参见图10，在所述第二金属重布线上面制作一层第二钝化层602，在第二金属重布线预设焊盘位置打开第二钝化层，制备焊盘；
J.参见图11，在所述硅基板正面及背面上的焊盘处形成有电性导出结构7。电性导出结构可以为或焊球或者金属凸点 等，本实施例中优选焊球。形成焊球的方式可以在正面先形成焊球；然后在硅基板背面形成焊球。
优选的，所述第一金属重布线及所述第二金属重布线的形成工艺包括在绝缘层上沉积种子金属层、涂胶、光刻、曝光、显影、电镀、去胶、种子层刻蚀。或者，在绝缘层上整面沉积种子金属层，在种子金属层上光刻暴露出金属重布线图形，在暴露出的金属重布线图形上电镀/化镀方式形成金属线路，最后，去除图形外的种子金属层，形成金属重布线。
形成本发明结构的另一个方法可以是如下流程：(1)在一个硅基板上制备垂直通孔互连结构。孔可以是激光烧蚀的通孔，然后制备绝缘层，种子层，电镀填充，或者液态金属焊料填充，或者导电胶印刷填充。优选的，通过电镀金属填充。(2)在所述硅基板上刻蚀制作凹槽，把功能芯片埋入到凹槽内。(3)在正面上制备再布线金属层，至少有一个功能芯片上的焊盘与一个垂直导电通孔电连接；制备钝化层，在预设焊盘位置打开钝化层，制备焊盘，印刷焊球或制备金属凸点。(4)在背面上制备再布线金属层，金属布线与垂直导电通孔连接；制备钝化层，在预设焊盘位置打开钝化层，制备焊盘，印刷焊球或制备金属凸点。(5)切割，形成最终单个封装体。
以上实施例是参照附图，对本发明的优选实施例进行详细说明。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更，但不背离本发明的实质的情况下，都落在本发明的保护范围之内。

Claims (10)

  1. 一种埋入硅基板扇出型3D封装结构，其特征在于：包括一硅基板(1)和至少一功能芯片(2)，所述硅基板(1)具有至少一个凹槽(103)，所述功能芯片(2)功能面向上嵌入在所述凹槽中，所述功能芯片(2)与所述凹槽之间通过聚合物粘结，所述硅基板(1)上凹槽位置外形成有至少一个穿透硅基板的导电通孔(104)，至少有一个所述导电通孔(104)与所述功能芯片(2)上的焊垫(201)电连接；所述硅基板(1)正面(101)和背面(102)均具有电性导出结构(7)。
  2. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述功能芯片是集成电路芯片或MEMS芯片。
  3. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述凹槽的竖直截面形状为矩形或梯形，且所述凹槽的深度不大于所述硅基板的厚度。
  4. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述导电通孔的轴向垂直所述硅基板的正面。
  5. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述导电通孔内填充的金属为钛、钽、铬、钨、铜、铝、镍、金中的一种或几种。
  6. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述导电通孔内填充的金属为低熔点焊料锡、锡银、锡铜、锡金、锡铟和锡银铜中的一种。
  7. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述导电通孔内由导电胶填充。
  8. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于：所述导电通孔与所述硅基板之间电绝缘。
  9. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于，所述电性导出结构为焊球、金属凸点、导电胶中的一种。
  10. 根据权利要求1所述的埋入硅基板扇出型3D封装结构，其特征在于，所述硅基板正面和背面形成有至少一层金属布线。
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