WO2017143782A1 - 埋入硅基板扇出型3d封装结构 - Google Patents
埋入硅基板扇出型3d封装结构 Download PDFInfo
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- WO2017143782A1 WO2017143782A1 PCT/CN2016/101437 CN2016101437W WO2017143782A1 WO 2017143782 A1 WO2017143782 A1 WO 2017143782A1 CN 2016101437 W CN2016101437 W CN 2016101437W WO 2017143782 A1 WO2017143782 A1 WO 2017143782A1
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- silicon substrate
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 111
- 239000010703 silicon Substances 0.000 title claims abstract description 111
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 107
- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 3
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 77
- 235000012431 wafers Nutrition 0.000 description 27
- 238000000034 method Methods 0.000 description 25
- 238000002161 passivation Methods 0.000 description 16
- 238000004806 packaging method and process Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 8
- 238000011161 development Methods 0.000 description 8
- 238000000465 moulding Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000012536 packaging technology Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000002991 molded plastic Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/0237—Disposition of the redistribution layers
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- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Definitions
- the present invention relates to the field of electronic packaging technology, and in particular to a buried silicon substrate fan-out type 3D package structure.
- Wafer-level fan-out package which re-distributes the wafer and wafer-level rewiring, and I/O fills the package surface through the rewiring surface array to expand the I/O pitch to meet the next level of interconnection. Pitch requirements.
- the material of the reconstituted wafer is mainly a molding compound, or an organic material such as a prepreg for substrate encapsulation, which realizes the plastic sealing of the fan-out structure of the functional chip, and finally cuts into a single package.
- wafer-level fan-out packaging is considered to be an advanced packaging technology with a large number of I/Os and good integration flexibility.
- the technical requirements for three-dimensional stacking have been proposed for fan-out packages.
- the PoP package is integrated with a microprocessor chip and a memory chip, and the PoP package is in a BGA package.
- the molding compound to form a micro-processed 3D fan-out type package structure, it can replace the PoP package shape. It can achieve higher density and smaller size interconnections.
- it can be completed directly in the foundry or packaging plant without the need for substrate materials.
- the current problem with the fan-out package is that the mold is used to reconstruct the wafer, and the processing of the mold plastic wafer is greatly different from that of the conventional silicon wafer.
- Photolithography, development, exposure, fabrication of fine metal lines, and ball placement on silicon wafers are very mature.
- the molding compound itself is very unsuitable for the above process, especially for the foundry. Therefore, in order to develop a fan-out process based on a molded plastic wafer, many process challenges must be overcome, and customized equipment is needed to solve the rounding of the molding compound which is easy to warp.
- the handling of the sheets and the fine line preparation problems on the surface of the molding compound is large, which brings reliability problems. It has been reported that the fan-out structure is not suitable for the package of ultra-high 12 ⁇ 12 mm 2 ; Large chips, heat dissipation from molding compounds are also a problem.
- Patent No. ZL201210243958.4 discloses a fan-out type wafer-level functional chip packaging method, including a functional chip, a metal microstructure, a high-density wiring layer, a silicon cavity, a bonding layer, and a solder bump.
- the metal microstructure is formed on the functional chip by sputtering, photolithography, electroplating, etc., and the functional chip is flipped on the high-density wiring layer, and formed on the silicon cavity by optical masking, etching, or the like.
- a concave silicon cavity the silicon cavity is buckled in the silicon cavity, the high-density wiring layer and the silicon cavity are bonded by a bonding layer, and heating is performed to cure the encapsulation layer and the bonding layer.
- the invention has a complicated process and high cost, and is not suitable for a thin packaging process.
- Patent No.: ZL201110069815.1 discloses a fan-out system packaging method, comprising the steps of: providing a carrier plate, forming a release film on the carrier plate, forming a protective layer on the release film, forming in the protective layer Rewiring the metal layer, forming a wiring encapsulation layer electrically connected to the rewiring metal layer on the protective layer, forming a wire bonding encapsulation layer on the wiring encapsulation layer, electrically connecting each group of encapsulation layers, removing the carrier plate and the release film
- the rewiring metal in the first protective layer is exposed, and a metal solder ball is formed on the bare rewiring metal.
- the patented technical solution can reduce the resistance, inductance and interference between functional chips in the system.
- Patent Document No. ZL201110032264.1 discloses a highly integrated wafer fan-out package structure, comprising: a packaged unit, consisting of a functional chip and a passive device, the packaged unit having a functional surface; The opposite side of the functional surface of the package unit is formed with a sealing layer that encapsulates and cures the packaged unit, and the surface of the sealing layer corresponds to a groove provided between the packaged units.
- Chinese patent 201110032519.7 discloses a highly integrated wafer fan-out packaging method comprising the following steps: (1) forming a glue layer on a carrier board; (2) functional surface of a packaged unit composed of a functional chip and a passive device.
- the side of the carrier chip with the functional chip and the passive device is formed into a sealing layer for curing, and the surface of the sealing layer corresponds to a groove between the packaged units (4) removing the carrier and the glue layer.
- the present invention provides a fan-out type 3D package structure embedded in a silicon substrate, which uses a silicon substrate instead of a molding compound or other non-silicon material as a fan-out substrate, and solves the problem that the molded plastic material is reconstructed by the wafer.
- a series of problems such as warpage, mismatch in thermal expansion coefficient; use of a mature process on silicon to prepare high-density wiring; vertical conductive vias can be fabricated on silicon substrates in a variety of ways to achieve three-dimensional vertical interconnection.
- a fan-out type 3D package structure embedded in a silicon substrate comprising a silicon substrate and at least one functional chip, the silicon substrate having at least one groove, the functional chip functioning upwardly embedded in the groove,
- the functional chip is bonded to the groove by a polymer, and at least one conductive through hole penetrating the silicon substrate is formed outside the groove position on the silicon substrate, and at least one of the conductive through hole and the functional chip is formed.
- the upper pads are electrically connected; the front and back sides of the silicon substrate have an electrical lead-out structure.
- the functional chip is an integrated circuit chip or a MEMS chip.
- the vertical cross-sectional shape of the groove is rectangular or trapezoidal, and the depth of the groove is not greater than the thickness of the silicon substrate.
- an axial direction of the conductive via is perpendicular to a front surface of the silicon substrate.
- the metal filled in the conductive via is one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold.
- the metal filled in the conductive via is one of low melting point solder tin, tin silver, tin copper, tin gold, tin indium, and tin silver copper.
- the conductive via is filled with a conductive paste.
- the conductive via is electrically insulated from the silicon substrate.
- the electrical lead-out structure is one of a solder ball, a metal bump, and a conductive paste.
- At least one layer of metal wiring is formed on the front and back surfaces of the silicon substrate.
- the invention provides a buried-out type 3D package structure of a silicon substrate.
- the functional chip is embedded in the groove of the silicon substrate with the same material through the organic polymer adhesion, on the front surface of the silicon substrate.
- the region not including the groove is provided with a vertical conductive via hole through which the functional chip can be electrically exported to the back surface of the silicon substrate, and metal wiring and solder balls can be prepared on the front and back surfaces of the silicon substrate.
- the advantages of this structure are as follows: First, because the thermal expansion coefficient between the silicon substrate and the chip is close, the package structure has good reliability; secondly, the structure can realize interconnection of 3D package; again, using a silicon substrate, fine lines can be fabricated High-density wiring can meet the needs of high-density interconnections; finally, the package structure can be more easily miniaturized and thinned.
- FIG. 1 is a plan view showing a buried functional chip when a silicon substrate is a wafer according to the present invention
- FIG. 2 is a schematic cross-sectional view showing a first insulating layer formed by embedding a chip on a front surface of a wafer;
- FIG. 3 is a schematic structural view of forming a silicon blind via lithography/etching on a first insulating layer according to the present invention
- FIG. 4 is a schematic view showing a structure in which a second insulating layer is formed in a first insulating layer and a silicon blind via hole, and a die pad is exposed by photolithography/etching;
- FIG. 5 is a schematic view showing the structure of forming a first metal rewiring on a silicon blind via filler metal and a surface according to the present invention
- FIG. 6 is a schematic structural view showing a first passivation layer formed on a first metal rewiring and opening a corresponding passivation layer opening on a metal wiring according to the present invention
- FIG. 7 is a schematic view showing the structure of the silicon substrate in the blind hole after thinning the back surface of the silicon substrate;
- FIG. 8 is a schematic structural view showing the third insulating layer on the back side of the thinned silicon wafer wafer and exposing the first metal rewiring in the silicon blind via hole according to the present invention
- FIG. 9 is a schematic structural view of the present invention for performing rewiring on a third insulating layer to form a metal connecting the conductive vias;
- FIG. 10 is a schematic structural view showing a second passivation layer on a second metal rewiring and opening a corresponding passivation layer opening on the metal wiring;
- Figure 11 is a schematic view showing the structure of forming solder balls on the openings of the first and second metal rewiring passivation layers on the first and back sides of the silicon substrate wafer according to the present invention.
- a buried silicon substrate fan-out type 3D package structure includes a silicon substrate 1 and at least one functional chip 2.
- the silicon substrate 1 encloses other surfaces of the functional chip that do not have a functional surface through the recess 103.
- the functional chip 2 and the silicon substrate 1 have a bonding layer.
- the silicon substrate 1 has a plurality of vertical conductive vias 104 near the recess. At least one pad 201 on the functional chip 2 is electrically connected to the conductive via 104, and an electrical lead-out structure 7 is formed on the front surface 101 and the back surface 102 of the silicon substrate 1.
- the functional chip is buried therein, and at least one conductive via is formed in a region where the front surface of the silicon substrate does not include a recess, and the functional chip is passed through the conductive via.
- the electrical conductivity of the solder pad is led to the back surface of the silicon substrate, and solder balls are formed on the front and back surfaces of the silicon substrate, and the external chip or the printed circuit board can pass through the solder balls on the front and back sides of the silicon substrate and the functional chip embedded in the silicon substrate.
- the vertical cross-sectional shape of the groove is rectangular or trapezoidal, and the depth of the groove is not greater than the thickness of the silicon substrate.
- the conductive via is axially perpendicular to the front side of the silicon substrate.
- the metal filled in the conductive via may be one or more of a metal material such as titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, and is realized by physical vapor deposition, electroplating, or the like. It is also possible to fill a low melting point solder such as tin, tin silver, tin copper, tin gold, tin indium, tin silver copper or the like.
- the conductive via hole may also be filled with a conductive paste, a through hole may be formed, and then the conductive paste is printed and filled.
- the conductive via is filled with titanium or copper metal, wherein titanium is an adhesion layer.
- the method for fabricating a silicon substrate fan-out type 3D package structure of the present invention comprises the following steps:
- the shape of the groove may be A trapezoid, a rectangle or the like may be used to indicate the shape of the groove, the upper opening of the groove being larger than the bottom of the groove, the depth being comparable to the thickness of the packaged chip, and the size of the groove being such that the chip is placed therein.
- the silicon substrate is a wafer, and the wafer is formed with a plurality of grooves arranged in an array, and the sidewalls of the grooves are vertical, as shown in FIG.
- the functional chip 2 with the pad surface of the functional chip facing outward, the pad surface of the functional chip being close to the front surface of the silicon substrate, and having a gap between the functional chip and the sidewall of the groove The gap is filled by the polymer.
- the functional chip can be attached into the groove of the silicon substrate through the adhesive or dry film.
- the connection method used in the present embodiment is to bond with the adhesive, the functional chip and the The gap between the sidewalls of the groove is filled and bonded by the first insulating layer 401.
- a first insulating layer 401 is laid over the gap on the pad surface of the functional chip and the front surface of the silicon substrate; the front surface of the silicon substrate does not include a groove.
- At least one silicon blind via 105 having a certain depth is formed in the region; in a specific implementation, the opening of the silicon blind via is preset on the first insulating layer by a photolithography process, and the photolithography process mainly includes photoresist Coating, exposure, development, etc.
- the opening is deeply etched to form a silicon blind hole having a certain depth
- the etching can be divided into dry etching and wet etching, and dry etching is a new type, which uses plasma (plasma) ) to perform etching processing of semiconductor materials.
- plasma plasma
- the present invention forms a silicon blind via having a certain depth by dry etching.
- a second insulating layer 402 is laid over the first insulating layer and the silicon blind vias, and the pad 201 of the functional chip is exposed; the second insulating layer is insulated from the first insulating layer.
- the material of the layers can be the same or similar.
- the pads of the lower functional chips of the first and second insulating layers are exposed by etching or photolithography; preferably, the method of filling the second insulating layer in the silicon blind vias is prepared by spraying.
- the silicon blind hole is filled with metal and on the surface of the insulating layer.
- the metal material may be one of copper, nickel, a target, and gold.
- the method of forming the metal redistribution may be one of electroplating, electroless plating, vacuum evaporation, and physical vapor deposition.
- the metal filling in the silicon blind hole can fill the hole or only fill a part; in this embodiment, the blind hole is not filled with metal for cost reasons;
- the material of the metal rewiring in the silicon blind via is made of titanium or copper.
- a first passivation layer 601 is formed on the first metal rewiring, and a first passivation layer is opened at a first metal rewiring preset pad position to prepare a pad;
- the back surface of the silicon substrate is ground and thinned to expose the metal in the silicon blind hole;
- the thinning process of the silicon substrate may be one of grinding, dry or wet etching. Or a combination of the two;
- a third insulating layer 403 is laid on the back surface of the silicon substrate, and the metal in the silicon blind via is exposed by a process such as photolithography, development, exposure, etc., and the third insulating layer is laid on the third insulating layer.
- a second passivation layer 602 is formed on the second metal rewiring, and a second passivation layer is opened at a second metal rewiring preset pad position to prepare a pad;
- an electrically derived structure 7 is formed at the pads on the front and back sides of the silicon substrate. Electrically derived structures can be either solder balls or metal bumps Etc., solder balls are preferred in this embodiment.
- the solder ball is formed by forming a solder ball on the front side; then forming a solder ball on the back surface of the silicon substrate.
- the forming process of the first metal redistribution and the second metal redistribution comprises depositing a seed metal layer on the insulating layer, coating, photolithography, exposure, development, electroplating, degumming, seed layer etching .
- a seed metal layer is deposited on the entire surface of the insulating layer, a metal redistribution pattern is exposed on the seed metal layer, and a metal line is formed on the exposed metal redistribution pattern by electroplating/lithography, and finally, the pattern is removed.
- the seed metal layer forms a metal rewiring.
- a vertical via interconnect structure is fabricated on a silicon substrate.
- the holes may be laser ablated through holes and then an insulating layer, a seed layer, a plating fill, or a liquid metal solder fill, or a conductive paste print fill. Preferably, it is filled by electroplating metal.
- (2) etching a groove on the silicon substrate to embed the functional chip into the groove.
- the metal wiring is connected to the vertical conductive via; preparing a passivation layer, opening a passivation layer at a predetermined pad position, preparing a pad, printing a solder ball, or preparing a metal bump. (5) Cutting to form the final individual package.
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Abstract
Description
Claims (10)
- 一种埋入硅基板扇出型3D封装结构,其特征在于:包括一硅基板(1)和至少一功能芯片(2),所述硅基板(1)具有至少一个凹槽(103),所述功能芯片(2)功能面向上嵌入在所述凹槽中,所述功能芯片(2)与所述凹槽之间通过聚合物粘结,所述硅基板(1)上凹槽位置外形成有至少一个穿透硅基板的导电通孔(104),至少有一个所述导电通孔(104)与所述功能芯片(2)上的焊垫(201)电连接;所述硅基板(1)正面(101)和背面(102)均具有电性导出结构(7)。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述功能芯片是集成电路芯片或MEMS芯片。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述凹槽的竖直截面形状为矩形或梯形,且所述凹槽的深度不大于所述硅基板的厚度。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述导电通孔的轴向垂直所述硅基板的正面。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述导电通孔内填充的金属为钛、钽、铬、钨、铜、铝、镍、金中的一种或几种。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述导电通孔内填充的金属为低熔点焊料锡、锡银、锡铜、锡金、锡铟和锡银铜中的一种。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述导电通孔内由导电胶填充。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于:所述导电通孔与所述硅基板之间电绝缘。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于,所述电性导出结构为焊球、金属凸点、导电胶中的一种。
- 根据权利要求1所述的埋入硅基板扇出型3D封装结构,其特征在于,所述硅基板正面和背面形成有至少一层金属布线。
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KR1020187024776A KR20180121893A (ko) | 2016-02-23 | 2016-10-07 | 내장형 실리콘 기판의 팬 아웃 3d 패키지 구조 |
JP2018544551A JP2019512168A (ja) | 2016-02-23 | 2016-10-07 | シリコン基板に埋め込まれたファンアウト型の3dパッケージ構造 |
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Cited By (4)
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US10504841B2 (en) | 2018-01-21 | 2019-12-10 | Shun-Ping Huang | Semiconductor package and method of forming the same |
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Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN117303305A (zh) * | 2023-11-29 | 2023-12-29 | 麦斯塔微电子(深圳)有限公司 | 一种mems器件封装结构及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1893053A (zh) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | 插件结构及其制造方法、晶片级堆叠结构和封装结构 |
CN105023900A (zh) * | 2015-08-11 | 2015-11-04 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装结构及其制造方法 |
CN105575913A (zh) * | 2016-02-23 | 2016-05-11 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
CN205488088U (zh) * | 2016-02-23 | 2016-08-17 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243605A (ja) * | 2002-02-21 | 2003-08-29 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
US7838337B2 (en) * | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US8847376B2 (en) * | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
US8518746B2 (en) * | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
CN103646943A (zh) * | 2013-09-30 | 2014-03-19 | 南通富士通微电子股份有限公司 | 晶圆封装结构 |
CN104485320A (zh) * | 2014-12-30 | 2015-04-01 | 华天科技(西安)有限公司 | 一种有垂直通孔的埋入式传感芯片封装结构及其制备方法 |
-
2016
- 2016-02-23 CN CN201610098740.2A patent/CN105575913B/zh active Active
- 2016-10-07 EP EP16891230.1A patent/EP3422398A4/en not_active Withdrawn
- 2016-10-07 WO PCT/CN2016/101437 patent/WO2017143782A1/zh active Application Filing
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- 2016-10-07 KR KR1020187024776A patent/KR20180121893A/ko not_active Application Discontinuation
-
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- 2018-08-23 US US16/109,955 patent/US10559525B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1893053A (zh) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | 插件结构及其制造方法、晶片级堆叠结构和封装结构 |
CN105023900A (zh) * | 2015-08-11 | 2015-11-04 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装结构及其制造方法 |
CN105575913A (zh) * | 2016-02-23 | 2016-05-11 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
CN205488088U (zh) * | 2016-02-23 | 2016-08-17 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
Non-Patent Citations (1)
Title |
---|
See also references of EP3422398A4 * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109987572A (zh) * | 2017-12-29 | 2019-07-09 | 中芯长电半导体(江阴)有限公司 | 一种mems晶圆级封装结构及方法 |
US10504841B2 (en) | 2018-01-21 | 2019-12-10 | Shun-Ping Huang | Semiconductor package and method of forming the same |
CN111968942A (zh) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | 一种转接板侧壁互联射频模组的互联工艺 |
CN111968942B (zh) * | 2020-08-24 | 2023-08-04 | 浙江集迈科微电子有限公司 | 一种转接板侧壁互联射频模组的互联工艺 |
CN113078148A (zh) * | 2021-03-12 | 2021-07-06 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN113078148B (zh) * | 2021-03-12 | 2024-03-26 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
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KR20180121893A (ko) | 2018-11-09 |
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CN105575913B (zh) | 2019-02-01 |
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