CN1835229A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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CN1835229A
CN1835229A CNA2006100592086A CN200610059208A CN1835229A CN 1835229 A CN1835229 A CN 1835229A CN A2006100592086 A CNA2006100592086 A CN A2006100592086A CN 200610059208 A CN200610059208 A CN 200610059208A CN 1835229 A CN1835229 A CN 1835229A
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chip
semiconductor
semiconductor substrate
connection pads
wiring plate
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CN100470793C (zh
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波多野正喜
高冈裕二
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Sony Corp
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Sony Corp
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Abstract

本发明提供了一种廉价且能够抑制信号传输延迟的半导体器件及其制造方法。该半导体器件包括：多个半导体芯片；半导体衬底，在其同一表面上具有用于把所述多个半导体芯片彼此电连接的芯片到芯片互连以及连接到所述芯片到芯片互连的多个芯片连接焊盘；以及布线板，具有多个焊接区，所述焊接区的间距大于所述芯片连接焊盘的间距，其中所述多个半导体芯片的每个的主表面通过第一连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在半导体衬底上，且在所述主表面上除面对所述半导体衬底的区域之外形成外部连接焊盘并通过第二连接器将其连接到所述布线板上的所述焊接区。

Description

半导体器件和制造半导体器件的方法
技术领域
本发明涉及被称为所谓的封装中***(system in package)的半导体器件及其制造方法，在封装中***中多个半导体芯片安装在一个封装形式中。本发明更具体地涉及这样一种半导体器件及其制造方法，该半导体器件具有这样的结构，其中把半导体衬底用于电连接多个半导体芯片。
背景技术
电子设备向着更高功能发展的近期趋势正要求设备中所用的半导体芯片也具有更高的功能。不过，试图用芯片上***(SoC)的方法(其中大尺度的功能***是形成于一个芯片上的)实现更高的功能要求芯片的大尺度开发，导致了开发周期长和成本高昂的问题。因此提出了封装中***(SiP)的方法，其中多个半导体芯片是安装在***式衬底(interposer substrate)上的且所得的组件被用作一个封装部件。
例如，日本专利公开No.2004-79745(以下简称专利文献1)公开了一种SiP方法，其中在***式硅衬底上边靠边地倒装焊安装多个芯片。
将参考图16描述该SiP结构。***式硅衬底53具有表面互连层50和通孔部分56。表面互连层50具有用于在多个芯片之间互连的细微互连(例如具有亚微米线和空间的互连)以及用于连接到芯片的小间距(例如60μm或更小的间距)焊盘。通孔部分56是通过例如以如下方式电镀而形成的导电部分：填充沿其厚度方向穿过***式硅衬底53的通孔并在通孔的侧壁和导电部分之间插置绝缘膜。通孔部分56导引从表面互连层50中的焊盘到形成(重新布置，rearranged)于***式硅衬底53的下表面(安装有芯片的表面的相对表面)上的焊盘49的互连，且具有相对较大的间距(例如100μm或更大的间距)，允许连接到***式有机衬底57。
多个半导体芯片2a和2b通过焊料凸点(solder bump)51倒装焊连接到***式硅衬底53的表面互连层50上，以便安装于***式硅衬底53上。用底填树脂材料(underfill resin material)54填充半导体芯片2a和2b以及***式硅衬底53之间的缝隙。
***式硅衬底53通过提供于下表面上的焊盘49、有机***式衬底57上的焊料凸点58和焊接区(lands)59电连接并安装到有机***式衬底57上。用底填树脂材料55填充***式硅衬底53和有机***式衬底57之间的缝隙。
此外，作为另一项技术，日本专利公开No.平8-250653(以下简称专利文献2)披露了一种使用不具有通孔部分的***式硅衬底的SiP方法。图17示出了该SiP的结构。多个半导体芯片62a和62b通过焊料凸点64连接到***式硅衬底61。***式硅衬底61通过安装有半导体芯片62a和62b的同一表面经由焊料凸点65连接到有机***式衬底63。
发明内容
不过，专利文献1的SiP方法需要形成穿透***式硅衬底53的通孔且形成掩埋在通孔中的导电部分56。用于形成通孔的硅蚀刻以及通过在通孔中电镀沉积导电部分56要花费高成本和长周期，这导致了整个半导体器件的制造成本增加的问题。
此外，***式硅衬底53除了微细设计规则符合半导体芯片2a和2b的设计规则的芯片到芯片互连层50之外，在其下表面上还具有焊盘49，焊盘49具有符合有机***式衬底57的设计规则(design rule)的较大间距。由于焊盘49具有这样的大间距，***式硅衬底53在其平面方向中的尺寸易于变大，这也导致了高成本。
在专利文献2的SiP方法中，***式硅衬底61在其安装有半导体芯片62a和62b的同一表面上具有用于连接到有机***式衬底63的焊盘。半导体芯片62a和62b通过形成于***式硅衬底61上的互连连接到有机***式衬底63。因此，半导体芯片62a和62b与有机***式衬底63之间的互连长度易于变大，这容易导致半导体芯片62a和62b与有机***式衬底63之间的信号传输延迟。
此外，***式硅衬底61除了用于把半导体芯片62a和62b彼此连接的互连之外，还具有用于把半导体芯片62a和62b连接到外部(在该例中是有机***式衬底63)的互连。这些引出到外部的互连的存在降低了芯片到芯片互连的路线布局的灵活性，于是芯片到芯片互连的长度易于变大，这易于导致半导体芯片62a和62b之间的信号传输延迟。
考虑到上述问题而做出了本发明，其目的在于提供一种廉价且能够抑制信号传输延迟的半导体器件及其制造方法。
为了解决上述问题本发明采用了以下实施例。
具体而言，根据本发明的一个实施例的半导体器件包括：多个半导体芯片；半导体衬底，在其同一表面上具有用于把所述多个半导体芯片彼此电连接的芯片到芯片互连以及连接到所述芯片到芯片互连的多个芯片连接焊盘；以及布线板，具有多个焊接区，所述焊接区的间距大于所述芯片连接焊盘的间距。所述多个半导体芯片的每个的主表面通过第一连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在半导体衬底上。在所述主表面上除面对所述半导体衬底的区域之外形成外部连接焊盘并通过第二连接器将其连接到所述布线板上的所述焊接区。
此外，根据本发明的另一个实施例的半导体器件包括：多个半导体芯片；以及半导体衬底，在其同一表面上具有用于把所述多个半导体芯片彼此电连接的芯片到芯片互连以及连接到所述芯片到芯片互连的多个芯片连接焊盘。所述多个半导体芯片的每个的主表面通过连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在半导体衬底上。在所述主表面上除面对所述半导体衬底的区域之外形成多个外部连接焊盘，所述外部连接焊盘的间距大于所述芯片连接焊盘的间距。
此外，根据本发明的又一实施例的制造半导体器件的方法包括以下步骤：在半导体衬底的同一表面上形成芯片到芯片互连和多个连接到所述芯片到芯片互连的芯片连接焊盘；以及在多个半导体芯片的主表面上除了面对所述半导体衬底的区域之外形成多个外部连接焊盘。外部连接焊盘具有大于所述芯片连接焊盘的间距的间距。所述方法还包括以下步骤：在布线板上形成多个焊接区，所述焊接区的间距等于所述外部连接焊盘的间距；将所述多个半导体芯片的每个的所述主表面通过第一连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在所述半导体衬底上；以及把所述半导体芯片上的所述外部连接焊盘通过第二连接器连接到所述布线板上的所述焊接区。
所述多个半导体芯片通过形成于所述半导体衬底上的芯片到芯片互连彼此电连接并直接连接到所述布线板，中间没有半导体衬底。
半导体衬底仅仅具有把多个半导体芯片彼此连接的功能。在布线板与焊接到半导体芯片的形成有焊接区的表面相对的表面上，形成符合被称为所谓母板(motherboard)的布线板的设计规则的焊接区。因此布线板充当着互连半导体芯片和母板的内插件(interposer)。
形成于半导体芯片的主表面上的细微和小间距的电极焊盘连接到(重新布置为)外部连接焊盘，该外部连接焊盘具有符合外部的设计规则的尺寸和间距。
不必在半导体衬底上形成其较大的尺寸和间距符合布线板的设计规则的焊盘用于连接到布线板。亦即，半导体衬底上仅仅具有用于连接到半导体芯片的更微细尺寸和间距的芯片连接焊盘作为焊盘就足够了。因此，能够减小半导体衬底的平面尺寸，这使得半导体衬底的成本降低。
半导体芯片通过直接设置于半导体芯片上的外部连接焊盘连接到外部(布线板)，中间不需要半导体衬底。因此，与上述专利文献2(其中，半导体芯片是通过半导体衬底连接到布线板的)相比，能够减小半导体芯片和布线板(wiring board)之间的互连的长度，这能够抑制半导体芯片和布线板之间信号传输的延迟。
此外，就互连而言，半导体衬底上仅仅具有芯片到芯片互连，而没有用于把半导体芯片连接到布线板的互连。因此，可以把芯片到芯片互连集中(collectively)形成在半导体衬底上的特定区域上，而其路线设计不会受到用于把半导体芯片连接到布线板的互连的干扰。因此，能够减小芯片到芯片互连的长度，这使得能够抑制半导体芯片之间的信号传输的延迟。
如果把半导体衬底放在形成于布线板中的空洞(hollow)中，就能够抑制整个半导体器件的厚度增大。此外，如果通过在空洞中提供树脂材料把半导体衬底固定到布线板，就能够减小通过第一和第二连接器作用在焊接部分上的应力，这能够提高焊接部分的焊接可靠性。
此外，如果在把半导体芯片焊接到半导体衬底之前预先把半导体衬底放在形成于布线板中的空洞中，那么可以使用与现有安装方法类似的方法，其中，逐个挑选半导体芯片，以使用比如负压吸引工具(vacuum suction tool)的现有安装装置安装在半导体衬底上。这种方法避免了成本增加和安装效率的降低。
根据本发明的实施例，半导体衬底仅具有把多个半导体芯片彼此电连接的功能，而没有把半导体芯片上的电极焊盘导引到用于连接到外部的具有放大的间距的焊盘的功能。因此，不必形成穿透半导体衬底的通孔以及掩埋在通孔中的导电构件，于是能够相应降低工艺成本和时间。结果，能够降低整个半导体器件的成本。半导体芯片通过直接设置于半导体芯片上的外部连接焊盘连接到外部(布线板)，中间不需要半导体衬底。因此，能够减小半导体芯片和布线板之间的互连的长度，这能够抑制半导体芯片和布线板之间的信号传输的延迟。此外，就互连而言，半导体衬底上仅仅具有芯片到芯片互连，而没有用于把半导体芯片连接到布线板的互连。因此，可以把芯片到芯片互连集中形成在半导体衬底上的特定区域上，而其路线设计不会受到用于把半导体芯片连接到布线板的互连的干扰。因此，能够减小芯片到芯片互连的长度，这使得能够抑制半导体芯片之间的信号传输的延迟。
附图说明
图1为根据本发明第一实施例的半导体器件的局部截面透视图。
图2为根据第一实施例的半导体器件的截面图。
图3为根据第一实施例的半导体器件的制造步骤的第一截面图。
图4为根据第一实施例的半导体器件的制造步骤的第二截面图。
图5为根据第一实施例的半导体器件的制造步骤的第三截面图。
图6为根据第一实施例的半导体器件的制造步骤的第四截面图。
图7为根据第一实施例的半导体器件的制造步骤的第五截面图。
图8为根据第一实施例的半导体器件的制造步骤的第六截面图。
图9为根据本发明第二实施例的半导体器件的局部截面透视图。
图10为根据第二实施例的半导体器件的截面图。
图11为根据第二实施例的半导体器件的制造步骤的第一截面图。
图12为根据第二实施例的半导体器件的制造步骤的第二截面图。
图13为根据本发明第三实施例的半导体器件的截面图。
图14为示出改变的平面图，其中多个半导体芯片安装在半导体衬底上。
图15为截面图，示出了作为本发明实施例的改变的半导体器件。
图16为截面图，示出了作为第一常规例的半导体器件。
图17为截面图，示出了作为第二常规例的半导体器件。
具体实施方式
将参考附图通在下文中详细描述本发明的实施例。应当指出，本发明不限于以下的实施例，而是可以基于本发明的技术思想做出许多改变。
[第一实施例]
图1为示出根据本发明第一实施例的半导体器件1的局部截面透视图。图2为示出半导体器件1的截面图。
半导体器件1包括半导体衬底3、安装在半导体衬底3上的多个半导体芯片2a和2b以及连接到半导体芯片2a和2b的布线板7。
半导体衬底3在其同一表面上具有用于把半导体芯片2a和2b彼此电连接的芯片到芯片互连4以及连接到芯片到芯片互连4的多个芯片连接焊盘5。
半导体芯片2a和2b的主表面(形成IC的表面)通过第一连接器8和9连接到半导体衬底3上的芯片连接焊盘5。于是，半导体芯片2a和2b通过形成于半导体衬底3上的芯片到芯片互连4彼此电连接。半导体芯片2a和2b和半导体衬底3之间的围绕焊接部分的空间被底填树脂材料14填充，该树脂材料14保护着焊接部分。
多个外部连接焊盘13形成于半导体芯片2a和2b的主表面上面对半导体衬底3的区域之外的区域上。多个焊接区6形成于布线板7上。外部连接焊盘13和焊接区6的间距比半导体衬底3上的芯片连接焊盘5的间距(第一连接器8和9的间距)大。外部连接焊盘13通过第二连接器12连接到焊接区6，于是半导体芯片2a和2b被电连接到布线板7。半导体芯片2a和2b和布线板7之间的围绕焊接部分的空间被底填树脂材料15填充，该树脂材料15保护着焊接部分。
以下将描述半导体器件1的制造方法的一例。
参考图3，半导体衬底3为例如硅衬底。在其一个表面上形成的是芯片到芯片互连4和连接到芯片到芯片互连4的多个芯片连接焊盘5。使用典型半导体晶片工艺的技术和设备形成芯片到芯片互连4和芯片连接焊盘5。芯片到芯片互连4具有多层结构，例如绝缘层插置在互连层之间。作为芯片到芯片互连4和芯片连接焊盘5的材料，例如铜或铝就可以。当半导体衬底3由硅形成时，绝缘层可以由氧化硅或氮化硅形成，或者可以由比如聚酰亚胺的树脂材料形成。芯片到芯片互连4可以由单层形成。芯片到芯片互连4具有亚微米(0.1到1μm)量级上的线和空间的图案(line-and-space pattern)(最小的线宽度)。芯片连接焊盘5具有几个微米到60μm范围内的间距。典型的半导体加工工艺能够容易地形成在半导体衬底3(为硅衬底)上具有这样的设计规则的互连和焊盘。
半导体衬底3不限于硅衬底，而是可以是另一种由锗、化合物半导体等构成的半导体衬底。在本实施例中，安装在半导体衬底3上的半导体芯片2a和2b是硅芯片，因此使用硅衬底作为半导体衬底3，以便保证半导体芯片2a和2b以及半导体衬底3之间的线性膨胀系数相匹配。如果半导体衬底3和安装于其上的半导体芯片2a和2b具有相同或接近的线性膨胀系数，就能够抑制当二者经受温度循环时作用于焊接部分上的应力，这可以提高焊接可靠性。因此优选半导体衬底3和半导体芯片2a和2b由同样的材料构成或者由具有接近的线性膨胀系数的材料构成。
接着参考图4，第一连接器9形成于芯片连接焊盘5上。第一连接器9是通过例如电镀或印刷形成的半球形焊料凸点。第一连接器9可以由焊料之外的金属或合金形成，且其形状可以是柱形。
在形成第一连接器9之后，使用背部研磨机(back grinder)抛光半导体衬底3的背面(已经形成有芯片到芯片互连4、芯片连接焊盘5和第一连接器9的表面的相对表面)，于是半导体衬底3被减薄了。随后，使用解理锯、激光或另一种手段沿其厚度方向切割半导体衬底3，使得半导体衬底3被分成单个的芯片。
接着参考图5，多个(在本实施例中为两个)半导体芯片2a和2b通过第一连接器8和9被焊接到经解理的半导体衬底3。
每个半导体芯片2a和2b的主表面(形成IC的表面)其上具有互连10和多个连接到互连10的焊盘11。半导体芯片2a和2b的电极焊盘(未示出)通过互连10连接到焊盘11，焊盘11具有比电极焊盘的间距大的间距。亦即，电极焊盘被重新布置为焊盘11。互连10和焊盘11是在类似于在半导体衬底3上形成芯片到芯片互连4和芯片连接焊盘5的步骤的步骤中形成的。半导体芯片2a和2b上的焊盘11和半导体衬底3上的焊盘5具有相同的间距，且焊盘11和焊盘5的数目是相同的。
半导体芯片2a和2b上的焊盘11其上具有第一连接器(例如焊料凸点)8，第一连接器8类似于半导体衬底3的芯片连接焊盘5上形成的第一连接器9。在连接器8和9彼此接触的时候加热熔化连接器8和9，这使得连接器8和9彼此焊接起来。于是，半导体芯片2a和2b上的互连10电连接到半导体衬底3上的芯片到芯片互连4。于是，两个半导体芯片2a和2b通过半导体衬底3上的芯片到芯片互连4彼此电连接。
半导体衬底3和半导体芯片2a和2b之间的间隙用底填树脂材料14填充，从而覆盖第一连接器8和9附近的焊接部分，这保护了焊接部分免受应力、尘埃、水等的影响。为了形成底填树脂材料14，将例如液体或膏状热固性树脂提供在半导体衬底3和半导体芯片2a和2b之间的间隙中，使芯片2a和2b位于衬底3上方，然后热固化所提供的树脂。
除了用于连接到半导体衬底3的焊盘11之外，每个半导体芯片2a和2b在形成焊盘11的同一表面上还具有多个外部连接焊盘13。外部连接焊盘13与形成焊盘11同时形成，并连接到互连10。外部连接焊盘13位于半导体芯片2a和2b上除面对半导体衬底3的区域之外的区域上，具体而言位于半导体芯片2a和2b的边缘部分上。外部连接焊盘13具有大于焊盘11的尺寸和间距(例如100μm或更大的间距)。外部连接焊盘13通过第二连接器12焊接到图6所示的布线板7。
布线板7是比如玻璃环氧树脂布线板的有机布线板。多个焊接区6形成于布线板7的一个表面上。焊接区6具有与形成于半导体芯片2a和2b上的外部连接焊盘13相同的间距，且其数目也与外部连接焊盘13相同。在布线板7形成焊接区6的相对表面上形成的是多个焊接区17，焊接区17具有比焊接区6的间距大的间距。焊接区6和17通过导电构件18彼此电连接，导电构件18填充形成于布线板7和互连19中的通路。焊接区17是作为焊接区6的重新设置而提供的，于是提供了比焊接区6的间距大的间距。焊接区6和17、导电构件18和互连19由比如铜的金属材料构成。互连19具有多层结构，绝缘层***于互连层之间。
互连19的线和空间图案与焊接区6和17的间距是基于在典型的有机布线板中采用的设计规则的。例如，焊接区6和17的间距至少为100μm。作为布线板7，可以使用由氧化铝等构成的陶瓷布线板而不是有机布线板。
在布线板7的中心部分中形成的是平面尺寸比半导体衬底3大的空洞16，作为在其厚度方向上穿透布线板7的通孔。该空洞16能够由机械工具、激光、蚀刻或另一种手段形成。
在布线板7的焊接区6上形成的是例如作为第二连接器12的焊料凸点。例如，利用焊球支架(mounter)通过转移(transfer)法或另一种方法把焊球固定在焊接区6上，随后通过焊料回流使之变成半球形。或者，第二连接器12可以是通过电镀、印刷等形成的柱金属凸点。
半导体衬底3置于布线板7的空洞16中，第二连接器12接触半导体芯片2a和2b上的外部连接焊盘13。在这种状态下，把第二连接器12加热熔化，将半导体芯片2a和2b上的外部连接焊盘13通过第二连接器12连接到布线板7上的焊接区6。于是就获得了图1和2所示的半导体器件1。
两个半导体芯片2a和2b通过形成于半导体衬底3上的芯片到芯片互连4而彼此电连接，并直接连接到布线板7，中间没有半导体衬底3。
在布线板7与焊接到半导体芯片2a和2b的表面相对的表面上，形成符合被称为所谓母板的布线板的设计规则的焊接区17。因此布线板7起到了互连半导体芯片2a和2b与母板的内插件的功能。半导体衬底3仅仅具有使半导体芯片2a和2b彼此连接的功能。
结果，形成于半导体芯片2a和2b的主表面上的细微且小间距的电极焊盘通过互连10等被连接到(重新布置成)尺寸和间距符合母板的设计规则的焊接区17。
在布线板7的焊接区17上形成的是比如焊球或金属凸点的连接器，而焊接区17通过连接器被连接到形成于母板上的焊接区和互连。除了半导体器件1之外，在母板上还安装了许多部件(其他半导体器件、电阻器、电容器、连接器等)。这些部件通过形成于母板上的互连电连接到半导体器件1。
作为半导体器件的另一种结构，还有如图15所示的没有布线板7的结构。具体而言，半导体芯片2a和2b上的外部连接焊盘13可以通过比如焊球或金属凸点的连接器直接安装在母板上。不过，由于芯片2a和2b的尺寸的限制，半导体芯片2a和2b的外部连接焊盘13不能具有非常大的尺寸和间距。因此，有这种可能性，即，不能把这种直接连接用于具有较大设计规则的母板。因此，优选这样的结构，其中半导体芯片2a和2b上的外部连接焊盘13通过布线板7被重新布置为具有放大的间距的焊接区17，因为这种结构可以避免导致额外成本的母板的微加工。
制造方法不局限于上述例子。如图7所示，在焊盘11和13上分别形成所有第一连接器8和第二连接器12之后，可以在半导体芯片2a和2b上执行半导体芯片2a和2b与半导体衬底3通过第一连接器8的焊接(见图8)以及半导体芯片2a和2b与布线板7通过第二连接器12的焊接。
如上所述，在本实施例的半导体器件1中，半导体衬底3仅具有把多个半导体芯片2a和2b彼此电连接的功能，而没有把半导体芯片2a和2b上的电极焊盘导引到具有扩大的间距的焊盘以连接至外部的功能。因此，与图16所示的常规例不同，不必形成穿透半导体衬底3的通孔以及掩埋在通孔中的导电构件，于是能够相应降低工艺成本和时间。结果，能够降低半导体器件1的总成本。
此外，不必在半导体衬底3上形成其大尺寸和间距符合布线板7的设计规则的焊盘用于连接到布线板7。亦即，半导体衬底3上仅仅具有焊盘5作为焊盘就足够，焊盘5用于连接到半导体芯片2a和2b，因而具有小尺寸和间距。因此，允许半导体衬底3具有小的平面尺寸。这种小的平面尺寸使得半导体衬底3的成本降低。
此外，半导体芯片2a和2b通过直接设置于半导体芯片2a和2b上的外部连接焊盘13连接到布线板7，中间没有半导体衬底3上的互连。因此，与图17所示的常规例(其中半导体芯片62a和62b通过半导体衬底61连接到布线板63)相比，能够减小半导体芯片与布线板之间的互连的长度，这使得能够抑制半导体芯片和布线板之间信号传输的延迟。
此外，至于互连，本实施例的半导体衬底3其上仅具有芯片到芯片互连4而没有如上所述的用于把半导体芯片2a和2b连接到布线板7的互连。因此，可以把芯片到芯片互连4集中形成在半导体衬底3上的特定区域上，而其路线设计不会受到用于把半导体芯片2a和2b连接到布线板7的互连干扰。因此，能够减小芯片到芯片互连4的长度，这使得能够抑制半导体芯片2a和2b之间的信号传输的延迟。
[第二实施例]
图9为示出根据本发明第二实施例的半导体器件21的局部截面透视图。图10为示出半导体器件21的截面图。与第一实施例中相同的部分赋予相同的标号，其详细说明将被省略。
本实施例的半导体器件21包括半导体衬底3、安装在半导体衬底3上的多个半导体芯片2a和2b以及连接到半导体芯片2a和2b的布线板27。
半导体衬底3在其同一表面上具有用于把半导体芯片2a和2b彼此电连接的芯片到芯片互连4以及连接到芯片到芯片互连4的多个芯片连接焊盘5。半导体芯片2a和2b的主表面(形成IC的表面)通过第一连接器8和9连接到半导体衬底3上的芯片连接焊盘5。于是，半导体芯片2a和2b通过形成于半导体衬底3上的芯片到芯片互连4彼此电连接。
多个外部连接焊盘13形成于半导体芯片2a和2b的主表面上面对半导体衬底3的区域之外的区域上。多个焊接区6形成于布线板27上。外部连接焊盘13和焊接区6的间距比半导体衬底3上的芯片连接焊盘5的间距(第一连接器8和9的间距)大。外部连接焊盘13通过第二连接器12连接到焊接区6，于是半导体芯片2a和2b被电连接到布线板27。
半导体衬底3和半导体芯片2a和2b之间的间隙以及半导体芯片2a和2b和布线板27之间的间隙用底填树脂材料24填充，保护着半导体芯片2a和2b与半导体衬底3之间的焊接部分以及半导体芯片2a和2b与布线板27之间的焊接部分。
半导体衬底3用这样的方式置于形成于布线板27中的空洞26中，使得芯片连接焊盘5和形成于芯片连接焊盘5上的第一连接器9暴露于空洞26上方。空洞26被形成为具有底部的凹陷。树脂材料提供于空洞26的内壁表面以及半导体衬底3的底部和侧面之间并把半导体衬底3固定在空洞26中。在空洞26中提供树脂材料可以通过与在半导体芯片2a和2b与半导体衬底3之间以及半导体芯片2a和2b与布线板27之间的间隙中提供材料24一起在其中提供底填树脂材料24而实现。或者，在提供底填树脂材料24之前，可以独立地在其中提供用于空洞26的另一种树脂材料。
如上所述，本实施例具有这样的结构：其中，半导体衬底3掩埋在布线板27中，以便与布线板27成为一体。因此，与第一实施例(其中，半导体芯片2a和2b与半导体衬底3仅仅通过第二连接器12通过焊接部分由布线板7所支撑)相比，通过第二连接器12作用在焊接部分上的应力(具体而言，是在布线板经受温度循环时因为线性膨胀系数大的有机布线板收缩而产生的应力)能够得以减小，这能够提高焊接部分的焊接可靠性。此外，由于半导体衬底3被支撑在布线板27的空洞26之中，因此还可以防止由小尺寸的第一连接器8和9在半导体芯片2a和2b与半导体衬底3之间形成的焊接部分受到过大的应力，这能够提高焊接部分的焊接可靠性。结果，与第一实施例相比，可以提高半导体芯片2a和2b、半导体衬底3和布线板27之间的焊接的可靠性。
第二实施例的其他优点与第一实施例相同。
将参考图11和12描述根据第二实施例的半导体器件21的制造方法例。
如图11所示，在布线板27的中心部分形成的是空洞26，空洞26的平面尺寸稍大于半导体衬底3，作为具有底部的凹陷。这个空洞26能够通过机械工具、激光、蚀刻或另一种方法形成。
在把液态或糊状树脂材料供应在空洞26的底部和侧壁表面上之后，把半导体衬底3放在空洞26中，如图12所示，然后把树脂材料例如加热固化，以便把半导体衬底3固定到布线板27。或者，可以在把半导体衬底3放在空洞26中之后，在半导体衬底3和空洞26之间的间隙中提供树脂材料，然后可以加以固化。
在这种状态下，通过第一连接器8和9把半导体芯片2a和2b焊接到半导体衬底3上的芯片连接焊盘5，芯片连接焊盘5稍稍位于其上已经形成有焊接区6的布线板27的表面上方。与这一焊接同时，把半导体芯片2a和2b上的外部连接焊盘13通过第二连接器12焊接到布线板27上的焊接区6。将第一和第二连接器8、9和12设置足够的高度，允许半导体衬底3上的芯片连接焊盘5与形成焊接区的布线板27的表面同高，或者位于形成焊接区的表面的稍下方，即，位于空洞26中。
如果在半导体芯片2a和2b与半导体衬底3之间的焊接之前预先把半导体衬底3这样掩埋在布线板27中并固定到其上，就能够逐个挑选半导体芯片2a和2b，以使用现有的安装设备，比如负压吸引工具将其安装在半导体衬底3上。
相反，如果预先把半导体芯片2a和2b焊接到半导体衬底3上，然后把所得的组件焊接到布线板27，那么就存在以下的问题。具体而言，在把所得的组件焊接到布线板27期间，当负压吸引多个半导体芯片2a和2b时，可能会因为从芯片间的间隙漏气而导致吸引失效。此外，为了防止被吸引的组件相对于空洞26中的焊接表面倾斜，必须要使多个半导体芯片2a和2b的厚度均衡。
另一方面，如果如上所述预先把半导体衬底3掩埋在布线板27中，就能够使用负压吸引工具逐个挑选半导体芯片2a和2b并以现有方式安装在半导体衬底3上。
[第三实施例]
图13示出了根据本发明第三实施例的半导体器件31。与第一和第二实施例中相同的部分赋予相同的标号，其详细说明将被省略。
本实施例的半导体器件31包括半导体衬底3、安装在半导体衬底3上的多个半导体芯片2a和2b以及连接到半导体芯片2a和2b的布线板37。
半导体衬底3在其同一表面上具有用于把半导体芯片2a和2b彼此电连接的芯片到芯片互连4以及连接到芯片到芯片互连4的多个芯片连接焊盘5。半导体芯片2a和2b的主表面(形成IC的表面)通过第一连接器8和9连接到半导体衬底3上的芯片连接焊盘5。于是，半导体芯片2a和2b通过形成于半导体衬底3上的芯片到芯片互连彼此电连接。
多个外部连接焊盘13形成于半导体芯片2a和2b的主表面上面对半导体衬底3的区域之外的区域上。多个焊接区6形成于布线板37上。外部连接焊盘13和焊接区6的间距比半导体衬底3上的芯片连接焊盘5的间距(第一连接器8和9的间距)大。外部连接焊盘13通过第二连接器38连接到焊接区6，于是半导体芯片2a和2b被电连接到布线板37。
半导体衬底3和半导体芯片2a和2b之间的间隙以及半导体芯片2a和2b和布线板37之间的间隙用底填树脂材料36填充，保护着半导体芯片2a和2b与半导体衬底3之间的焊接部分以及半导体芯片2a和2b与布线板37之间的焊接部分。
在本实施例中，半导体衬底3未被放在布线板37中，而是安装在布线板37的其上已形成焊接区6的表面上。因此，与第一和第二实施例不同，不必在布线板中形成空洞，这能够相应地减少工艺成本和时间。不过，与第一和第二实施例相比，在减小整个半导体器件的厚度方面第三实施例存在缺点，在第一和第二实施例中半导体衬底3分别位于布线板7和27中。
此外，在半导体芯片2a和2b上的外部连接焊盘13与布线板37上的焊接区6之间的距离大，这不可避免地要求连接它们的第二连接器38相应具有大尺寸。这些大的第二连接器38迫使外部连接焊盘13和焊接区6具有大尺寸和间距。相反，第一和第二实施例允许第二连接器12、外部连接焊盘13和焊接区6比第三实施例具有更小的尺寸和间距，因此能够实现小平面尺寸。
安装在半导体衬底3上的半导体芯片数目不局限于两个，而是可以是三个或更多。图14示出了一个例子，其中四个半导体芯片70a到70d安装在半导体衬底3上。在多个半导体芯片70a到70d中，举例来说，一个半导体芯片充当存储元件，而另一个半导体芯片充当逻辑元件。只要该多个芯片中至少一个半导体芯片连接到外部布线板，这些半导体芯片70a到70d就可以包括不直接连接到外部布线板的半导体芯片70b。
尽管已经使用特定术语描述了本发明的优选实施例，但是这样的描述仅仅出于说明目的，应当理解，在不背离权利要求的精神或范围的情况下可以做出改变和变化。
本发明包含与2005年3月16日在日本专利局提交的日本专利申请JP2005-075165相关的主题，在此将其全文引入以做参考。

Claims (6)

1.一种半导体器件，包括：
多个半导体芯片；
半导体衬底，在其同一表面上具有用于把所述多个半导体芯片彼此电连接的芯片到芯片互连以及连接到所述芯片到芯片互连的多个芯片连接焊盘；以及
布线板，具有多个焊接区，所述焊接区的间距大于所述芯片连接焊盘的间距，其中
所述多个半导体芯片的每个的主表面通过第一连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在所述半导体衬底上，且
在所述主表面上除面对所述半导体衬底的区域之外形成有外部连接焊盘并通过第二连接器将其连接到所述布线板上的所述焊接区。
2.根据权利要求1的半导体器件，其中
所述半导体衬底位于形成于所述布线板中的空洞中。
3.根据权利要求2的半导体器件，其中
以围绕所述半导体衬底的方式在所述空洞中提供树脂材料，且把所述半导体衬底通过所述树脂材料焊接到所述布线板。
4.一种半导体器件，包括：
多个半导体芯片；以及
半导体衬底，在其同一表面上具有用于把所述多个半导体芯片彼此电连接的芯片到芯片互连以及连接到所述芯片到芯片互连的多个芯片连接焊盘，其中
所述多个半导体芯片的每个的主表面通过连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在所述半导体衬底上，且
在所述主表面上除面对所述半导体衬底的区域之外形成有多个外部连接焊盘，所述外部连接焊盘的间距大于所述芯片连接焊盘的间距。
5.一种制造半导体器件的方法，包括以下步骤：
在所述半导体衬底的同一表面上形成芯片到芯片互连和多个连接到所述芯片到芯片互连的芯片连接焊盘；
在多个半导体芯片除面对所述半导体衬底的区域之外的主表面上形成多个外部连接焊盘，所述外部连接焊盘的间距大于所述芯片连接焊盘的间距；
在布线板上形成多个焊接区，所述焊接区的间距等于所述外部连接焊盘的间距；
将所述多个半导体芯片的每个的所述主表面通过第一连接器连接到所述芯片连接焊盘，以便把所述多个半导体芯片安装在所述半导体衬底上；以及
把所述半导体芯片上的所述外部连接焊盘通过第二连接器连接到所述布线板上的所述焊接区。
6.根据权利要求5的制造半导体器件的方法，其中
在把所述半导体芯片安装在所述半导体衬底上之前，把所述半导体衬底安装在所述布线板上或放在所述布线板中，使所述芯片连接焊盘在与所述布线板的其上具有所述焊接区的表面的同一侧暴露。
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CN113855032A (zh) * 2021-09-13 2021-12-31 江西脑虎科技有限公司 一种脑电极器件的制备方法及脑电极器件

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JP4581768B2 (ja) 2010-11-17
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