CN102804364A - 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的*** - Google Patents

封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的*** Download PDF

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CN102804364A
CN102804364A CN2010800287406A CN201080028740A CN102804364A CN 102804364 A CN102804364 A CN 102804364A CN 2010800287406 A CN2010800287406 A CN 2010800287406A CN 201080028740 A CN201080028740 A CN 201080028740A CN 102804364 A CN102804364 A CN 102804364A
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chip
stack
tube core
tsv
flip
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CN102804364B (zh
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S·穆萨库玛
C·A·盖勒
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Intel Corp
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Intel Corp
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Abstract

一种层叠芯片装置包括封装衬底和***件，其中芯片叠层设置有间隙，该间隙匹配于该***件。一种封装体堆叠层叠芯片装置包括设置在***件上的顶部封装体。

Description

封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的***
技术领域
所公开的实施例涉及半导体微电子器件及其封装工艺。
附图简述
为了理解获得实施例的方式，将通过参照附图提供对以上简述的多个实施例的更具体描述。这些附图描绘了不一定按比例绘制的实施例，且不应被认为是对范围的限制。将通过使用附图更为具体且详细地描述并说明一些实施例，在附图中：
图1a是根据示例实施例的用于层叠管芯封装体的安装衬底和***件装置的横截面图；
图1b是根据实施例的图1a中描述的该装置在进一步处理之后的横截面图；
图1c是根据实施例的图1b中描述的该装置在进一步处理之后的横截面图；
图1d是根据实施例的图1c中描述的该装置在进一步处理之后的横截面图；
图1e是根据示例实施例的已与进一步处理之后的图1d中描述的该装置相组合的封装体堆叠层叠芯片装置的横截面图；
图2a是根据示例实施例的用于层叠管芯封装体的安装衬底和***件装置的横截面图；
图2b是根据示例实施例的从进一步处理之后的图2a中描述的该装置组合而来的封装体堆叠层叠芯片装置的横截面图；
图3a是根据示例实施例的在处理期间的混合管芯装置的横截面图；
图3b是根据实施例的图3a中描述的该装置在进一步处理之后的横截面图；
图4是根据示例实施例的用于层叠管芯封装体的***件装置的横截面图；
图5是根据实施例的将支承封装体堆叠装置的混合管芯装置的横截面图；
图6是根据实施例的将支承封装体堆叠混合管芯装置的混合管芯装置的横截面图；
图7是根据实施例的将支承封装体堆叠装置的混合管芯装置的横截面图；
图8是根据示例实施例的制程和方法流程图；以及
图9是根据实施例的计算机***的示意图。
具体描述
现将参照附图，在附图中可能向相似结构提供了相似的下标附图标记。为了最清楚地示出多个实施例的结构，本文中所包含的附图是集成电路结构的图解表示。因此，所制造结构的实际外观(例如显微照片中的实际外观)可能有所不同，但仍包含声明要求保护的所示实施例的结构。此外，附图可能仅示出理解所示实施例所必需的结构。本领域已知的附加结构未被包括在内，以保持附图的清楚。尽管在同一句子中可能提到处理器芯片和存储器芯片，但应当理解它们是等效结构。
本说明书通篇中，对“一个实施例”或“一实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。因此，在本公开内容通篇中的多个位置中，短语“在一个实施例中”或“在实施例中”的出现不一定全部指的是同一实施例。而且，特定特征、结构、或特性可按照任何合适的方式在一个或多个实施例中组合。
通过参照X-Z或Y-Z坐标可理解诸如“上方”和“下方”之类的术语，且通过参照所示X-Y坐标可理解诸如“毗邻”之类的术语。
图1a是根据示例实施例的用于层叠管芯封装体的安装衬底和***件装置100的横截面图。以分解图垂直地(Z方向)描绘该装置100，该装置100包括封装衬底110和***件130。封装衬底110包括用于接受处理器的管芯面112，以及用于耦合至诸如板之类的外部通信的底面(land side)114。该“板”可以是用于诸如无线通信装置之类的手持设备的外部或近外部结构。该封装衬底110包括在该管芯面112上的底部芯片覆盖区域116。在本文所公开的后续附图中，通过将所示处理器投影到所示安装衬底的相应诸个管芯面，可查明该底部芯片覆盖区域116。
封装衬底110包括底面球栅阵列，该球栅阵列的一个球形焊盘用附图标记118表示。在一实施例中，该球形焊盘118包括表面精整层120。该表面精整层120被配置为是比球形焊盘118更少负电性的金属。根据一实施例，该表面精整层120通过电镀形成。替代地，该表面精整层120通过无电镀覆形成。
在一示例实施例中，球形焊盘118是铜，且表面精整层120是镀在铜上的镍-钯-金合金。在一实施例中，该表面精整层120是镀在铜上的镍-金合金。在一实施例中，该表面精整层120是镀在铜上的铜-金。
在一示例实施例中，球形焊盘118是铜，且表面精整层120是诸如芳基-苯基咪唑之类的有机保焊剂(OSP)组合物。在一示例实施例中，表面精整层120具有从
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到
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的厚度，且为芳基-苯基咪唑。
类似地，封装衬底110包括管芯面球栅阵列，该球栅阵列的一个球形焊盘用附图标记122表示，且该球形焊盘122包括表面精整层124。球形焊盘122和表面精整层124可以是与板面114上存在的那些球形焊盘和表面精整层相似的实施例。在一实施例中，管芯面球栅阵列122由阻焊剂126所限定。类似地，阻焊剂126可限定在底部芯片覆盖区域116内存在的管芯凸点焊盘，且其中一个管芯凸点焊盘用附图标记128表示。封装衬底110被描绘为位于管芯面112与底面114之间，并具有互连和中间层介电结构，这些互连和中间层介电结构是说明性而非限制性的。
该装置100组装有***件130，该***件130与管芯面球栅阵列122配合。***件130包括管芯面132和顶面134，且具有偏移高度136，该偏移高度136被配置成匹配于封装衬底110上方的偏移高度138，该偏移高度138用于将占据底部芯片覆盖区域116的多管芯叠层(MDS)。***件130可包括芯140和互连142。在一实施例中，管芯面电气凸点144和顶面电气凸点146耦合至互连142。
图1b是根据实施例的图1a中描述的该装置在进一步处理之后的横截面图。装置101示出了***件偏移高度136匹配于封装衬底偏移高度138(图1a)。底部芯片覆盖区域116被***件130所包围，且将包围该多管芯叠层，该多管芯叠层将被组装作为装置101的一部分。
图1c是根据实施例的图1b中描述的该装置在进一步处理之后的横截面图。装置102已经由***件填充材料148所加固，该***件填充材料148使封装衬底110与***件130之间的接合变得稳定。
底部芯片150被放置在底部芯片覆盖区域116内(图1b)。在一实施例中，底部芯片150是倒装芯片150，该倒装芯片150已通过芯片球阵列倒装接合，该芯片球阵列的一个电气凸点通过标记152表示。在一实施例中，底层填料154已经被流入以加固底部芯片150与封装衬底110之间的接合。在制程实施例中，在底层填料154的固化期间同时，进行电气凸点152的回流。在制程实施例中，在填料材料148的固化期间同时，进行电气凸点152的回流。
在实施例中，底部芯片150经处理以回流电气凸点152，然后在凸点回流之后放置底层填料154。
图1d是根据实施例的图1c中描述的该装置在进一步处理之后的横截面图。图1c中描绘的该装置102已被进一步处理以获得混合管芯装置103，该混合管芯装置103将成为封装体堆叠(PoP)层叠芯片装置的一部分。该混合管芯装置103包括管芯间粘合剂156，该管芯间粘合剂156已被形成在底部芯片150上，且顶部芯片158已被安装在该粘合剂156上。顶部芯片158由底部芯片150所支承。在下文中，从设置在封装衬底110上的底部芯片(例如芯片150)开始且以后续芯片(例如芯片158)结束的芯片叠层也可称为3维(3D)芯片叠层。
在实施例中，顶部芯片158通过引线接合被耦合至封装衬底110，其中一条引线接合通过附图标记160表示。因此，混合叠层装置103包括安装在封装衬底110上的倒装芯片150，以及设置在倒装芯片150上方的引线接合芯片158。因此，***件130的偏移高度136容纳混合叠层的高度，该混合叠层的高度包括引线接合160以及顶部芯片158、粘合剂156、底部芯片150以及电气凸点152所产生的偏移(参见图1c中)。
在制程实施例中，已填充叠层密封剂162，以隔离混合管芯叠层，并进一步防止引线接合160的移动。叠层密封剂162也可被用于保护混合管芯叠层免遭环境和处理危害。叠层密封剂162也可被用于利于从混合管芯叠层向外的热交换。在一实施例中，未使用叠层密封剂。
在一实施例中，底部芯片150是处理器，且顶部芯片158是射频(RF)器件。该混合管芯叠层可在诸如智能电话之类的无线通信装置(例如蜂窝电话)中使用。
图1e是根据示例实施例的已与进一步处理之后的图1d中描述的装置相组合的封装体堆叠(PoP)层叠芯片装置104的横截面图。底部芯片150和顶部芯片158被安置在***件偏移136内，且顶部封装体164已与***件130的顶面134配合。顶部封装体164可能具有安装衬底170，用于与底部芯片150和/或顶部芯片158的通信。顶部封装体164被描绘为引线接合启用解决方案，诸如对于原始设备制造商的情形。在顶部封装体164中描绘了两个引线接合管芯。位于顶部封装体164中的管芯可被称为微电子器件。在一实施例中，设置图1d中所描绘的混合叠层装置103以容纳诸如用于智能电话之类的顶部封装体164，其中，智能电话专属的微电子器件在顶部封装164中，并且，支承微电子器件在芯片叠层中。
在实施例中，顶部封装体填充材料172使***件130与顶部封装体164之间的接合变得稳定。
可以看出，***件偏移136已容纳了底部芯片150和顶部芯片158的混合叠层，以使顶部封装体164不与该混合叠层相抵触。由此，该PoP层叠芯片装置被组装以足够的***件偏移136以容纳芯片叠层的偏移高度，该芯片叠层的偏移高度可能随特定应用而有所变化。
图2a是根据示例实施例的用于层叠管芯封装体的安装衬底和***件装置200的横截面图。装置200类似于图1d中描绘的装置103，且已通过在封装衬底210上安置***件230而类似地被处理。
描绘了层叠芯片装置200。层叠芯片装置200包括底部芯片250和顶部芯片258。在一实施例中，底部芯片250是处理器，且顶部芯片258是通过硅通孔(TSV)技术耦合的存储器管芯。在虚线圆中详细描绘了单个TSV274。在一实施例中，顶部芯片258是2级(L2)存储器高速缓存(其中L0和L1在处理器250内)，诸如用于处理器250的静态随机存取存储器(SRAM)。底部芯片250和顶部芯片258是3D
因此，层叠芯片装置200包括安装在封装衬底210上的倒装芯片250，以及设置在倒装芯片250上方的通过TSV耦合的芯片258。因此，***件230的偏移高度236容纳了层叠芯片配置的高度。底部芯片20的制程可通过关于图1c和其它位置中所描绘的底部芯片150而公开的任一实施例来完成。
在一实施例中，顶部芯片258是诸如随机存取存储器(RAM)管芯258之类的存储器管芯。在一实施例中，顶部芯片258是诸如动态随机存取存储器(DRAM)管芯258之类的存储器管芯。在一实施例中，顶部芯片258是诸如静态随机存取存储器(SRAM)管芯258之类的存储器管芯。在一实施例中，顶部芯片258是诸如可擦除可编程存储器(EPROM)管芯258之类的存储器管芯。根据特定应用，可使用其它存储器管芯配置。
在实施例中，顶部芯片258包括射频器件(RF)标签。在实施例中，顶部芯片258包括用于无线通信的射频器件。
在制程实施例中，已填充叠层密封剂262以隔离该芯片叠层。叠层密封剂262也可用于保护芯片叠层免遭环境和处理危害。叠层密封剂262也可用于利于从芯片叠层向外的热交换。在一实施例中，未使用叠层密封剂。
图2b是根据示例实施例的从进一步处理之后的图2a中描述的该装置组合而来的PoP层叠芯片装置201的横截面图。底部芯片250和顶部芯片258被安置在***件偏移236内，且顶部封装体264已与***件230的顶面234配合。顶部封装体264可能具有安装衬底270，用于与底部芯片250和/或顶部芯片258的通信。顶部封装体被描绘为TSV启用解决方案，诸如对于原始设备制造商的情形。在一实施例中，设置图2a中描绘的芯片叠层装置200以容纳诸如用于智能电话的顶部封装体264。
可以看出，***件偏移236已容纳了底部芯片250和顶部芯片258的芯片叠层，以使顶部封装体264不与该芯片叠层相抵触。
通过适当地观测图2b中所描绘的相似结构和空间，也可推断出关于图1e所说明和描述的细节。
现可理解，用于获得PoP层叠芯片装置201的制程可类似于图1e中所描绘的用于获得PoP层叠芯片装置104的制程。
在一示例实施例中，底部芯片150与顶部芯片158之间的I/O密度在每管芯128位(诸如当顶部芯片258是DRAM管芯时)与252位/管芯之间的范围中。在一示例实施例中，处理器250与后续的芯片258之间的I/O速度在10Gb/s与1Tb/s(每秒万亿位)之间。沿后续的芯片250(如DRAM器件)的10mm边缘部分，总带宽为160GB/s至320GB/s。根据一个实施例，作为封装体，PoP装置201具有640GB/s至6400GB/s之间的总封装体带宽，其中处理器250和后续的芯片258均在256位或在高于256位上操作。该I/O速度可低于10Gb/s(诸如低于7Gb/s)，其中给定的应用可能在此范围有用。
图3a是根据示例实施例的在处理期间的混合管芯装置300的横截面图。底部芯片350放置在封装衬底310上，该封装衬底310可类似于图1c中描绘的封装衬底110。在一实施例中，底部芯片350是倒装芯片350，该倒装芯片350已通过芯片球阵列倒装接合，该芯片球阵列的一个电气凸点通过标记352表示。在一实施例中，底层填料354已经被流入以加固底部芯片350与封装衬底310之间的接合。在一制程实施例中，在底层填料354的固化期间同时，进行电气凸点352的回流。
底部芯片350的制程可通过关于底部芯片150、250和本公开内容中其它位置中公开的任一实施例来完成。
图3b是根据实施例的图3a中描述的该装置在进一步处理之后的横截面图。图3b中描绘的该装置301已被进一步处理以获得混合叠层装置301，该混合叠层装置301将成为PoP层叠芯片装置的一部分。该混合叠层装置301包括管芯间粘合剂356，该管芯间粘合剂356已被形成在底部芯片350上，且顶部芯片358已被安装在该粘合剂156上。顶部芯片358由底部芯片350所支承。
在一实施例中，顶部芯片358通过引线接合而耦合至封装衬底310，其中一条引线接合通过附图标记360表示。因此，混合叠层装置301包括安装在封装衬底310上的倒装芯片350，以及设置在倒装芯片350上方的引线接合芯片358。在进一步处理中，通过***件的偏移高度来匹配偏移高度336。现在将清楚，该混合叠层的组装先于***件至封装衬底310的组装。
与图1d中描绘的混合管芯叠层装置实施例相似，要组装的***件将容纳该混合管芯叠层的高度，该混合管芯叠层的高度包括引线接合360以及顶部芯片358、粘合剂356、底部芯片350和电气凸点352所产生的偏移。在一实施例中，未使用叠层密封剂。
在一实施例中，底部芯片350是处理器，且顶部芯片358是RF器件。该混合管芯叠层可在诸如智能电话之类的无线通信装置中使用。通过适当地观测图3b中所描绘的相似结构和空间，也可推断出之前相对于所公开的实施例所说明和描述的细节。此外，相对于图3b中所描绘和描述的PoP层叠芯片实施例，可推断出之前公开的I/O和带宽能力。
图4是根据示例实施例的用于层叠管芯封装体的***件装置400的横截面图。该装置400类似于图2a中描绘的装置200，除了在层叠管芯450和458的组装之后进行***件的组装。
描绘了层叠芯片装置400。层叠芯片装置400包括底部芯片450和顶部芯片458。在一实施例中，底部芯片450是处理器，且顶部芯片458是通过硅通孔(TSV)技术耦合的存储器管芯。在虚线圆中详细描绘了单个TSV474。在实施例中，顶部芯片558是2级(L2)存储器高速缓存(其中L0和L1在处理器450内)，诸如用于处理器450的诸如静态随机存取存储器(SRAM)。底部芯片450的制程可通过关于底部芯片150、250、350和本公开内容中其它位置中公开的任一实施例来完成。
因此，层叠芯片装置400包括安装在封装衬底410上的倒装芯片450，以及设置在倒装芯片450上方的通过TSV耦合的芯片458。通过将被组装的***件来匹配层叠芯片450和458的偏移高度436。因此，该***件将容纳该层叠芯片配置的高度。
在一实施例中，顶部芯片458是诸如随机存取存储器(RAM)管芯458之类的存储器管芯。在一实施例中，顶部芯片458是诸如动态随机存取存储器(DRAM)管芯458之类的存储器管芯。在一实施例中，顶部芯片458是诸如静态随机存取存储器(SRAM)管芯458之类的存储器管芯。在一实施例中，顶部芯片458是诸如可擦除可编程存储器(EPROM)管芯458之类的存储器管芯。根据特定应用，可使用其它存储器管芯配置。
在一实施例中，顶部芯片458包括射频器件(RF)标签。在一实施例中，顶部芯片458包括用于无线通信的射频器件。在一制程实施例中，叠层密封剂将被填充到凹部中，该凹部将由***件形成在芯片叠层周围。
通过适当地观测图4中所描绘的相似结构和空间，也可推断出之前关于所公开的实施例所说明和描述的细节。此外，相对于图4中所描绘和描述的PoP层叠芯片实施例，可推断出之前公开的I/O和带宽能力。
图5是根据实施例的将支承封装体堆叠装置的混合管芯装置500的横截面图。该混合管芯装置500包括底部芯片550、顶部芯片558以及中间芯片551。顶部芯片558和中间芯片551由底部芯片550所支承。底部芯片550是可称为第一芯片的倒装芯片，中间芯片551是可称为第二芯片551的通过TSV耦合的芯片，顶部芯片558是可称为后续芯片558的引线接合芯片。在一实施例中，紧邻设置在底部芯片550上方的通过TSV耦合的芯片的数量在2到8的范围内，然后是顶部芯片556。底部芯片550的制程可通过相对于本公开内容中描绘的底部芯片所公开的任一实施例来完成。
在一实施例中，顶部芯片558通过引线接合而被耦合至封装衬底510，其中一条引线接合通过附图标记560表示。因此，***件530的偏移高度536容纳混合管芯叠层的高度，该混合管芯叠层的高度包括引线接合560以及顶部芯片558、中间芯片551、底部芯片550以及电气凸点和芯片间粘合剂和间隔件所产生的偏移，如图所示。
在制程实施例中，已填充叠层密封562，以隔离混合管芯叠层，并进一步防止引线接合560的移动。叠层密封剂562也可用于保护混合管芯叠层免遭环境和处理危害。叠层密封剂562也可用于利于从混合管芯叠层向外的热交换。在一实施例中，未使用叠层密封剂。
在一实施例中，第一芯片550是处理器，中间芯片551是TSV RAM芯片，顶部芯片558是RF器件。该混合管芯叠层可在诸如智能电话之类的无线通信装置中使用。
通过适当地观测图5中所描绘的相似结构和空间，也可推断出之前相对于所公开的实施例所说明和描述的细节。此外，相对于图5中所描绘和描述的PoP层叠芯片实施例，可推断出之前所公开的I/O和带宽能力。
图6是根据实施例的将支承PoP混合管芯装置的混合管芯装置600的横截面图。该混合管芯装置600包括底部芯片650、顶部芯片659以及若干中间芯片651、653和658。顶部芯片659和中间芯片651、653和658由底部芯片650所支承。底部芯片650的制程可通过相对于本公开内容中所描绘的底部芯片所公开的任一实施例来完成。
混合管芯装置600是具有多个TSV芯片和多个引线接合芯片的实施例。底部芯片650是可被称为第一芯片的倒装芯片。中间芯片651是可被称为第二芯片651的通过TSV耦合的芯片。中间芯片653是可被称为第三芯片653的通过TSV耦合的芯片。中间芯片658是可被称为第四芯片658的引线接合芯片。并且，顶部芯片659是可被称为后续芯片659的引线接合芯片。在一实施例中，紧邻设置在底部芯片550上方和引线接合芯片658下方的通过TSV耦合的芯片的数量在从2到8的范围内。
在一实施例中，引线接合芯片658和引线接合芯片559分别通过引线接合660和661而耦合至封装衬底610。因此，***件630的偏移高度636容纳混合管芯叠层的高度，该混合管芯叠层的高度包括引线接合660和661以及整个芯片叠层、电气凸点、芯片间粘合剂和间隔件，如图所示。
在制程实施例中，已填充叠层密封剂662，以隔离混合管芯叠层，并进一步防止接合线660和661的移动。叠层密封剂662也可用于保护混合管芯叠层免遭环境和处理危害。叠层密封剂662也可用于利于从混合管芯叠层向外的热交换。在一实施例中，未使用叠层密封剂。
通过适当地观测图6中所描绘的相似结构和空间，也可推断出之前相对于所公开的实施例所说明和描述的细节。此外，相对于图6中所描绘和描述的PoP层叠芯片实施例，可推断出之前公开的I/O和带宽能力。
图7是根据实施例的将支承封装体堆叠装置的混合管芯装置700的横截面图。该混合管芯装置700包括底部芯片750、顶部芯片759以及若干中间芯片751、753和758。顶部芯片759和中间芯片751、753和758由底部芯片750所支承。混合管芯装置700是具有多个TSV芯片和多个引线接合芯片的实施例，其中引线接合芯片在TSV芯片下方。
底部芯片750是可被称为第一芯片的倒装芯片。中间芯片751是可被称为第二芯片751的通过TSV耦合的芯片。中间芯片758是可被称为第三芯片758的引线接合芯片。中间芯片753是可被称为第四芯片753的通过TSV耦合的芯片。并且，顶部芯片759是可被称为后续芯片759的引线接合芯片。在一实施例中，第二芯片751是支承底部芯片750的存储器高速缓存芯片。底部芯片750的制程可通过相对于本公开内容中描绘的底部芯片所公开的任一实施例来完成。
在一实施例中，第四芯片753是支承后续芯片759的TSV存储器高速缓存芯片。在示例实施例中，混合管芯装置700是诸如超级智能电话之类的PoP层叠芯片装置的一部分。在此实施例中，底部芯片750是处理器，且第二芯片751是存储器高速缓存。中间芯片758是用于处理在线通信的引线接合器件。顶部芯片759是由第四芯片753所支承的全球定位***(GPS)芯片，该第四芯片753充当该GPS芯片759的高速缓存。此外，在示例实施例中，顶部封装体
在一实施例中，第四芯片753被用作支承件，且被用作中间芯片758与顶部芯片759之间的接口。例如，第四芯片753具有TSV，该TSV允许顶部芯片759与中间芯片758之间的直接通信。
在一实施例中，引线接合芯片758和引线接合芯片759分别通过引线接合760和761耦合至封装衬底710。因此，***件730的偏移高度736容纳混合管芯叠层的高度，该混合管芯叠层的高度包括引线接合760和761以及整个芯片叠层、电气凸点、芯片间粘合剂和间隔件，如图所示。
在制程实施例中，已填充叠层密封剂762，以隔离混合管芯叠层，并进一步防止接合线760和761的移动。叠层密封剂662也可用于保护混合管芯叠层免遭环境和处理危害。叠层密封剂762也可用于利于从混合管芯叠层向外的热交换。在一实施例中，未使用叠层密封剂。
通过适当地观测图6中所描绘的相似结构和空间，也可推断出之前相对于所公开的实施例所说明和描述的细节。此外，相对于图6中所描绘和描述的PoP层叠芯片实施例，可推断出之前公开的I/O和带宽能力。
图8是根据示例实施例的制程和方法流程图800。
在810，制程包括在封装衬底上形成***件。该***件被配置成具有偏移，该偏移将匹配于要被放置在该封装衬底上的芯片叠层。
在820，该制程包括在封装衬底上形成芯片叠层。在制程820先于制程810的情况下，在形成芯片叠层之后，该***件被放置在封装衬底上。在制程820在制程810之后的情况下，该芯片叠层在***件留下的凹部内形成。在一实施例中，该制程开始于810，结束于820。
在830，该制程包括填充叠层密封剂以隔离该芯片叠层。在一实施例中，该制程开始于810，结束于830。
在840，该制程包括在***件上形成顶部封装体。在一实施例中，该制程开始并结束于840。
图9是根据实施例的计算机***900的示意图。如所描绘，计算机***900(也称为电子***900)可具体实现如本公开内容中所陈述的若干公开实施例中的任一个实施例及其等价方案的PoP层叠芯片装置。在一实施例中，电子***900是计算机***，该计算机***包括***总线920，用于将电子***900的多个部件电耦合。根据多个实施例，***总线920是单个总线或总线的任意组合。电子***900包括提供功率至集成电路910的电压源930。在一些实施例中，电压源930通过***总线920向集成电路910提供电流。
根据一实施例，集成电路910电耦合至***总线920，且包括任何电路或电路的组合。在一实施例中，集成电路910包括任何类型的处理器912。如本文中所使用，处理器912可表示任何类型的电路，诸如但不限于微处理器、微控制器、图形处理器、数字信号处理器或另一种处理器。在一实施例中，在处理器的存储器高速缓存中存在SRAM实施例。可包含在集成电路910中的其他类型的电路为定制电路或专用集成电路(ASIC)，诸如：用于诸如蜂窝电话、寻呼机、便携式计算机、双向无线电之类的无线设备以及类似电子***中的通信电路914。在一实施例中，处理器910包括诸如静态随机存取存储器(SRAM)之类的管芯上存储器916，且该SRAM可包括具有存取和拉低区的独立S/D区的6T SRAM单元。在一实施例中，处理器910包括诸如嵌入动态随机存取存储器(eDRAM)之类的嵌入管芯上存储器916。
在一实施例中，电子***900还包括外部存储器940，该外部存储器940又可包括适合于特定应用的一个或多个存储器元件，诸如RAM形式的主存储器942、一个或多个硬驱动器944、和/或处理可移除介质的一个或多个驱动器946(诸如软磁盘、光盘(CD)、数字多功能盘(DVD)、快闪存储器驱动器以及本领域已知的其他可移除介质)。根据一实施例，外部存储器940也可以是嵌入存储器948，诸如嵌入在处理器安装衬底中的微电子管芯。
在一实施例中，电子***900还包括显示设备950、音频输出960。在一实施例中，电子***900包括诸如控制器970之类的输入设备，其可以是键盘、鼠标、轨迹球、游戏控制器、麦克风、语音识别设备、或向电子***900中输入信息的任何其他输入设备。
如本文中所示，集成电路910可按照多种不同实施例来实现，包括根据若干公开的实施例中的任一实施例及其等价方案的PoP层叠芯片装置、电子***、计算机***、一种或多种制造集成电路的方法、以及一种或多种制造包括根据如本文多个实施例中陈述的若干公开实施例中的任一实施例及其业内认可等价方案的PoP层叠芯片装置的电子组件的方法。根据所公开的若干PoP层叠芯片装置实施例及其等价方案，元件、材料、几何形状、尺寸以及操作顺序均可改变以适合特定I/O耦合要求，这些要求包括处理器安装衬底中所嵌入的微电子管芯的阵列触点数、阵列触点配置。
提供摘要以符合37C.F.R.§1.72(b)，该法条要求存在摘要，以允许读者快速地查明技术公开内容的本质和要点。该摘要是以它不用于解释或限制权利要求的范围或含义的理解而提交的。
在上述详细描述中，为了组织本公开的内容，在单个实施例中将多种特征组合在一起。这种公开方法不应被解释为反映声明要求保护的本发明实施例相比于各个权利要求中所明确陈述的特征而言需要更多特征的意图。相反，如所附权利要求所反映出来的那样，发明的主题少于以上公开的单个实施例的所有特征。因此，所附权利要求在此被包括到具体描述中，其中每个权利要求独立作为单独的优选实施例。
本领域普通技术人员将容易理解，可对为了说明本发明本质而描述和说明的部件和方法阶段的细节、材料和安排作出各种其他改变，而不背离如所附权利要求中表达的本发明的原理和范围。

Claims (25)

1.一种封装体堆叠装置，包括：
封装衬底，包括管芯面和底面；
设置在所述管芯面上的芯片叠层，其中所述芯片叠层包括设置在所述管芯面上的底部芯片和设置在所述底部芯片上方的顶部芯片，其中所述顶部芯片由所述底部芯片所支承，且其中所述芯片叠层具有偏移高度；以及
***件，其设置在所述管芯面上且包围所述芯片叠层，其中所述***件匹配于所述偏移高度。
2.如权利要求1所述的装置，其特征在于，所述***件具有球栅阵列，所述装置还包括：
顶部封装体，其中所述顶部封装体包括至少一个微电子器件，且其中所述顶部封装体配合所述***件球栅阵列。
3.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；以及
所述顶部芯片是设置在所述倒装芯片上的引线接合芯片。
4.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的引线接合第二芯片；以及
所述顶部芯片是设置在所述引线接合第二芯片上方的引线接合后续芯片。
5.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的硅通孔(TSV)第二芯片；以及
所述顶部芯片是设置在所述TSV第二芯片上的引线接合后续芯片。
6.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的硅通孔(TSV)第二芯片；
设置在所述TSV第二芯片上的TSV第三芯片；以及
所述顶部芯片是设置在所述TSV第三芯片上的引线接合第四芯片。
7.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的硅通孔(TSV)第二芯片；
设置在所述TSV第二芯片上的TSV第三芯片，其中所述TSV第三芯片是范围为2至8个TSV芯片的多个TSV芯片；以及
所述顶部芯片是设置在所述TSV第三芯片上方的引线接合后续芯片。
8.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的硅通孔(TSV)第二芯片；
设置在所述TSV第二芯片上方的TSV第三芯片；
设置在所述TSV第二芯片上方的引线接合第四芯片；以及
所述顶部芯片是设置在所述引线接合第四芯片上方的引线接合后续芯片。
9.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述TSV第一芯片上方的引线接合第二芯片；
设置在所述引线接合第二芯片上方的硅通孔(TSV)第三芯片；以及
所述顶部芯片是设置在所述TSV第三芯片上方的引线接合后续芯片。
11.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；以及
所述顶部芯片是设置在所述倒装芯片上的硅通孔(TSV)芯片。
12.如权利要求1所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
所述顶部芯片是设置在所述倒装芯片上方的硅通孔(TSV)后续芯片；以及
设置在所述底部芯片与所述顶部芯片之间的范围为2至7个芯片的至少一个TSV芯片。
13.一种封装体堆叠层叠芯片装置，包括：
封装衬底，包括管芯面和底面；
设置在所述管芯面上的芯片叠层，其中所述芯片叠层包括设置在所述管芯面上的底部芯片和设置在所述底部芯片上方的顶部芯片，其中所述顶部芯片由所述底部芯片所支承，且其中所述芯片叠层具有偏移高度；
***件，设置在所述管芯面上且包围所述芯片叠层，其中所述***件匹配于所述偏移高度；以及
设置在所述***件上的顶部封装体，其中所述顶部封装体包括至少一个微电子器件。
14.如权利要求13所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；以及
所述顶部芯片是设置在所述倒装芯片上的硅通孔(TSV)芯片。
15.如权利要求13所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
所述顶部芯片是设置在所述倒装芯片上方的硅通孔(TSV)后续芯片；以及
设置在所述底部芯片与所述顶部芯片之间的范围为2至7个芯片的至少一个TSV芯片。
16.如权利要求13所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；以及
所述顶部芯片是设置在所述倒装芯片上的引线接合芯片。
17.如权利要求13所述的装置，其特征在于，所述芯片叠层包括：
所述底部芯片是安装在所述衬底管芯面上的倒装芯片；
设置在所述倒装芯片上的引线接合第二芯片；以及
所述顶部芯片是设置在所述引线接合第二芯片上方的引线接合后续芯片。
18.一种组装封装体堆叠层叠芯片装置的方法，包括：
将具有球栅阵列的顶部封装体组装至三维(3D)层叠芯片装置的匹配球栅阵列，所述3D层叠芯片装置包括：
封装衬底，包括底面和管芯面；
设置在所述管芯面上的芯片叠层，其中所述芯片叠层具有叠层高度；
以及
包括管芯面和顶面的***件，其中所述***件产生偏移高度，所述
偏移高度匹配于所述叠层高度，且其中所述组装包括使所述顶部封装体配
合所述***件。
19.如权利要求18所述的方法，其特征在于，在将所述***件组装至所述封装衬底之前，将所述芯片叠层组装在所述封装衬底上。
20.如权利要求18所述的方法，其特征在于，在将所述芯片叠层组装至所述封装衬底之前，将所述***件组装在所述封装衬底上。
21.如权利要求18所述的方法，其特征在于，还包括在所述芯片叠层上形成叠层密封剂。
22.如权利要求18所述的方法，其特征在于，形成所述芯片叠层包括：
将底部芯片倒装安装在所述衬底管芯面上；以及
将顶部芯片引线接合安装在所述倒装芯片上方。
23.如权利要求18所述的方法，其特征在于，形成所述芯片叠层包括：
将底部芯片倒装安装在所述衬底管芯面上；
将第二芯片引线接合安装在所述底部芯片上方；以及
将顶部芯片引线接合安装在所述第二芯片上方。
24.如权利要求18所述的装置，其特征在于，形成所述芯片叠层包括：
将底部芯片倒装安装在所述衬底管芯面上；
将第二芯片通过硅通孔(TSV)安装在所述倒装芯片上；以及
将后续芯片引线接合安装在所述第二芯片上方作为顶部芯片。
25.一种计算***，包括：
封装衬底，包括管芯面和底面；
设置在所述管芯面上的芯片叠层，其中所述芯片叠层包括设置在所述管芯面上的底部芯片和设置在所述底部芯片上方的顶部芯片，其中所述顶部芯片由所述底部芯片所支承，且其中所述芯片叠层具有偏移高度；
***件，设置在所述管芯面上且包围所述芯片叠层，其中所述***件匹配于所述偏移高度；以及
设置在所述***件上的顶部封装体，其中所述顶部封装体包括至少一个微电子器件；以及
包含所述顶部封装体的设备外壳。
26.如权利要求25所述的计算***，其特征在于，所述计算***是下述之一的一部分：蜂窝电话、寻呼机、便携式计算机、桌面计算机以及双向无线电。
CN201080028740.6A 2009-06-26 2010-05-04 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的*** Expired - Fee Related CN102804364B (zh)

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