CN110010490B - 一种纵向互联的射频立方体结构的制作工艺 - Google Patents
一种纵向互联的射频立方体结构的制作工艺 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000005520 cutting process Methods 0.000 claims abstract description 10
- 238000003466 welding Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 30
- 229910052802 copper Inorganic materials 0.000 claims description 29
- 239000010949 copper Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000005496 eutectics Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 27
- 235000012431 wafers Nutrition 0.000 description 17
- 239000011135 tin Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005336 cracking Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008093 supporting effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明公开了一种纵向互联的射频立方体结构的制作工艺，包括以下步骤：在射频芯片转接板表面做凹槽，凹槽内填充金属；在转接板正面开空腔，埋入射频芯片；在射频芯片一面做RDL，焊盘，减薄转接板背面，在背面做焊盘；通过晶圆级键合把射频芯片转接板焊接在一起；机械切割得到单一立方体；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体。
Description
技术领域
本发明属于半导体技术领域，具体涉及一种纵向互联的射频立方体结构的制作工艺。
背景技术
对于高频率的微***，天线阵列的面积越来越小，且天线之间的距离要保持在某个特定范围，才能使整个模组具备优良的通信能力。但是对于射频芯片这种模拟器件芯片来讲，其面积不能像数字芯片一样成倍率的缩小，这样就会出现特高频率的射频微***将没有足够的面积同时放置PA/LNA，需要把PA/LNA堆叠放置。
对于堆叠的模块来讲，需要把上层的芯片通过TSV互联的方式把信号引到下层，最后跟基板互联，实现功能的输出。但是对于较高密度的TSV转接板来讲，如果堆叠层数较多，应力太大，往往会导致整个模组的碎裂或层间开裂，且多层的TSV结构会大大增加整个模块的成本。
发明内容
本发明要解决的技术问题是提供一种纵向互联的射频立方体结构的制作工艺。
为解决上述技术问题，本发明采用如下的技术方案：
一种纵向互联的射频立方体结构的制作工艺，包括以下步骤：
在射频芯片转接板表面做凹槽，凹槽内填充金属；在转接板正面开空腔，埋入射频芯片；
在射频芯片一面做RDL，焊盘，减薄转接板背面，在背面做焊盘；通过晶圆级键合把射频芯片转接板焊接在一起；
机械切割得到单一立方体；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体。
优选地，所述在射频芯片转接板表面做凹槽，凹槽内填充金属；在转接板正面开空腔，埋入射频芯片具体为：
通过光刻，刻蚀工艺在射频芯片转接板表面制作凹槽，凹槽长宽范围在1um到1000um，深度在10um到1000um；在硅片上方沉积氧化硅或者氮化硅等绝缘层，或者直接热氧化，绝缘层厚度范围在10nm到100um之间；通过物理溅射，磁控溅射或者蒸镀工艺在绝缘层上方制作种子层，种子层厚度范围在1nm到100um，为一层或多层，金属材质为钛、铜、铝、银、钯、金、铊、锡或镍；
电镀铜，使铜金属充满凹槽，200到500度温度下密化使铜更致密；铜CMP工艺使硅片表面铜去除，使硅片表面只剩下填铜；
通过光刻和干法刻蚀工艺在凹槽开口端做空腔，空腔长宽范围在1um到10000um，深度在10um到1000um。
优选地，所述在射频芯片一面做RDL，焊盘，减薄转接板背面，在背面做焊盘；通过晶圆级键合把射频芯片转接板焊接在一起具体为：
通过共晶键合或者胶粘的方式在空腔内设置射频芯片；通过光刻和电镀工艺在射频芯片正面制作RDL，使射频芯片PAD通过转接板表面RDL跟凹槽顶部开口互联；
通过光刻，电镀工艺在硅片表面制作键合金属，焊盘高度范围在10nm到1000um，金属可以是铜，铝，镍，银，金，锡等材料，可以是一层也可以是多层，其厚度范围为10nm到1000um；
此处焊盘和RDL是一面的，位于TSV铜柱露出的一端；
减薄转接板背面，减薄厚度控制在10um到1000um，通过光刻，电镀工艺在硅片表面制作键合金属，焊盘高度范围在10nm到1000um，金属可以是铜，铝，镍，银，金，锡等材料，可以是一层也可以是多层，其厚度范围为10nm到1000um；
干法刻蚀使转接板侧面的凹槽填充金属露出；
通过晶圆级键合把射频芯片转接板焊接在一起；键合层数控制在2到10层之间。
优选地，所述机械切割得到单一立方体；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体具体为：
通过干法刻蚀或者机械切割的方式得到单一的射频模块立方体结构，通过表贴工艺在立方体上面贴装天线；
制作具有表面RDL和表面Bump或BGA的互联转接板，其功能是电线互联和焊接；在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体；
在立方体的两侧或者四面都设置一个，实现射频立方体集成度的最大化。
采用本发明具有如下的有益效果：本发明实施例通过把单层芯片的信号线在转接板的侧壁引出，然后通过一个具有密集布线结构的互联无源芯片做层间互联，起到了TSV互联的作用,且避免了TSV结构的引入，降低了工艺难度和成本。
附图说明
图1a所示为本发明实施例通过光刻，刻蚀工艺在射频芯片转接板表面制作凹槽的结构示意图；
图1b所示为本发明实施例通过共晶键合或者胶粘的方式在空腔内设置射频芯片的结构示意图；
图1c所示为本发明实施例通过晶圆级键合把射频芯片转接板焊接在一起的结构示意图；
如图1d所示为通过干法刻蚀或者机械切割的方式得到单一的射频模块立方体结构，通过表贴工艺在立方体上面贴装天线的结构示意图；
图1e所示为互联转接板在立方体的两侧设置的结构示意图；
图1f所示为互联转接板在立方体的四面设置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供的一种纵向互联的射频立方体结构的制作工艺，具体包括以下步骤：
A：在射频芯片转接板表面做凹槽，凹槽内填充金属；在转接板正面开空腔，埋入射频芯片；
如图1a所示，通过光刻，刻蚀工艺在射频芯片转接板101表面制作凹槽103，凹槽长宽范围在1um到1000um，深度在10um到1000um；在硅片上方沉积氧化硅或者氮化硅等绝缘层，或者直接热氧化，绝缘层厚度范围在10nm到100um之间；通过物理溅射，磁控溅射或者蒸镀工艺在绝缘层上方制作种子层，种子层厚度范围在1nm到100um，其可以是一层也可以是多层，金属材质可以是钛、铜、铝、银、钯、金、铊、锡、镍等；
电镀铜，使铜金属充满凹槽，200到500度温度下密化使铜更致密；铜CMP工艺使硅片表面铜去除，使硅片表面只剩下填铜；硅片表面绝缘层可以用干法刻蚀或者湿法腐蚀工艺去除；硅片表面绝缘层也可以保留；
通过光刻和干法刻蚀工艺在凹槽开口端做空腔102，空腔长宽范围在1um到10000um，深度在10um到1000um；
此步骤的硅片包括4，6，8，12寸晶圆，厚度范围为200um到2000um，也可以是其他材质，包括玻璃，石英，碳化硅，氧化铝等无机材料，也可以是环氧树脂，聚氨酯等有机材料，其主要功能是提供支撑作用。
B：在射频芯片一面做RDL，焊盘，减薄转接板背面，在背面做焊盘；通过晶圆级键合把射频芯片转接板焊接在一起；
如图1b所示，通过共晶键合或者胶粘的方式在空腔内设置射频芯片；通过光刻和电镀工艺在射频芯片正面制作RDL，使射频芯片PAD通过转接板表面RDL跟凹槽顶部开口互联；
通过光刻，电镀工艺在硅片表面制作键合金属，焊盘高度范围在10nm到1000um，金属可以是铜，铝，镍，银，金，锡等材料，可以是一层也可以是多层，其厚度范围为10nm到1000um；
此处焊盘和RDL是一面的，位于TSV铜柱露出的一端；
减薄转接板背面，减薄厚度控制在10um到1000um，通过光刻，电镀工艺在硅片表面制作键合金属，焊盘高度范围在10nm到1000um，金属可以是铜，铝，镍，银，金，锡等材料，可以是一层也可以是多层，其厚度范围为10nm到1000um；
干法刻蚀使转接板侧面的凹槽填充金属露出；
如图1c所示，通过晶圆级键合把射频芯片转接板焊接在一起；键合层数控制在2到10层之间；
C：机械切割得到单一立方体；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体；
如图1d所示，通过干法刻蚀或者机械切割的方式得到单一的射频模块立方体结构，通过表贴工艺在立方体上面贴装天线；
制作具有表面RDL和表面Bump或BGA的互联转接板，其功能是电线互联和焊接；在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体；
此处互联转接板还可以如图1e或者1f所示，在立方体的两侧或者四面都设置一个，实现射频立方体集成度的最大化。
对本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
应当理解，本文所述的示例性实施例是说明性的而非限制性的。尽管结合附图描述了本发明的一个或多个实施例，本领域普通技术人员应当理解，在不脱离通过所附权利要求所限定的本发明的精神和范围的情况下，可以做出各种形式和细节的改变。
Claims (2)
1.一种纵向互联的射频立方体结构的制作工艺，其特征在于，包括以下步骤：
在由硅片构成的射频芯片转接板上表面做凹槽，凹槽内填充金属；在射频芯片转接板上表面开空腔，埋入射频芯片，具体为：通过光刻，刻蚀工艺在射频芯片转接板上表面制作凹槽，凹槽长宽范围在1um到1000um，深度在10um到1000um；在射频芯片转接板上表面沉积氧化硅或者氮化硅绝缘层，或者直接热氧化，绝缘层厚度范围在10nm到100um之间；通过物理溅射，磁控溅射或者蒸镀工艺在绝缘层上方制作种子层，种子层厚度范围在1nm到100um，为一层或多层，金属材质为钛、铜、铝、银、钯、金、铊、锡或镍；
电镀铜，使铜金属充满凹槽，200到500度温度下密化使铜更致密；铜CMP工艺使硅片表面铜去除，使硅片表面只剩下填铜；
通过光刻和干法刻蚀工艺在凹槽一侧做空腔，空腔长宽范围在1um到10000um，深度在10um到1000um；
在射频芯片一面做RDL，焊盘，减薄射频芯片转接板转接板下表面，在射频芯片转接板转接板下表面做焊盘；通过晶圆级键合把射频芯片转接板焊接在一起，具体为：
通过共晶键合或者胶粘的方式在空腔内设置射频芯片；通过光刻和电镀工艺在射频芯片上表面制作RDL，使射频芯片PAD通过射频芯片转接板上表面RDL跟凹槽顶部开口互联；
通过光刻，电镀工艺在射频芯片转接板上表面制作键合金属构成的焊盘，焊盘高度范围在10nm到1000um，焊盘的金属为一层或者多层，其厚度范围为10nm到1000um；
此处焊盘和RDL是在同一侧的，位于凹槽内填充铜金属构成的TSV铜柱露出的一端；
减薄射频芯片转接板下表面，减薄厚度控制在10um到1000um，通过光刻，电镀工艺在硅片下表面制作键合金属构成的焊盘，焊盘高度范围在10nm到1000um，焊盘的金属为一层或者多层，其厚度范围为10nm到1000um；
干法刻蚀使射频芯片转接板侧面的凹槽填充金属露出；
通过晶圆级键合把射频芯片转接板焊接在一起；键合层数控制在2到10层之间；
机械切割得到单一的射频模块立方体结构；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体。
2.如权利要求1所述的纵向互联的射频立方体结构的制作工艺，其特征在于，所述机械切割得到单一的射频模块立方体结构；在立方体上面贴装天线，在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体具体为：
通过机械切割的方式得到单一的射频模块立方体结构，通过表贴工艺在立方体上面贴装天线；
制作具有表面RDL和表面Bump或BGA的互联转接板，其功能是电线互联和焊接；在立方体侧面贴互联转接板和电源驱动芯片完成立方体的电性互联得到最后的功能射频立方体；
在立方体的两侧或者四面都设置一个互联转接板或电源驱动芯片，实现射频立方体集成度的最大化。
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