CN114122002A - 存储装置 - Google Patents
存储装置 Download PDFInfo
- Publication number
- CN114122002A CN114122002A CN202111411443.6A CN202111411443A CN114122002A CN 114122002 A CN114122002 A CN 114122002A CN 202111411443 A CN202111411443 A CN 202111411443A CN 114122002 A CN114122002 A CN 114122002A
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- memory cell
- cell array
- contact plug
- electrically connected
- electrode layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H—ELECTRICITY
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Bipolar Transistors (AREA)
- Noodles (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017042675A JP2018148071A (ja) | 2017-03-07 | 2017-03-07 | 記憶装置 |
JP2017-042675 | 2017-03-07 | ||
CN201710796424.7A CN108573959B (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710796424.7A Division CN108573959B (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114122002A true CN114122002A (zh) | 2022-03-01 |
Family
ID=63445107
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111412363.2A Pending CN114122003A (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
CN202111411443.6A Pending CN114122002A (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
CN201710796424.7A Active CN108573959B (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111412363.2A Pending CN114122003A (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710796424.7A Active CN108573959B (zh) | 2017-03-07 | 2017-09-06 | 存储装置 |
Country Status (4)
Country | Link |
---|---|
US (5) | US10297578B2 (zh) |
JP (1) | JP2018148071A (zh) |
CN (3) | CN114122003A (zh) |
TW (5) | TWI771579B (zh) |
Families Citing this family (94)
Publication number | Priority date | Publication date | Assignee | Title |
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US10892269B2 (en) | 2014-09-12 | 2021-01-12 | Toshiba Memory Corporation | Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit |
JP6203152B2 (ja) * | 2014-09-12 | 2017-09-27 | 東芝メモリ株式会社 | 半導体記憶装置の製造方法 |
US10418369B2 (en) * | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
JP2018148071A (ja) * | 2017-03-07 | 2018-09-20 | 東芝メモリ株式会社 | 記憶装置 |
JP2019201028A (ja) * | 2018-05-14 | 2019-11-21 | 東芝メモリ株式会社 | 半導体装置 |
CN112262474B (zh) * | 2018-08-07 | 2024-07-16 | 铠侠股份有限公司 | 半导体存储装置 |
CN111354732B (zh) * | 2018-09-14 | 2021-04-27 | 长江存储科技有限责任公司 | 三维存储器件以及用于形成三维存储器件的方法 |
JP2020047806A (ja) * | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | 半導体記憶装置 |
JP2020047819A (ja) * | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | 半導体記憶装置 |
TWI713195B (zh) * | 2018-09-24 | 2020-12-11 | 美商森恩萊斯記憶體公司 | 三維nor記憶電路製程中之晶圓接合及其形成之積體電路 |
CN109643700B (zh) | 2018-11-21 | 2019-09-10 | 长江存储科技有限责任公司 | 用于接合界面处的接合对准标记的方法、器件和结构 |
CN109524409B (zh) * | 2018-11-23 | 2020-04-10 | 长江存储科技有限责任公司 | 形成三维存储器的方法 |
CN109768050B (zh) * | 2018-12-18 | 2020-11-17 | 长江存储科技有限责任公司 | 三维存储器及其制备方法 |
KR102658194B1 (ko) * | 2018-12-21 | 2024-04-18 | 삼성전자주식회사 | 반도체 장치 |
US11469214B2 (en) * | 2018-12-22 | 2022-10-11 | Xcelsis Corporation | Stacked architecture for three-dimensional NAND |
US10957705B2 (en) * | 2018-12-24 | 2021-03-23 | Sandisk Technologies Llc | Three-dimensional memory devices having a multi-stack bonded structure using a logic die and multiple three-dimensional memory dies and method of making the same |
CN109727989B (zh) * | 2018-12-29 | 2020-07-07 | 长江存储科技有限责任公司 | 一种三维存储器及其制造方法 |
CN109727990B (zh) * | 2018-12-29 | 2020-05-15 | 长江存储科技有限责任公司 | 一种三维存储器及其制造方法 |
US10957680B2 (en) * | 2019-01-16 | 2021-03-23 | Sandisk Technologies Llc | Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same |
JP7425069B2 (ja) * | 2019-01-30 | 2024-01-30 | サンライズ メモリー コーポレイション | 基板接合を用いた高帯域幅・大容量メモリ組み込み型電子デバイス |
KR102618756B1 (ko) | 2019-01-30 | 2023-12-27 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 더미 접합 콘택트를 사용한 하이브리드 접합 |
WO2020154954A1 (en) | 2019-01-30 | 2020-08-06 | Yangtze Memory Technologies Co., Ltd. | Hybrid bonding using dummy bonding contacts and dummy interconnects |
WO2020163984A1 (en) * | 2019-02-11 | 2020-08-20 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same |
JP2020141100A (ja) | 2019-03-01 | 2020-09-03 | キオクシア株式会社 | 半導体装置およびその製造方法 |
WO2020177048A1 (en) | 2019-03-04 | 2020-09-10 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices |
JP2020145231A (ja) * | 2019-03-04 | 2020-09-10 | キオクシア株式会社 | 半導体装置およびその製造方法 |
CN111524900B (zh) * | 2019-03-04 | 2021-02-09 | 长江存储科技有限责任公司 | 三维存储器件 |
JP2020150037A (ja) * | 2019-03-11 | 2020-09-17 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2020155487A (ja) * | 2019-03-18 | 2020-09-24 | キオクシア株式会社 | 半導体記憶装置およびその製造方法 |
WO2020188775A1 (ja) * | 2019-03-19 | 2020-09-24 | キオクシア株式会社 | 半導体記憶装置 |
KR20200112013A (ko) * | 2019-03-20 | 2020-10-05 | 삼성전자주식회사 | 수직형 반도체 소자 |
KR20240045345A (ko) * | 2019-04-15 | 2024-04-05 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 프로세서 및 동적 랜덤 액세스 메모리를 갖는 본디드 반도체 장치 및 이를 형성하는 방법 |
CN110945652A (zh) * | 2019-04-15 | 2020-03-31 | 长江存储科技有限责任公司 | 堆叠三维异质存储器件及其形成方法 |
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