JP2012146861A - 半導体記憶装置 - Google Patents
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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Abstract
【解決手段】半導体記憶装置は、半導体基板100と、前記半導体基板上に形成され、データを記憶する複数のメモリセルが配置されたメモリセルアレイ部Aと、前記メモリセルアレイ部上に絶縁層を介して形成され、かつ、前記絶縁層および前記メモリセルアレイ部を貫通する孔106内に形成されて前記半導体基板に接続された単結晶半導体層109と、前記単結晶半導体層上に形成された回路部Bと、を具備し、前記メモリセルアレイ部上における前記単結晶半導体層の下部側は、上部側よりもGe濃度が高い。
【選択図】 図1
Description
図1乃至図7を用いて、第1の実施形態に係る半導体記憶装置について説明する。第1の実施形態は、メモリセルアレイの直上に制御回路が設けられる単結晶半導体層が形成される例である。
以下に図1乃至図3を用いて、第1の実施形態に係る半導体記憶装置の構造について説明する。
以下に、図4乃至図7を用いて、第1の実施形態に係る半導体記憶装置の製造方法について説明する。
上記第1の実施形態によれば、メモリセルアレイ部Aの上部に、メモリセルアレイ部Aへの供給電圧等を制御する回路部B(制御回路)が設けられている。これにより、任意の位置で制御回路の隙間からビット線BLにコンタクトをとることが可能となる。すなわち、ビット線BLの直上にコンタクトプラグ102を形成することで、ビット線BLと回路部Bとを1つのプラグで接続することができる。したがって、回路部をメモリセルアレイの下部に形成する従来の構造のように、メモリセルアレイ端で配線等を折り返して下部の回路部に接続する必要がなく、チップ面積を縮小することができる。
図8および図9を用いて、第2の実施形態に係る半導体記憶装置について説明する。第2の実施形態は、メモリセルアレイの直上の回路部において、単結晶半導体層を貫通するようにSTIが形成される例である。なお、第2の実施形態において、上記第1の実施形態と同様の点については説明を省略し、異なる点について説明する。
以下に図8を用いて、第2の実施形態に係る半導体記憶装置の構造について説明する。
以下に、図9を用いて、第2の実施形態に係る半導体記憶装置の製造方法について説明する。
上記第2の実施形態によれば、第1の実施形態と同様の効果を得ることができる。
Claims (6)
- 半導体基板と、
前記半導体基板上に形成され、データを記憶する複数のメモリセルが配置されたメモリセルアレイ部と、
前記メモリセルアレイ部上に絶縁層を介して形成され、かつ、前記絶縁層および前記メモリセルアレイ部を貫通する孔内に形成されて前記半導体基板に接続された単結晶半導体層と、
前記単結晶半導体層上に形成された回路部と、
を具備し、
前記メモリセルアレイ部上における前記単結晶半導体層の下部側は、上部側よりもGe濃度が高いことを特徴とする半導体記憶装置。 - 前記メモリセルアレイ部は、前記半導体基板に対して垂直方向に3次元的に積層された前記複数のメモリセルを含むことを特徴とする請求項1に記載の半導体記憶装置。
- 前記メモリセルアレイ部は、マトリクス状に配置された複数のメモリセルストリングを有し、
各前記メモリセルストリングは、
前記半導体基板に対して垂直方向に延び、カラム方向に並ぶ一対の柱状部、および前記一対の柱状部の下端を連結させるように形成された連結部を有するシリコンピラーと、
前記柱状部と直交してロウ方向に延び、前記半導体基板に対して垂直方向に積層された複数のコントロールゲートと、
前記柱状部と複数の前記コントロールゲートとの各交差部に形成され、前記半導体基板に対して垂直方向に直列に接続された複数のメモリセルトランジスタと、
を含むことを特徴とする請求項1に記載の半導体記憶装置。 - 前記単結晶半導体層は、前記メモリセルアレイ部上に前記絶縁層を介して形成され、かつ、前記絶縁層および前記メモリセルアレイ部を貫通する孔内に形成されて前記半導体基板と接続された単結晶SiGe層と、前記単結晶SiGe層上に形成された単結晶Si層と、で構成されている
ことを特徴とする請求項1に記載の半導体記憶装置。 - 前記メモリセルアレイ部の配線層と前記回路部の配線層とは、前記メモリセルアレイ部の配線層の直上に形成されたコンタクトプラグを介して接続されていることを特徴とする請求項1に記載の半導体記憶装置。
- 前記単結晶半導体層内に形成され、前記単結晶半導体層の第1面から前記第1面に対向する第2面まで貫通するSTIをさらに具備し、
前記コンタクトプラグは、前記STI内に形成される
ことを特徴とする請求項5に記載の半導体記憶装置。
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JP2011004954A JP2012146861A (ja) | 2011-01-13 | 2011-01-13 | 半導体記憶装置 |
US13/346,888 US8476708B2 (en) | 2011-01-13 | 2012-01-10 | Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration |
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