CN103311317B - 碳化硅半导体装置及其制造方法 - Google Patents

碳化硅半导体装置及其制造方法 Download PDF

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CN103311317B
CN103311317B CN201210582270.9A CN201210582270A CN103311317B CN 103311317 B CN103311317 B CN 103311317B CN 201210582270 A CN201210582270 A CN 201210582270A CN 103311317 B CN103311317 B CN 103311317B
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silicon carbide
carbide semiconductor
semiconductor device
epitaxial layer
manufacture method
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CN103311317A (zh
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松野吉德
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明提供一种碳化硅半导体装置及碳化硅半导体装置的制造方法，以在分割成多个芯片的碳化硅半导体衬底中，分割后能够抑制放电产生。本发明，包括：n＋型衬底（1）；n＋型衬底1上形成的杂质浓度比n＋型衬底（1）低的漂移外延层（2）；漂移外延层（2）上形成的肖特基电极（6）；以及至少覆盖肖特基电极（6）的端部、和漂移外延层（2）的端部及侧面而形成的作为绝缘膜的PI（8）。

Description

碳化硅半导体装置及其制造方法
技术领域
本发明涉及碳化硅半导体装置及碳化硅半导体装置的制造方法。
背景技术
一般知晓碳化硅（以下SiC）半导体与硅（Si）相比，破坏电场、带隙、热传导率较大。由于带隙及热传导率较大，因此耐热性优异，高温工作、简易冷却成为可能。另外，破坏电场较大，所以薄型化容易，损耗低，高温工作成为可能。
在SiC肖特基势垒二极管（SiC Schottky Barrier Diode：以下SiC-SBD）、SiC-MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor：金属-氧化层-半导体-场效应晶体管）的设计中，其破坏电场，与使用硅时的0.3MV/cm相对，在使用SiC的情况下为2.8MV/cm。如果有效利用该特长，决定活性层的漂移外延层的厚度、终端构造，则在使用破坏电场为硅的约10倍大的SiC的情况下，例如漂移外延层为硅的1/10左右即可。
关于kV级高耐压的SiC-SBD，肖特基电极形成于n型SiC外延层上而构成。
在该构造，在外延层和肖特基电极的结合面周边电场容易集中，所以需要在其结合面（肖特基结合面）周边的表层形成用于缓冲电场集中的p型终端构造。
p型终端构造的形成，一般使用将Al（铝）、B（硼）等p型杂质离子注入到n型外延层，用1500℃左右以上的高温热处理激活退火的方法。接着，研磨背面，形成背面欧姆，在表面形成肖特基结合。进而，作为引线焊接（WB）时的垫片（pad），一般形成5μm左右的Al。以前是在此后，形成需要350℃左右的固化加热的聚酰亚胺（以下PI）作为钝化膜后，最后实施Ni/Au的背面金属化，完成晶圆工艺。
元件的电特性评价需要进行晶圆测试（以下WT）及芯片测试（以下CT）的情况下，WT后，利用切割分割成各个芯片，实施CT。以上是一般的工序顺序。
这里，PI以分别覆盖表面电极垫片开口部以外的表面电极端、切割线开口部以外的表面电极端、终端构造附近的方式形成。
通常形成PI时，在与衬底表面的芯片端相当的部位不实施形成槽之类，所以在各个元件的侧壁部不形成PI。
对于此，关于为某些目的而在各个元件的侧壁部形成PI等的钝化膜的技术确认如下的实例。
在专利文献1，记载了将在蓝宝石衬底上形成GaN类结晶层的衬底分割成芯片的方法。特别关于碎屑对策进行了详细记载。
关于GaN元件的制造方法，记载了对于劈开时的碎屑、切割时的切屑量的扩大的对策。另外，记载了以钝化膜覆盖电极用凹部内的侧壁面的工序。
关于形成的槽部的深度，记载了优选1～100μm，特别是1～50μm为更优选的范围，并未设想最终断开所形成的槽部。
在专利文献2，记载了通过具备被称为芯片框的绝缘性框，使不良芯片的抽出得以容易，模块制造时的芯片保护成为可能的方法。依据该方法，进一步小型化、低电感化也成为可能。
在专利文献3，关于在端面整体形成导体层的构造进行了记载。
在专利文献4，记载了在硅太阳电池的制造中，利用激光划片法形成0.1μm以上10μm以下的凹部的方法。
在专利文献5，记载为了在保持衬底强度并且降低导通电阻的目的而在元件背面具有凹部的构造。
[专利文献]
[专利文献1]日本专利申请公开第2005-012206号公报；
[专利文献2]日本专利申请公开第2000-183282号公报；
[专利文献3]日本专利申请公开第2009-224641号公报；
[专利文献4]日本专利申请公开第2004-064028号公报；
[专利文献5]日本专利申请公开第2006-156658号公报。
发明内容
如上述，有效利用破坏电场在使用硅时为0.3MV/cm而在使用SiC时为2.8MV/cm的特长，决定活性层即漂移外延层的厚度、终端构造。
破坏电场为硅的约10倍大的SiC，漂移外延层为硅的1/10左右即可。即使关于终端构造的面方向的尺寸，在使用SiC材料的情况下也为硅的1/10左右即可。
这里，由于芯片端的形状引起的电场集中、受周围气氛影响的芯片状态，在电特性评价时可能产生放电。
由于已经分割成各个芯片，该放电容易在露出未形成PI的侧壁部（侧面部）的各个元件产生，由此，存在即使WT中不放电，CT中也会放电的这一问题。
本发明是为解决如上述的问题而成的，其目的在于提供一种碳化硅半导体装置及碳化硅半导体装置的制造方法，以在分割成多个芯片的碳化硅半导体衬底中，分割后能够抑制放电产生。
本发明的碳化硅半导体装置，其特征在于，包括：碳化硅半导体衬底；外延层，在所述碳化硅半导体衬底上形成，该外延层的杂质浓度比所述碳化硅半导体衬底低；电极，在所述外延层上形成；绝缘膜，至少覆盖所述电极的端部、和所述外延层的端部及侧面而形成。
本发明的碳化硅半导体装置的制造方法，其特征在于，包括：（a）在碳化硅半导体衬底上，形成杂质浓度比所述碳化硅半导体衬底低的外延层的工序；（b）在所述外延层上，形成多个电极的工序；（c）在各所述电极所夹着的所述外延层上，形成比所述外延层下表面深的槽的工序；（d）至少覆盖所述电极的端部、和所述外延层的端部及露出的侧面而形成绝缘膜的工序；以及（e）从形成有所述槽的部分分割所述碳化硅半导体衬底的工序。
依据本发明的碳化硅半导体装置，通过包括至少覆盖所述电极的端部、和所述外延层的端部及侧面而形成的绝缘膜，能够防止外延层的侧面部露出，能够抑制放电产生。
依据本发明的碳化硅半导体装置的制造方法，包括（c）在各所述电极所夹着的所述外延层上，形成比所述外延层下表面深的槽的工序、（d）至少覆盖所述电极的端部、和所述外延层的端部及露出的侧面而形成绝缘膜的工序、和（e）从形成有所述槽的部分分割所述碳化硅半导体衬底的工序，从而，在分割碳化硅半导体衬底后，也能够防止外延层的侧面部露出，能够抑制放电产生。
附图说明
图1是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图2是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图3是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图4是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图5是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图6是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图7是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图8是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图9是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图10是说明本发明的实施方式的碳化硅半导体装置的制造方法的剖面图；
图11是说明本发明的先前技术的碳化硅半导体装置的制造方法的剖面图；
图12是说明本发明的先前技术的碳化硅半导体装置的制造方法的剖面图。
具体实施方式
作为本发明的先前技术，如图11，示出PI8以分别覆盖表面电极垫片开口部10以外的表面电极端、切割线开口部100以外的表面电极端、终端构造附近的方式形成的情况。
通常形成PI8时，在与n＋型衬底1表面的芯片端相当的部位不实施形成槽之类，所以，如图12所示，在分割成各个芯片时，在各个元件的侧壁部（侧面部），不形成作为绝缘膜的PI8。
这里，由于芯片端的形状引起的电场集中、受周围气氛影响的芯片状态，在电特性评价时能够产生放电。
由于已经分割，该放电容易在露出未形成PI8的侧壁部（侧面部）的各个元件产生，由此，即使WT中不放电而完成，CT中也会放电。
在以下的实施方式，鉴于如上述的问题，示出在分割成多个芯片的碳化硅半导体衬底中，分割后能够抑制放电产生的碳化硅半导体装置及碳化硅半导体装置的制造方法。
＜实施方式1＞
＜制造方法＞
以下，本发明的碳化硅半导体装置及碳化硅半导体装置的制造方法的概要如果以SiC-SBD为例进行说明，则大概如下。
例如，在口径4英寸4°斜角的n型4H-SiC衬底的硅面（0001），利用CVD法外延生长n型SiC层。
关于生长于n型4H-SiC衬底上的n型外延层的、浓度和厚度进行调整，以实现期望的耐压。
依次实施照相制版工序中需要的步骤，即形成用于衬底内的对位基准的标记、形成p型终端构造、研磨背面、形成背面中的欧姆结合、形成表面中的肖特基结合、形成引线焊接（以下WB）用的表面垫片。
关于槽的深度，至少比与漂移外延层厚相当的量还要深。也取决于耐压规格，但漂移外延层厚为数μm～数十μm左右。如果考虑将PI也形成在槽的侧面，则槽越深形成越困难，由此，最好限于与外延层厚相当的深度。
另一方面，将槽形成到与衬底厚度的2/3相当程度的深度，即，在4英寸SiC衬底的厚度为300～350μm左右的情况下，也能够将未被切割的剩余厚度设为例如100μm左右。
这是因为在利用机械断开来分割时，在未被切割的SiC的剩余厚度部分容易发生成为缺损的碎屑、或者反过来被称为“毛边”的多余突出部，SiC的剩余厚度部分越厚，这些越容易发生，其程度也变得更显著。分割自身也变得困难。
另外，包括半切工序在内，为了不破坏衬底状态地处理其后的PI形成、背面金属化、进而直至电特性评价的WT，需要确保衬底的强度。在上述的4英寸SiC衬底的情况下，为确保强度需要的厚度为100μm左右，所以，能够薄化到如上述的剩余厚度。
半切后的PI形成，与通常的晶圆工艺同样，设想旋涂PI的液体材料的手法。
与照相制版中使用的光致抗蚀剂比较，通常将高粘性的粘液状PI材料以与目标厚度相应的旋转数、例如2000～3000rpm左右的旋转数旋涂，从而控制形成在衬底表面的PI厚度，同时提高其面内均匀性。
但是，作为最终的PI形成完成是在固化加热后。利用半切，在SiC衬底表面做出例如50～100μm的宽度的槽，在那里也形成有PI。
关于形成于该区域的PI，无法如通常的衬底表面那样实现目标厚度和良好的面内均匀性。然而，能够达到以SiC覆盖侧壁的目的。此外，可以明了在防止在芯片的角发生的放电现象时，PI的膜厚依赖性较小。
以下，参照图1～图10，说明本发明的实施方式的碳化硅半导体装置的制造方法的细节。图1～图10是用于说明本发明的实施方式1的制造方法的、制造工序中的SiC-SBD的主要剖面图。
首先，如图1所示，在工序1，准备由（0001）硅面4H-SiC而成的8°或4°斜角的n＋型衬底1。n＋型衬底1的电阻率为0.02Ω・cm左右。
接下来，在n＋型衬底1上，对应600V～3300V左右的期望的耐压，使杂质浓度5×1015/cm3左右的n型的漂移外延层2生长5～30μm左右。漂移外延层2设为浓度比n＋型衬底1低的杂质浓度。
而且，在SiC表面蚀刻0.3μm左右而形成后续工序的照相制版时需要的对照标记。关于该标记，省略图示。为简化制造工序，该标记形成也能与接下来的注入工序组合。
接下来，如图2所示，在工序2，为稳定并确保期望的耐压，作为肖特基电极端部的电场集中缓冲构造，将Al离子注入的终端p型注入层3形成在漂移外延层2上。
作为一例，也可以形成被称为FLR（Field Limiting Ring：场限环）的、1种浓度的多重环构造，或者包括GR（Guard Ring：保护环）和其外侧连续而浓度小一些的环构造的被称为JTE（Junction Termination Extension：结终端扩展）的、2种浓度的终端构造。
任一种情况下，为作为终端构造而完成，都需要激活注入层。在SiC工艺，一般在1300～1700℃左右的高温进行热处理。此时，也可以为抑制被称为群聚阶梯（bunchingstep）的阶梯差发生，用石墨膜覆盖（capping）。在良好的工艺中，能将群聚阶梯抑制到不足1nm。p型注入层如果能得到50％以上、更好为90％以上的激活率，则作为终端构造起作用。激活率较高这一事项，能够解释成注入工序中坏掉的结晶的再结晶状态处于较完善的状态的标志，有助于实现器件的高可靠性。
接下来，如图3所示，在工序3，为保护n型的漂移外延层2及终端p型注入层3的表面，形成SiO2热氧化膜4。
为使SBD器件的电特性良好，干式氧化是有效的，最好形成大概20nm以上的氧化膜。在热氧化的情况下，一般在背面也形成SiO2热氧化膜，但在图3省略其记载。此后，背面研磨成期望的厚度，露出清洁SiC的背面。
接下来，如图4所示，在工序4，形成背面的欧姆电极5。例如利用溅射形成100nm厚的Ni，将其在1000℃退火，从而能得到良好的欧姆结合。
在工序3形成的表面的SiO2热氧化膜4作为工艺保护膜起作用。在接下来将要形成肖特基金属之前，利用氢氟酸蚀刻除去SiO2热氧化膜4，准备清洁的n型的漂移外延层2的SiC表面。
接下来，如图5所示，在工序5，在每个表面的终端p型注入层3所夹着的位置，分别形成肖特基电极6。例如，利用溅射在整个面成膜Ti，照相工序中利用稀氢氟酸蚀刻进行电极构图。为使电特性更稳定，在450℃左右热处理肖特基电极6是有效的。
此外，在将Ti设为肖特基金属的情况下，在SiC-SBD，对器件特性造成最大影响的结合部位是Ti/SiC界面，所以，可能的话，最好先形成表面的Ti的肖特基电极6，之后形成背面的欧姆电极5。
然而，为形成良好的Ni的背面的欧姆电极5，需要1000℃左右的退火，Ti的肖特基电极6在该高温工艺将被破坏，由此，只好选择先形成背面的欧姆电极5，在后形成表面的Ti的肖特基电极6的手法。
接下来，如图6所示，在工序6，形成WB用的表面垫片7。例如利用溅射在整个面成膜5μm的Al，与上述的Ti同样利用照相制版形成构图。一般Al的蚀刻液以磷酸为主。
接下来，如图7所示，在工序7，在形成PI8前，利用刀片切割将n＋型衬底1半切而形成槽11。
关于槽的深度，至少形成到与漂移外延层厚相当的深度。即，槽11的底面，形成到与漂移外延层2的下表面、或下表面附近的n＋型衬底1相当的深度。也取决于耐压规格，但漂移外延层厚为数μm～数十μm左右。如果考虑将PI也形成在槽11的侧面，则槽越深形成越困难，因此，最好限于与外延层厚相当的深度。
另一方面，将槽形成到与衬底厚度的2/3相当程度的深度，即，在4英寸SiC衬底的厚度为300～350μm左右的情况下，也能够将未被切割的剩余厚度设为例如100μm左右。
这是因为在利用机械断开来分割时，在未被切割的SiC的剩余厚度部分容易发生成为缺损的碎屑、或者反过来被称为“毛边”的多余突出部，SiC的剩余厚度部分越厚，这些越容易发生，其程度也变得更显著。另外，剩余厚度部分越厚分割自身也越困难。
包括半切工序在内，为了不破坏衬底状态地处理其后的PI形成、背面金属化、进而直至电特性评价的WT，需要确保衬底的强度。在上述的4英寸SiC衬底的情况下，为确保强度需要的厚度为100μm左右，所以，能够薄化到如上述的剩余厚度。
接下来，如图8所示，在工序8，与通常的晶圆工艺同样，以旋涂PI8的液体材料的手法进行半切后的PI8的形成。
与照相制版中使用的光致抗蚀剂比较，通常将高粘性的粘液状PI材料以与目标厚度相应的旋转数、例如2000～3000rpm左右的旋转数旋涂，控制形成在衬底表面的PI厚度，同时提高其面内均匀性。
但是，作为最终的PI8形成完成是在350℃左右的固化加热后。
利用半切在n＋型衬底1表面做出例如50～100μm的宽度的槽11，在那里也形成有PI8。即，对除了表面电极垫片开口部10的表面垫片7及肖特基电极6（包含端部）、进而漂移外延层2的表面（包含端部）及侧面、露出的n＋型衬底1，形成有PI8。
关于形成在该区域的PI8，无法如通常的n＋型衬底1表面那样实现目标厚度和良好的面内均匀性。然而，能够达到以SiC覆盖侧壁的目的。此外，可以明了在防止在芯片的角发生的放电现象的情况下，PI8的膜厚依赖性较小。
接下来，如图9所示，在工序9，作为背面金属层9，例如利用溅射在整个面成膜Ni、Au。由以上，晶圆工艺完成。在实施晶圆测试（WT）的情况下，在该状态实施。
接下来，如图10所示，在工序10，分割半切时剩余的n＋型衬底1厚度部分。这样晶圆从形成有槽11的部分被分割而成为芯片状态，能够实现本发明的以PI8覆盖芯片侧面的构造。为在半切切割后分割芯片，例如机械的断开是有效的。
如上所述，能够实现碳化硅半导体装置的构造，其关于SiC芯片的PI形成部位，作为绝缘膜的PI，至少从外延层形成侧的电极端开始覆盖芯片的角（漂移外延层2的端部）、进而在芯片的侧面（漂移外延层2的侧面）中至少覆盖与漂移外延层2厚相当的部分。
通过设为使PI也覆盖芯片的角及芯片侧面的构造，能够抑制芯片测试以后发生的放电现象。进而在衬底状态（分割前的状态）形成PI8，所以量产性优异。
这里，在PI形成后的切割的精加工工序，一般实施纯水的清洗。是为了除去切割导致的磨粒和切屑。
不过，也有SiC-SBD芯片表面的PI如果吸湿则使耐压特性变差的情况。作为该对策，以前是在表面金属化、及PI形成、背面金属层形成后进行切割及清洗，在芯片分割的情况下，将由于纯水清洗而吸湿的PI，利用芯片200℃左右的固化加热，使PI中的水分除去。
PI的吸湿，除如上述直接暴露在纯水以外，也会由大气中的湿气引起，但是前者一方大致等于浸渍状态，被认为是显著地吸湿。因此，如果该切割后的清洗导致的吸湿能够回避，则PI的吸湿度能显著地降低。
依据本发明的制造方法，能使半切分割、及纯水清洗在PI形成前结束。即，能够在图8所示的工序8前，在工序7的阶段进行半切切割，进行纯水清洗。
由此，在PI形成后，不需要PI暴露及浸渍在剧烈吸湿的纯水的工序。
＜效果＞
依据本发明的实施方式，在碳化硅半导体装置，包括：n＋型衬底1、n＋型衬底1上形成的杂质浓度比n＋型衬底1低的漂移外延层2、漂移外延层2上形成的肖特基电极6、至少覆盖肖特基电极6的端部和漂移外延层2的端部及侧面而形成的作为绝缘膜的PI8。
依据这样的碳化硅半导体装置，通过设为使PI8也覆盖芯片的角及芯片侧面的构造，能够抑制芯片测试以后发生的放电现象。特别是，通过以PI8覆盖漂移外延层2的侧面，能够抑制来自容易产生放电的漂移外延层2和n＋型衬底1的交界的放电。
另一方面，槽形成得越深，聚酰亚胺的形成越困难，由此，能够限于能良好地形成聚酰亚胺的范围。
进而在衬底状态形成PI，所以量产性优异。
另外，依据本发明的实施方式，在碳化硅半导体装置，作为绝缘膜的PI8，不覆盖漂移外延层2附近以外的n＋型衬底1的侧面。
依据这样的碳化硅半导体装置，能够抑制芯片测试以后发生的放电现象，并且在槽11内良好地形成PI8。在槽11内能有效地形成PI8，由此量产性优异。
另外，依据本发明的实施方式，在碳化硅半导体装置的制造方法，包括：（a）在n＋型衬底1上，形成杂质浓度比n＋型衬底1低的漂移外延层2的工序，（b）在漂移外延层2上，形成多个肖特基电极6的工序，（c）在各肖特基电极6所夹着的漂移外延层2上，形成比漂移外延层2下表面深的槽11的工序，（d）至少覆盖肖特基电极6的端部和漂移外延层2的端部及露出的侧面而形成作为绝缘膜的PI8的工序，（e）从形成有槽11的部分分割n＋型衬底1的工序。
依据这样的碳化硅半导体装置的制造方法，能够抑制芯片测试以后发生的放电现象，并且在槽11内良好地形成PI8。在槽11内能有效地形成PI8，由此量产性优异。
另外，依据本发明的实施方式，在碳化硅半导体装置的制造方法，工序（c）是形成到漂移外延层2下表面、或该下表面附近的n＋型衬底1的深度的槽11的工序。
依据这样的碳化硅半导体装置的制造方法，能在槽11内良好地形成PI8。
另外，依据本发明的实施方式，在碳化硅半导体装置的制造方法，还包括：（f）在工序（d）前，用纯水清洗n＋型衬底1上及漂移外延层2上的工序。
依据这样的碳化硅半导体装置的制造方法，能够防止吸湿性高的PI暴露及浸渍在纯水，能够抑制PI的吸湿导致的放电的发生。
＜实施方式2＞
＜制造方法＞
在实施方式1，在PI8形成前，将n＋型衬底1利用刀片切割半切而形成槽11。由此，实现使聚酰亚胺也覆盖芯片的角及芯片侧面的构造。
然而，也可以在将n＋型衬底1下表面粘贴于片的状态下，在全切切割（完全的分割）后涂敷PI。
在因PI涂敷而邻接芯片溶接，从而对芯片分割招致障碍的情况下，在全切切割后对片进行扩展（expand），在其后涂敷PI是有效的。由此，能够防止邻接芯片因PI涂敷而溶接。
＜变形例＞
此外，在实施方式1及2，关于使用Ti作为肖特基电极的情况进行了描述，但也可以使用其他的Ni、W、Mo等的金属。
进而，即使在SiC-SBD以外的器件、JBS（Junction Barrier Schottky：结势垒肖特基）、MOSFET等其他半导体器件，也同样能防止芯片以后的放电现象。
＜效果＞
依据本发明的实施方式，在碳化硅半导体装置的制造方法，工序（c）是将n＋型衬底1下表面固定到片，形成到n＋型衬底1下表面的深度的槽11的工序。
依据这样的碳化硅半导体装置的制造方法，通过在侧面整体涂敷PI，能够更有效地抑制芯片测试以后发生的放电现象。
另外，依据本发明的实施方式，在碳化硅半导体装置的制造方法，工序（e）是将固定于片的n＋型衬底1，利用片的扩展进行分割的工序。
依据这样的碳化硅半导体装置的制造方法，邻接的芯片彼此能够防止由于PI涂敷而溶接。
在本发明的实施方式，关于各构成因素的材质、材料、实施的条件等也进行了记载，但这些是例示，不受记载所限。
此外本发明，在其发明的范围内，能自由组合各实施方式、或者变形各实施方式的任意的构成因素、或在各实施方式省略任意的构成因素。
附图标记说明：
1　n＋型衬底，2　漂移外延层，3　终端p型注入层，4　SiO2热氧化膜，5　欧姆电极，6　肖特基电极，7　表面垫片，8　PI（聚酰亚胺），9　背面金属层，10　表面电极垫片开口部，11　槽，100　切割线开口部。

Claims (5)

1.一种碳化硅半导体装置的制造方法，其特征在于，包括：
(a)在碳化硅半导体衬底(1)上，形成杂质浓度比所述碳化硅半导体衬底(1)低的外延层(2)的工序；
(b)在所述外延层(2)上，形成多个电极(6)的工序；
(c)在各所述电极(6)所夹着的所述外延层(2)上，形成比所述外延层(2)下表面深的槽(11)的工序；
(d)至少覆盖所述电极(6)的端部、和所述外延层(2)的端部及露出的侧面而形成绝缘膜(8)的工序；以及
(e)仅从形成有所述槽(11)的部分分割所述碳化硅半导体衬底(1)的工序，
该碳化硅半导体装置的制造方法还包括：(f)在所述工序(d)前，用纯水清洗所述碳化硅半导体衬底(1)上及所述外延层(2)上的工序。
2.如权利要求1所述的碳化硅半导体装置的制造方法，其特征在于，
所述工序(c)是形成到所述外延层(2)下表面，或该下表面附近的所述碳化硅半导体衬底(1)的深度的所述槽(11)的工序。
3.如权利要求1所述的碳化硅半导体装置的制造方法，其特征在于，
所述工序(c)是将所述碳化硅半导体衬底(1)下表面固定到片，形成到所述碳化硅半导体衬底(1)下表面的深度的所述槽(11)的工序。
4.如权利要求3所述的碳化硅半导体装置的制造方法，其特征在于，
所述工序(e)是利用所述片的扩展，分割固定于所述片的所述碳化硅半导体衬底(1)的工序。
5.如权利要求1或2所述的碳化硅半导体装置的制造方法，其特征在于，
所述工序(e)是利用机械断开来分割所述碳化硅半导体衬底(1)的工序。
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