CN114944426A - 碳化硅半导体装置及碳化硅半导体装置的制造方法 - Google Patents

碳化硅半导体装置及碳化硅半导体装置的制造方法 Download PDF

Info

Publication number
CN114944426A
CN114944426A CN202111613299.4A CN202111613299A CN114944426A CN 114944426 A CN114944426 A CN 114944426A CN 202111613299 A CN202111613299 A CN 202111613299A CN 114944426 A CN114944426 A CN 114944426A
Authority
CN
China
Prior art keywords
semiconductor substrate
silicon carbide
electrode
silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111613299.4A
Other languages
English (en)
Inventor
大瀬直之
内海诚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN114944426A publication Critical patent/CN114944426A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供能够在具备AlSi电极的碳化硅半导体装置中使成品率提高的碳化硅半导体装置及碳化硅半导体装置的制造方法。通过溅射在由碳化硅构成的半导体基板的表面设置有由包含硅的铝合金构成的AlSi电极。在AlSi电极中析出有Si结节。AlSi电极在成为至少与键合线的接合部的部分中，以相对于该接合部处的Si结节的总面积为10％以上的面积比率包含枝晶结构的Si结节。AlSi电极中的Si结节的高度在枝晶结构和棱柱结构中的任一结构的Si结节中均为2μm以下。在AlSi电极的溅射时，将半导体基板的温度或AlSi电极的形成区域周边的温度、或者这两种温度设为430℃以上且500℃以下。

Description

碳化硅半导体装置及碳化硅半导体装置的制造方法
技术领域
本发明涉及碳化硅半导体装置及碳化硅半导体装置的制造方法。
背景技术
以往，作为半导体基板的正面的表面电极的电极材料，而使用包含硅(Si)的铝(Al)。半导体基板的正面的表面电极以埋入到层间绝缘膜的接触孔的方式形成。因此，作为使以包含硅的铝为电极材料的表面电极(以下，设为AlSi电极)的埋入性提高的方法，提出了一边通过溅射进行沉积(形成)一边通过热处理(回流)使其软化而进行埋入的回流溅射等。
在将硅(Si)作为半导体材料的情况下，如果以半导体基板与AlSi电极接触的状态暴露于高温中，则容易发生半导体基板中的硅原子与AlSi电极中的铝原子之间的相互扩散。从AlSi电极中扩散到半导体基板中的铝原子与半导体基板中的硅原子合金化，并成为从AlSi电极向半导体基板中局部地突出的突出部(合金尖刺，alloy spike)。如果合金尖刺发展达到半导体基板的内部的pn结，则担心由特性劣化而引起元件不良。
从半导体基板中扩散到AlSi电极中的硅原子在AlSi电极的、与半导体基板之间的界面附近作为硅(Si)结节(nodule)析出，并且在半导体基板与AlSi电极之间的界面处的电阻变高。已知通过将AlSi电极的溅射时的半导体基板的温度设为比较低的温度(小于300℃左右)，从而抑制半导体基板中的硅原子与AlSi电极中的铝原子之间的相互扩散，并抑制合金尖刺的发展和Si结节的析出。
此外，在层间绝缘膜的接触孔的纵横比大的情况等，使用利用化学气相沉积(CVD：Chemical Vapor Deposition)法，将埋入性比铝的埋入性高的钨(W)埋入到层间绝缘膜的接触孔的方法。通过在埋入到层间绝缘膜的接触孔内的钨插塞(W插塞)上沉积AlSi电极，从而AlSi电极与半导体基板不直接接触，因此，抑制合金尖刺的产生。
另一方面，在将碳化硅(SiC)作为半导体材料的情况下，即使将AlSi电极的溅射时的半导体基板的温度设为300℃以上，也难以产生合金尖刺。其理由是因为，除了碳化硅本身的扩散系数小(碳化硅的碳原子与硅原子之间的结合能大)以外，还通过在半导体基板与AlSi电极之间形成用于与半导体基板欧姆接触的硅化物膜，来抑制半导体基板中的硅原子与AlSi电极中的铝原子之间的相互扩散。
作为以硅为半导体材料的以往的硅半导体装置的制造方法，提出了如下方法：通过将AlSi电极的溅射时的半导体基板的温度设定为与AlSi电极的金属材料的再结晶温度接近的温度以下，从而抑制Si结节的析出(例如，参照下述专利文献1)。在下述专利文献1中，通过将AlSi电极的溅射时的半导体基板的温度设为扩散到AlSi电极中的硅原子难以成为粒状的170℃以下，从而使AlSi电极中的Si结节的析出为大致0％。
此外，作为以往的硅半导体装置的另一制造方法，提出了如下方法：在将半导体基板的温度设为150℃的低温度的状态和将半导体基板的温度设为350℃的高温度的状态下，连续地进行溅射而沉积AlSi电极(例如，参照下述专利文献2)。在下述专利文献2中，在低温度下沉积的AlSi电极中的Si结节被在高温度下沉积的AlSi电极中的Si结节吸收而生长，因此，在AlSi电极的总厚度的中间的深度析出Si结节，并与下层的阻挡金属分离。
此外，在以往的硅半导体装置的另一制造方法中，报告了如下情况：在通过溅射而沉积的AlSi电极中析出的粗大的硅析出物(Si析出物)在将键合线压接到AlSi电极时被强力地按压向半导体基板，产生从Si析出物被按压的位置到达半导体基板的裂纹(例如，参照下述非专利文献1)。在下述非专利文献1中，报告了有可能由于因Si析出物而产生的裂纹而引起元件损坏，并使成品率降低。
现有技术文献
专利文献
专利文献1：日本专利第3083301号公报
专利文献2：日本特开2000-164593号公报
非专利文献
非专利文献1：后藤裕史及另外4位，面向Si-IGBT的高强度铝合金电极材料，R&D神户制钢技报(Research and Development KOBE STEELEN GINEERING REPORTS)，神户制钢所，2005年9月，第65卷，第2号，p.58-61
发明内容
技术问题
如上所述，在将碳化硅作为半导体材料的情况下，能够不使用基于CVD法的W插塞的埋入等，而仅使用溅射来提高AlSi电极的埋入性。然而，发明人等反复进行深入研究的结果是明确了：如果将AlSi电极的溅射时的半导体基板的温度设为300℃以上，则在AlSi电极中析出的Si结节在AlSi电极的厚度方向(与半导体基板的表面正交并远离半导体基板的表面的方向)上以棱柱状进行晶粒生长而扩大。
明确了：如果AlSi电极中的Si结节扩大，则在引线键合工序中由施加到AlSi电极的载荷和/或超声波振动等引起的损伤介由AlSi电极中的Si结节而传递到半导体基板，并在Si结节附近产生到达半导体基板的内部的裂纹，或者键合线从半导体基板剥离。在上述非专利文献1中报告了对于由于该Si结节而在半导体基板产生裂纹的问题，在将硅作为半导体材料的情况下也同样产生。
此外，在AlSi电极中析出Si结节的情况下，在将AlSi电极图案化而残留在预定位置时，需要在利用湿蚀刻将AlSi电极去除之后，利用干蚀刻将残留在阻挡金属上的Si结节去除。然而，为了利用干蚀刻将在AlSi电极的厚度方向上以棱柱状进行晶粒生长而扩大并增加了高度的Si结节去除，需要延长干蚀刻时间，对AlSi电极的下层的阻挡金属的可靠性产生不良影响。
在上述专利文献1中，由于AlSi电极的溅射时的半导体基板的温度低至170℃以下，所以存在AlSi电极的埋入性差的问题。在上述专利文献2中，虽然连续进行在低温下的溅射和在高温下的溅射来沉积AlSi电极，但难以在溅射过程中改变半导体基板的温度。此外，用于功率器件的AlSi电极的厚度厚达4μm～6μm左右，即使应用上述专利文献2来沉积AlSi电极，也难以得到其效果。
本发明为了解决上述现有技术的问题，其目的在于提供能够在具备AiSi电极的碳化硅半导体装置中提高成品率的碳化硅半导体装置及碳化硅半导体装置的制造方法。
技术方案
为了解决上述课题，并实现本发明的目的，本发明的碳化硅半导体装置具有以下特征。具备：半导体基板，其由碳化硅构成；以及表面电极，其设置于所述半导体基板的表面，并由包含硅的铝合金构成。在所述表面电极的内部析出有硅结节。所述表面电极在成为至少与键合线的接合部的部分中，以相对于该接合部处的硅结节的总面积为10％以上的面积比率包含枝晶结构的硅结节。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述表面电极的内部的硅结节的高度比所述表面电极的厚度低。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述表面电极的内部的硅结节的高度比所述表面电极的、因接合所述键合线而相对变薄的所述接合部的厚度低。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述表面电极的内部的硅结节的高度为2μm以下。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述表面电极相对于铝以0.5wt％以上且3wt％以下含有硅。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述碳化硅半导体装置还具备阻挡金属，所述阻挡金属设置于所述半导体基板与所述表面电极之间，并防止杂质原子从所述半导体基板侧向所述表面电极扩散、或者杂质原子从所述表面电极侧向所述半导体基板扩散、或者这两种扩散。
此外，本发明的碳化硅半导体装置的特征在于，在上述发明中，所述碳化硅半导体装置还具备硅化物膜，所述硅化物膜设置于所述半导体基板与所述表面电极之间，并与所述半导体基板欧姆接触。
此外，为了解决上述课题，并实现本发明的目的，本发明的碳化硅半导体装置的制造方法是具备由碳化硅构成的半导体基板以及设置于所述半导体基板的表面并且由包含硅的铝合金构成的表面电极的碳化硅半导体装置的制造方法，并具有以下特征。包括沉积工序，所述沉积工序通过溅射在由碳化硅构成的所述半导体基板的表面沉积由包含硅的铝合金构成的所述表面电极。在所述沉积工序中，将所述半导体基板的温度或所述表面电极的形成区域周边的温度、或者这两种温度设为430℃以上且500℃以下。
此外，本发明的碳化硅半导体装置的制造方法的特征在于，在上述发明中，在所述沉积工序中，在所述表面电极的成为至少与键合线的接合部的部分中，使在所述表面电极的内部析出的硅结节中的枝晶结构的硅结节的面积比率相对于该接合部处的硅结节的总面积为10％以上。
根据上述发明，AlSi电极(表面电极)中的硅结节不会被键合线按压向半导体基板，因此，能够抑制到达半导体基板的内部的裂纹的产生、和/或键合线的剥离。此外，根据上述发明，通过将AlSi电极的溅射时的半导体基板的温度或AlSi电极的形成区域周边的温度设为430℃以上，从而能够使AlSi电极的埋入性提高。
发明效果
根据本发明的碳化硅半导体装置及碳化硅半导体装置的制造方法，起到能够在具备AiSi电极的碳化硅半导体装置中提高成品率的效果。
附图说明
图1为示出从半导体基板的正面侧观察实施方式的碳化硅半导体装置而得的布局的截面图。
图2为示出图1的剖切线A-A’处的截面结构的截面图。
图3为示意性地示出AlSi电极的溅射时的半导体基板的温度与AlSi电极的晶体结构之间的关系的说明图。
图4为示出实验例1的AlSi电极的溅射时的半导体基板的温度与AlSi电极中的Si结节的高度之间的关系的特性图。
图5为示意性地示出从半导体基板的正面侧观察图4的试样A～D的Si结节而得的状态的俯视图。
图6为示出实验例1的AlSi电极的溅射时的半导体基板的温度与AlSi电极中的Si结节的面积比率之间的关系的图表。
图7为示意性地示出实验例2的AlSi电极的与键合线的接合部的截面图。
符号说明
1：半导体基板
2：层间绝缘膜
3：阻挡金属
4：AlSi电极
4a：源极电极
4b：栅极焊盘
4c：AlSi电极的接合部
5：钝化膜
5a、5b：钝化膜的开口部
6：硅化物膜
7：表面电极
10：碳化硅半导体装置
11：键合线
11a：键合线的接合部
12：焊料层
13：安装基板
21：有源区
22：边缘终端区
t1、t2：AlSi电极的厚度
具体实施方式
以下，参照附图对本发明的碳化硅半导体装置及碳化硅半导体装置的制造方法的优选实施方式进行详细说明。在本说明书和附图中，在前缀有n或p的层和区域中，分别表示电子或者空穴为多数载流子。此外，标记于n或p的+和-分别表示杂质浓度比未标记+和-的层或区域的杂质浓度高和低。应予说明，在以下的实施方式的说明和附图中，对同样的构成标记相同的符号，并省略重复的说明。
(实施方式)
对实施方式的碳化硅半导体装置的结构进行说明。图1为示出从半导体基板的正面侧观察实施方式的碳化硅半导体装置而得的布局的截面图。在图1中示出碳化硅半导体装置10的安装后的状态。在图1中，利用虚线示出钝化膜5的开口部5a、5b，并省略图示焊料层12和安装基板13。图2为示出图1的剖切线A-A’处的截面结构的截面图。在图2中，省略图示碳化硅半导体装置10的元件结构(半导体基板1的内部的各部分)。
图1、图2所示的实施方式的碳化硅半导体装置10在由碳化硅(SiC)构成的半导体基板(半导体芯片)1的主面具备以包含硅(Si)的铝(Al)合金为电极材料的表面电极(以下，设为AlSi电极)4。在图1、图2中示出在半导体基板1的正面具备AlSi电极4的纵向型半导体装置作为碳化硅半导体装置10，但只要在半导体基板1的至少一个主面具备至少1个AlSi电极4即可，其他构成能够进行各种变更。
半导体基板1可以是从半导体晶锭(半导体单晶棒)切出并单片化为芯片状的体基板，也可以是在体基板(起始基板)上生长了预定导电型的外延层的外延基板。在半导体基板1设置有：有源区21、以及包围有源区21的周围的边缘终端区22。有源区21是在碳化硅半导体装置10导通时流通有主电流的区域。有源区21设置于例如半导体基板1的大致中央。
边缘终端区22是有源区21与半导体基板1的端部之间的区域，并且具有缓和半导体基板1的正面侧的电场而保持耐压的功能。耐压是指不引起碳化硅半导体装置10误动作和/或损坏的极限的电压。在边缘终端区22配置有场限环(FLR：Field Limiting Ring)和/或结终端扩展(JTE：Junction Termination Extension)结构等耐压结构(未图示)。
在有源区21中，在半导体基板1的正面设置有1个以上(在这里为2个)的AlSi电极4。在图1中，示出将实施方式的碳化硅半导体装置10设为MOSFET(Metal OxideSemiconductor Field Effect Transistor：具备由金属-氧化膜-半导体的3层结构构成的绝缘栅极的MOS型场效应晶体管)，并配置有作为源极电极4a发挥功能的AlSi电极4以及作为栅极焊盘4b发挥功能的AlSi电极4的情况。
对于AlSi电极4的构成将在后面进行描述。在半导体基板1的正面侧，作为碳化硅半导体装置10的元件结构，设置有通常的沟槽栅极结构(未图示)。符号2是选择性地设置于半导体基板1的正面上的层间绝缘膜或场绝缘膜、或者它们的层叠绝缘膜。在这里，设为层间绝缘膜2。可以在层间绝缘膜2的表面和在层间绝缘膜2的接触孔露出的半导体基板1的正面与AlSi电极4之间设置阻挡金属3。
阻挡金属3防止金属原子向半导体基板1侧的扩散、和/或在夹着阻挡金属3而相邻的各部分之间的相互作用。通过阻挡金属3，抑制铝原子从AlSi电极4向层间绝缘膜2扩散。阻挡金属3为例如钛(Ti)膜或氮化钛(TiN)膜、或者它们的层叠金属膜。可以在阻挡金属3(在不设置阻挡金属3的情况下为AlSi电极4)与半导体基板1之间设置与半导体基板1欧姆接触的硅化物膜6。
源极电极4a通过介由阻挡金属3和硅化物膜6或者仅介由硅化物膜6与半导体基板1的正面电连接，从而与在半导体基板1的正面露出的n+型源极区和p++型接触区电连接。源极电极4a覆盖有源区21中的、除配置有栅极焊盘4b的区域以外的区域的大致整个面。源极电极4a中的、在后述的钝化膜5的开口部5a露出的部分作为源极焊盘(电极焊盘)而发挥功能。
栅极焊盘(电极焊盘)4b与例如源极电极4a同时形成，并在与源极电极4a同一层，与源极电极4a分开地配置。栅极焊盘4b介由由多晶硅(poly-Si)构成的栅极流道(未图示)与MOSFET的所有栅极电极(未图示)电连接。栅极流道配置于边缘终端区22，并包围有源区21的周围。栅极焊盘4b在钝化膜5的开口部5b露出。
半导体基板1的正面被钝化膜5覆盖。在钝化膜5的各开口部5a、5b分别露出不同的AlSi电极4(源极电极4a和栅极焊盘4b)。钝化膜5的开口部5a、5b与在其自身露出的AlSi电极4相比表面积更小。在钝化膜5的各开口部5a、5b露出的AlSi电极4分别接合有不同的键合线11(栅极焊盘4b的键合线11未图示)。
键合线11的一端与AlSi电极4接合，另一端与引线框架(后述的安装基板13)的引线(未图示)接合。键合线11通过通常的引线键合而压接于AlSi电极4，并且在与AlSi电极4的接合部11a被压扁。AlSi电极4被键合线11压扁，并且在与键合线11的接合部4c处的剩余厚度t2比AlSi电极4的其他部分的厚度(沉积时或图案化(加工)后的厚度)t1薄。
遍及半导体基板1的整个背面，而设置有作为漏极电极发挥功能的表面电极7。通过表面电极7介由焊料层12接合到作为例如引线框架的安装基板13的裸片垫(Die pad)上，从而将碳化硅半导体装置10安装到安装基板13的正面上。安装基板13例如可以是在陶瓷基板的两面分别形成有由例如铜(Cu)箔等导电性板构成的电路图案的DCB(Direct CopperBond：直接铜键合)基板。
在安装接合有键合线11的一端的半导体基板1的安装基板13与接合有键合线11的另一端的引线(未图示)之间，以覆盖半导体基板1和键合线11的方式设置有环氧树脂等热固性的树脂。在安装基板13的周缘粘接有树脂壳体(未图示)的情况下，在树脂壳体与安装基板13之间以覆盖半导体基板1和键合线11的方式填充有环氧树脂等封装材料。
接下来，对AlSi电极4的构成进行说明。图3为示意性地示出AlSi电极的溅射时的半导体基板的温度与AlSi电极的晶体结构之间的关系的说明图。AlSi电极4是在将半导体基板1的温度或AlSi电极4的形成区域周边的温度、或者这两者的温度(以下，设为半导体基板1的温度或AlSi电极4的形成区域周边的温度)设为430℃以上左右且低于AlSi电极4的电极材料的熔点的高温的状态下，通过溅射而沉积于阻挡金属3上。
AlSi电极4的电极材料的熔点(凝固点)为基于AlSi电极4的电极材料的组成的共晶反应的液相点(液相线上的结晶点)的温度，例如为530℃左右。因此，通过提高AlSi电极4的溅射时的半导体基板1的温度或AlSi电极4的形成区域周边的温度，从而使AlSi电极4的埋入性提高，并且由于在设为例如500℃以下左右进行溅射时不会使AlSi电极4过于柔软(不会使其流动)，所以能够维持AlSi电极4的厚度t1。
AlSi电极4的厚度t1的上限值为基于溅射装置的层叠精度或干蚀刻装置的加工能力的极限的厚度，例如为5μm左右。优选AlSi电极4的厚度t1尽可能厚，并且AlSi电极4的厚度t1越厚，越能够使导通损耗降低。通过如上述那样将键合线11压接到AlSi电极4，从而AlSi电极4的、与键合线11的接合部4c处的剩余厚度t2在最薄的部分为例如2.1μm左右(参照图7)。
AlSi电极4相对于铝以例如0.5wt％以上且3wt％以下左右含有硅。通过在AlSi电极4中包含硅，从而抑制半导体基板1中的硅原子与AlSi电极4中的铝原子之间的相互扩散，并抑制合金尖刺的发展。AlSi电极4还可以相对于铝以0.1wt％以上且5wt％以下左右含有铜(Cu)。通过在AlSi电极4中包含铜，从而AlSi电极4的强度提高。更优选的是，AlSi电极4的铜相对于铝的含有率可以为0.5wt％以上且2wt％以下左右。
此外，AlSi电极4在阻挡金属3与AlSi电极4之间的界面附近，遍及AlSi电极4的面内大致均匀地包含硅(Si)结节。Si结节是以超过AlSi电极4的硅的固溶极限而析出的硅原子为核进行晶粒生长而成的硅析出物(Si结晶)。AlSi电极4在至少与键合线11的接合部4c中，以相对于在该接合部4c处的Si结节的总面积为10％以上的面积比率包含枝晶结构的Si结节。
只要在AlSi电极4中以上述面积比率包含枝晶结构的Si结节即可，可以在AlSi电极4中混合有枝晶结构的Si结节和除枝晶结构以外的Si结节。通过本发明人等的深入研究而确认：为了在AlSi电极4中以上述面积比率析出枝晶结构的Si结节，只要将AlSi电极4的溅射时的半导体基板1的温度或AlSi电极4的形成区域周边的温度设为430℃以上即可(由图3的矩形框30包围的Si结晶)。
枝晶结构的Si结节是在与AlSi电极4的厚度方向(与半导体基板1的表面正交并远离半导体基板1的表面的方向)大致正交的方向上如伸展树枝那样以树枝状进行晶粒生长而成的硅(Si)结晶。除枝晶结构以外的Si结节是在AlSi电极4的厚度方向上以棱柱状进行晶粒生长而成的棱柱结构的Si结节。Si结节的面积是从半导体基板1的正面侧观察到的Si结节的平面形状的面积(表面积)。
例如，在将硅作为半导体材料的情况下，如上述那样将AlSi电极的溅射时的半导体基板的温度设为低于300℃，因此AlSi电极中的Si结节几乎全部成为棱柱结构(由图3的矩形框130包围的Si结晶)。例如，在AlSi电极的溅射时的半导体基板的温度为400℃以下的情况下，AlSi电极中的Si结节几乎全部成为棱柱结构。此时的棱柱结构的Si结节的高度在AlSi电极4的厚度方向上最大达到5μm左右。
另一方面，如果AlSi电极4的溅射时的半导体基板1的温度或AlSi电极4的形成区域周边的温度超过400℃，则AlSi电极4中的Si结节的析出形态从棱柱结构变化为枝晶结构。而且，通过如本实施方式那样将AlSi电极4的溅射时的半导体基板1的温度或AlSi电极4的形成区域周边的温度设为430℃以上，从而能够使AlSi电极4中的枝晶结构的Si结节以上述面积比率析出。
越提高AlSi电极4的溅射时的半导体基板1的温度或AlSi电极4的形成区域周边的温度，则AlSi电极4中的枝晶结构的Si结节的个数(面积比率)越增加。枝晶结构的Si结节的个数越增加，则AlSi电极4中的棱柱结构的Si结节的个数越减少。在溅射时的AlSi电极4中(AlSi固溶体中)，枝晶结构的Si结节中的硅浓度比棱柱结构的Si结节中的硅浓度高。
AlSi电极4中的Si结节的高度(AlSi电极4的厚度方向上的高度)在枝晶结构和棱柱结构中的任一种结构的Si结节中，均比AlSi电极4的剩余厚度t2低，为2μm以下左右(参照图4～图6)。这是因为，枝晶结构的Si结节仅生长至1μm以下的高度，除此以外，如上述那样在AlSi电极4的溅射中，Si结节的析出形态从棱柱结构变化为枝晶结构，棱柱结构的Si结节不会生长超过2μm。
接下来，对实施方式的碳化硅半导体装置10的制造方法进行说明。首先，准备由碳化硅构成的半导体晶片。在半导体晶片的、在切割(切断)后成为半导体芯片(半导体基板1)的区域的正面侧形成预定的元件结构。例如，在实施方式的碳化硅半导体装置10为n沟道型的纵向型MOSFET的情况下，预定的元件结构为p型基区、n+型源极区、p++型接触区、以及由栅极绝缘膜和栅极电极构成的绝缘栅极(MOS栅极)结构。
接下来，通过在半导体晶片的正面形成层间绝缘膜2并选择性地去除层间绝缘膜2，从而在层间绝缘膜2的预定位置形成接触孔。接下来，形成与半导体晶片的正面的、在层间绝缘膜2的接触孔露出的部分欧姆接触的硅化物膜6。接下来，在层间绝缘膜2的表面和硅化物膜6的表面形成阻挡金属3。在阻挡金属3为层叠金属膜的情况下，可以在形成硅化物膜6之前，利用阻挡金属3的下层的金属膜仅覆盖层间绝缘膜2的表面来进行保护。
接下来，在通常的溅射装置(未图示)的工作台上，以背面为工作台侧载置半导体晶片，并通过例如静电卡盘(ESC：Electric Static Chuck)等保持在工作台上。接下来，通过利用例如加热器等加热单元对溅射装置的腔室(处理炉)内或工作台进行加热，从而在使半导体晶片的温度或AlSi电极4的形成区域周边的温度上升到430℃以上的状态下，通过溅射在阻挡金属3上沉积AlSi电极4。
接下来，从溅射装置的工作台取下，而将半导体晶片在常温(加热和冷却均未进行的状态)下放置并冷却，由此，使半导体晶片降温。如此，将AlSi电极4的溅射时的半导体晶片的温度或AlSi电极4的形成区域周边的温度设为430℃以上，并且在溅射后使半导体晶片在常温下降温，从而形成以上述预定的面积比率包含枝晶结构的Si结节的AlSi电极4。
除此之外，AlSi电极4中的Si结节的高度在枝晶结构和棱柱结构中的任一种结构的Si结节中均成为2μm以下左右。接下来，通过使用通常的干蚀刻装置对AlSi电极4进行蚀刻(图案化)从而使其残留在预定位置。在该图案化后残留在预定位置的AlSi电极4相当于图1的源极电极4a和栅极焊盘4b。接下来，在半导体晶片的背面侧形成元件结构，并在半导体晶片的背面形成表面电极7。
接下来，通过切割半导体晶片而单片化为各个芯片(半导体基板1)状，从而完成图1、图2的实施方式的碳化硅半导体装置10。接下来，介由焊料层12将半导体基板1的表面电极7接合到作为例如引线框架的安装基板13的裸片垫或成为引线的布线层上，从而将碳化硅半导体装置10安装到安装基板13的正面上。接下来，通过通常的引线键合工序，将键合线11压接并接合到半导体基板1的AlSi电极4。
此时，AlSi电极4的在与键合线11的接合部4c处的剩余厚度t2比AlSi电极4的其他部分的厚度t1薄，成为例如2.1μm左右，但是，不会发生像以往方法那样的键合线11的剥离。其理由是因为，如上述那样在AlSi电极4中以上述预定的面积比率包含枝晶结构的Si结节，并且AlSi电极4中的Si结节的高度为2μm以下左右。如此，完成安装了碳化硅半导体装置10的半导体封装。
(实验例1)
对AlSi电极4的溅射时的半导体基板1的温度与Si结节的高度之间的关系进行验证。图4为示出实验例1的AlSi电极的溅射时的半导体基板的温度与AlSi电极中的Si结节的高度之间的关系的特性图。图5为示意性地示出从半导体基板的正面侧观察图4的试样A～D的Si结节而得的状态的俯视图。图6为示出实验例1的AlSi电极的溅射时的半导体基板的温度与AlSi电极中的Si结节的面积比率之间的关系的图表。
准备在由碳化硅构成的半导体基板(半导体芯片)上通过对该半导体基板的温度进行各种变更并进行溅射而以5μm的厚度沉积AlSi电极而得的多个试样(以下，设为实验例1)。这些试样针对AlSi电极的溅射时的半导体基板的每个温度各制作多个。对所有试样的AlSi电极进行湿蚀刻而使Si结节露出，并测定从半导体基板的正面侧观察到的Si结节的尺寸和Si结节的高度(AlSi电极的厚度方向上的高度)。
在图4示出实验例1的AlSi电极的溅射时的半导体基板的温度与AlSi电极中的Si结节的高度之间的关系。在图5的(a)～(d)分别示意性地示出利用扫描电子显微镜(SEM：Scanning Electron Microscope)从半导体基板的正面侧观察将实验例1的AlSi电极的溅射时的半导体基板的温度设为200℃、350℃、400℃以及470℃的各试样A～D的AlSi电极中的Si结节而得的状态。
在图6示出计算实验例1的AlSi电极的Si结节的面积比率而得的结果。在图6中示出AlSi电极的溅射时(沉积时)的半导体基板的温度、Si结节的析出形态(棱柱、枝晶)、棱柱结构的Si结节的面积比率和高度(在图6中分别图示为棱柱比率和棱柱高度)、枝晶结构的Si结节的面积比率和高度(在图6中分别图示为枝晶比率和枝晶高度)、以及键合线剥离的有无(发生、未发生)。
根据图4～图6所示的结果，确认了在AlSi电极的溅射时的半导体基板的温度为400℃以下的情况下，AlSi电极中的Si结节全部成为棱柱结构(由图4的框41包围的部分。棱柱比率100％，参照图5的(a)～(c))。此外，确认了在AlSi电极的溅射时的半导体基板的温度为350℃以上且400℃以下的情况下，与AlSi电极接合的键合线剥离(图6的键合线剥离“发生”)。确认了此时的棱柱结构的Si结节的高度最大达到5μm(参照图5的(b)、图5的(c))。
确认了如果AlSi电极的溅射时的半导体基板的温度超过400℃，则在AlSi电极中混合有棱柱结构和枝晶结构的Si结节，但在AlSi电极的溅射时的半导体基板的温度低于430℃的情况下，与AlSi电极接合的键合线剥离。确认了此时的AlSi电极中的枝晶结构的Si结节的面积比率(枝晶比率)小于10％，棱柱结构的Si结节的高度(棱柱高度)超过2μm(参照图6)。
确认了在AlSi电极的溅射时的半导体基板的温度低于300℃的情况下，AlSi电极中的Si结节全部为棱柱结构，但棱柱结构的Si结节的高度为1μm以下(参照图4、图5的(a)，在图6中未图示)。确认了虽然与AlSi电极接合的键合线没有发生剥离，但在层间绝缘膜的接触孔的纵横比大的情况下，无法通过溅射将AlSi电极埋入到接触孔。
另一方面，确认了在AlSi电极的溅射时的半导体基板的温度为430℃以上的情况下(由图4的框42包围的部分)，与AlSi电极接合的键合线未剥离(图6的键合线剥离“未发生”)。确认了此时的AlSi电极中的枝晶结构的Si结节的面积比率(枝晶比率)和高度(枝晶高度)分别为10％以上和1μm以下，并且棱柱结构的Si结节的高度(棱柱高度)最大为2μm。
即，图6的AlSi电极的溅射时的半导体基板的温度设为430℃以上左右的试样的AlSi电极相当于本实施方式的AlSi电极4。在图6中，作为Si结节的面积比率，棱柱结构(棱柱比率)和枝晶结构(枝晶比率)都示出Si结节的总面积相对于AlSi电极的整个表面的面积(表面积)的比率，但是在设为在AlSi电极的一部分(例如与键合线的接合部)的面积处的Si结节的面积比率的情况下，也可得到同样的结果。
此外，确认了通过将AlSi电极的溅射时的半导体基板的温度设为430℃以上，从而即使层间绝缘膜的接触孔的纵横比大，也能够通过溅射将AlSi电极埋入到接触孔。因此，确认了通过将AlSi电极的溅射时的半导体基板的温度设为430℃以上，从而能够使基于溅射的AlSi电极的埋入性提高，并且能够防止键合线的剥离。
(实验例2)
对AlSi电极4的、与键合线11的接合部4c处的剩余厚度t2进行验证。图7为示意性地示出实验例2的AlSi电极的与键合线的接合部的截面图。准备按照上述实施方式的碳化硅半导体装置的制造方法，通过溅射在半导体基板1上以5μm的厚度沉积AlSi电极4，并通过引线键合将由铝构成的键合线11接合到AlSi电极4而得的试样(以下，设为实验例2)。
在图7示意性地示出利用SEM从与半导体基板1的正面平行的方向观察该试样的AlSi电极4(阴影部分)的、与键合线11的接合部4c而得的状态。根据图7所示的结果，确认了AlSi电极4被键合线11压扁，并且在与键合线11的接合部4c处的剩余厚度t2在最薄的部分变薄至AlSi电极4的其他部分的厚度(沉积时或图案化(加工)后的厚度)t1的一半左右的2.1μm左右的厚度t2’。
如以上说明的那样，根据实施方式，在AlSi电极中析出有Si结节，在AlSi电极的成为至少与键合线的接合部的部分，以相对于成为该接合部的部分处的Si结节的总面积为10％以上的面积比率包含枝晶结构的Si结节。由此，AlSi电极中的Si结节的高度成为比AlSi电极的、被键合线压扁而变薄的部分(AlSi电极的与键合线的接合部)的厚度低的2μm以下。
由此，AlSi电极中的Si结节不会被键合线按压向半导体基板，因此，能够抑制到达半导体基板的内部的裂纹的产生、和/或键合线的剥离。因此，能够提高成品率。此外，根据实施方式，通过将AlSi电极的溅射时的半导体基板的温度或AlSi电极的形成区域周边的温度设为430℃以上，从而能够使AlSi电极的埋入性提高，因此能够提高成品率。
以上，本发明不限于上述实施方式，能够在不脱离本发明的主旨的范围内进行各种变更。
工业上的可利用性
如上所述，本发明的碳化硅半导体装置及碳化硅半导体装置的制造方法对电力变换装置和/或各种工业用机械等的电源装置等所使用的功率半导体装置有用。

Claims (9)

1.一种碳化硅半导体装置，其特征在于，具备：
半导体基板，其由碳化硅构成；以及
表面电极，其设置于所述半导体基板的表面，并由包含硅的铝合金构成，
在所述表面电极的内部析出有硅结节，
所述表面电极在成为至少与键合线的接合部的部分中，以相对于该接合部处的硅结节的总面积为10％以上的面积比率包含枝晶结构的硅结节。
2.根据权利要求1所述的碳化硅半导体装置，其特征在于，
所述表面电极的内部的硅结节的高度比所述表面电极的厚度低。
3.根据权利要求2所述的碳化硅半导体装置，其特征在于，
所述表面电极的内部的硅结节的高度比所述表面电极的、因接合所述键合线而相对变薄的所述接合部的厚度低。
4.根据权利要求1至3中任一项所述的碳化硅半导体装置，其特征在于，
所述表面电极的内部的硅结节的高度为2μm以下。
5.根据权利要求1至4中任一项所述的碳化硅半导体装置，其特征在于，
所述表面电极相对于铝以0.5wt％以上且3wt％以下含有硅。
6.根据权利要求1至5中任一项所述的碳化硅半导体装置，其特征在于，
所述碳化硅半导体装置还具备阻挡金属，所述阻挡金属设置于所述半导体基板与所述表面电极之间，并防止杂质原子从所述半导体基板侧向所述表面电极扩散、或者杂质原子从所述表面电极侧向所述半导体基板扩散、或者这两种扩散。
7.根据权利要求1至6中任一项所述的碳化硅半导体装置，其特征在于，
所述碳化硅半导体装置还具备硅化物膜，所述硅化物膜设置于所述半导体基板与所述表面电极之间，并与所述半导体基板欧姆接触。
8.一种碳化硅半导体装置的制造方法，其特征在于，所述碳化硅半导体装置具备由碳化硅构成的半导体基板以及设置于所述半导体基板的表面并且由包含硅的铝合金构成的表面电极，
所述碳化硅半导体装置的制造方法包括沉积工序，所述沉积工序通过溅射在由碳化硅构成的所述半导体基板的表面沉积由包含硅的铝合金构成的所述表面电极，
在所述沉积工序中，将所述半导体基板的温度或所述表面电极的形成区域周边的温度、或者这两种温度设为430℃以上且500℃以下。
9.根据权利要求8所述的碳化硅半导体装置的制造方法，其特征在于，
在所述沉积工序中，在所述表面电极的成为至少与键合线的接合部的部分中，使在所述表面电极的内部析出的硅结节中的枝晶结构的硅结节的面积比率相对于该接合部处的硅结节的总面积为10％以上。
CN202111613299.4A 2021-02-17 2021-12-27 碳化硅半导体装置及碳化硅半导体装置的制造方法 Pending CN114944426A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021022958A JP2022125387A (ja) 2021-02-17 2021-02-17 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2021-022958 2021-02-17

Publications (1)

Publication Number Publication Date
CN114944426A true CN114944426A (zh) 2022-08-26

Family

ID=82801622

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111613299.4A Pending CN114944426A (zh) 2021-02-17 2021-12-27 碳化硅半导体装置及碳化硅半导体装置的制造方法

Country Status (3)

Country Link
US (1) US20220262905A1 (zh)
JP (1) JP2022125387A (zh)
CN (1) CN114944426A (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521515B1 (en) * 2000-09-15 2003-02-18 Advanced Micro Devices, Inc. Deeply doped source/drains for reduction of silicide/silicon interface roughness
US6955978B1 (en) * 2001-12-20 2005-10-18 Fairchild Semiconductor Corporation Uniform contact
JP4699812B2 (ja) * 2005-06-07 2011-06-15 株式会社デンソー 半導体装置およびその製造方法
US7109116B1 (en) * 2005-07-21 2006-09-19 International Business Machines Corporation Method for reducing dendrite formation in nickel silicon salicide processes
JP2009135453A (ja) * 2007-10-30 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
JP6455335B2 (ja) * 2015-06-23 2019-01-23 三菱電機株式会社 半導体装置
DE102016125030A1 (de) * 2016-12-20 2018-06-21 Infineon Technologies Ag Ausbilden einer Metallkontaktschicht auf Siliziumcarbid und Halbleitervorrichtung mit einer Metallkontaktstruktur

Also Published As

Publication number Publication date
US20220262905A1 (en) 2022-08-18
JP2022125387A (ja) 2022-08-29

Similar Documents

Publication Publication Date Title
US10020226B2 (en) Method for forming a semiconductor device and a semiconductor device
JP6253854B1 (ja) 半導体装置およびその製造方法、電力変換装置
US10573611B2 (en) Solder metallization stack and methods of formation thereof
US7812441B2 (en) Schottky diode with improved surge capability
CN103311317B (zh) 碳化硅半导体装置及其制造方法
JP6627359B2 (ja) 半導体装置および半導体装置の製造方法
US10651140B2 (en) Semiconductor device with metal structure electrically connected to a conductive structure
US9911686B2 (en) Source down semiconductor devices and methods of formation thereof
JP2004022878A (ja) 半導体装置およびその製造方法
US11658093B2 (en) Semiconductor element with electrode having first section and second sections in contact with the first section, and semiconductor device
US7368380B2 (en) Method of manufacturing semiconductor device
JP6695498B2 (ja) 炭化珪素半導体装置、電力変換装置、炭化珪素半導体装置の製造方法、および電力変換装置の製造方法
CN103069546B (zh) 半导体器件的制造方法
CN114944426A (zh) 碳化硅半导体装置及碳化硅半导体装置的制造方法
JP2019145667A (ja) 半導体装置および半導体装置の製造方法
JP4604633B2 (ja) 半導体装置とその製造方法
CN113140537A (zh) 功率半导体器件和用于制造功率半导体器件的方法
US20240055375A1 (en) Silicon carbide semiconductor device and method of manufacturing semiconductor device
CN114868231A (zh) 半导体元件及其制造方法、以及半导体装置及其制造方法
CN114467165A (zh) 半导体装置
US20230122575A1 (en) Semiconductor device and method for manufacturing semiconductor device
EP4358131A1 (en) Semiconductor device with stacked conductive layers and related methods
JP6918902B2 (ja) 半導体装置の製造方法
CN117913029A (zh) 具有堆叠导电层的半导体装置及相关方法
JPWO2020144790A1 (ja) 電力用半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination