CN1572025A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1572025A
CN1572025A CNA03801341XA CN03801341A CN1572025A CN 1572025 A CN1572025 A CN 1572025A CN A03801341X A CNA03801341X A CN A03801341XA CN 03801341 A CN03801341 A CN 03801341A CN 1572025 A CN1572025 A CN 1572025A
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mentioned
semiconductor
semiconductor element
section
work
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CN100403537C (zh
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北畠真
楠本修
内田正雄
高桥邦方
山下贤哉
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供一种半导体器件(半导体模块)及其制造方法。半导体模块具备在SiC衬底上、能够个别地工作的区段1(半导体元件)。区段1具备：设置在SiC衬底主面侧上源电极焊接区2及栅电极焊接区3和设置在SiC衬底的背面侧上的漏电极焊接区。具备用于使相邻接的区段1彼此之间电隔离的沟槽、肖特基二极管等元件隔离区。仅仅将经检查确认是合格品的区段1的电极焊接区2、3连接在电极端子41、43上。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件，该半导体器件具备多个由碳化硅(SiC)、GaN、金刚石等宽禁带宽度半导体构成的半导体元件。
背景技术
历来，为了控制大电流、实现低损耗，半导体功率器件都需要大面积。例如，正在市场上出售的单一功率器件，就是在4英寸以上大小的Si晶片全体上，集成多个作为半导体元件的纵型NISFET而成的器件(例如，参照文献：电气学会高性能高功能功率器件、功率IC调查专门委员会编：「功率器件、功率IC手册」、KORONA公司、1996年7月30日、P4)。集成多个纵型MISFET构成一个功率器件是为了分散电流流通区域，避免发热部的集中。
另一方面，使用碳化硅(SiC)、GaN、AlN等III族氮化物、金刚石等宽禁带宽度半导体构成的宽禁带宽度半导体器件，由于在材料物理特性上具有高速工作、高耐压、低损耗等优点，正在进行实用化的研究开发。
此外，用「SiC」表示的碳化硅和用「Si∶C」表示的含微量C(百分之几以下)的硅，是物理性质、化学性质不同的材料。
(解决课题)
但是，上述宽禁带宽度半导体材料，存在难于得到缺陷少的晶片的困难。
例如，在使用碳化硅(SiC)的情况下，将在碳化硅晶片上外延生长的薄膜作为沟道层使用，形成纵型MISFET，现在使用的SiC晶片有许多晶体缺陷，这是称为微管的贯通缺陷。在外延生长的薄膜中，当从微管延续的缺陷存在于MISFET、二极管等半导体元件的重要部分时，就成为绝缘击穿的原因，因而不能满足绝缘耐压等性能指标的要求。由于现在使用的SiC晶片的微管密度是数十个/cm2以上，当制作面积大于10mm2的功率器件时，在一个功率器件上必然存在包含几个以上微管的可能性。因此，当在SiC晶片上制作具有10mm2以上面积的SiC器件、特别是在SiC晶片上制作大电流功率器件时，由于在微管存在的区域上引起绝缘击穿，就存在那样的SiC器件的成品率几乎为零的问题。
另外，SiC以外的GaN、AlN等III族氮化物、金刚石等宽禁带宽度半导体晶片也包含高密度的、各种各样晶体缺陷，与上述SiC的情况同样，也存在因晶体缺陷引起的成品率降低的问题。
发明内容
本发明的目的在于：提供能够使用宽禁带宽度半导体，又确保高成品率、低成本制造的半导体器件及其制造方法。
本发明的半导体器件使用宽禁带宽度半导体层，在能够相互独立工作的多个半导体元件中，使特定半导体元件的各电极焊接区与电极端子相互电连接，特定半导体元件相互并联工作。
由此，能够使用缺陷多的宽禁带宽度半导体，又以高成品率得到作为整体发挥一个功能的半导体器件。
特别是，由于是将多个半导体元件预先形成在共同的衬底上，使特定半导体元件以外的半导体元件不工作，仅仅使用经检查合格的半导体元件，去除因缺陷判定为不合格的半导体元件，由此构成半导体器件，因此能够实现高成品率。
最好将特定半导体元件的个数预先规定为一定值。
由于具备作为肖特基二极管功能的元件隔离区域，以使多个半导体元件彼此之间电隔离，在半导体元件是MISFET的情况下，能够构成倒相器。
本发明的半导体器件制造方法是：预先形成具有由宽禁带宽度半导体构成的有源区，能够相互独立工作的多个半导体元件，将经检查确认合格的特定半导体元件的各电极焊接区分别连接在电极端子上，将特定半导体元件组装在一个管壳中的半导体器件制造方法。
根据本方法，能够使用缺陷率高的宽禁带宽度半导体，又能够以现实的成品率制造作为功率器件等发挥功能的半导体器件。
附图说明
图1是表示第1实施方式的半导体模块的关键部位的顶面图。
图2是表示第1实施方式的半导体模块中相邻接区段的一部分的结构的剖视图。
图3是表示第1实施方式的半导体模块中区段的一部分中的栅电极、源电极、杂质扩散层等的平面形状的俯视图。
图4(a)～(c)是表示第1实施方式的半导体模块制造工序的俯视图。
图5(a)、(b)依次分别是表示第2实施方式的半导体模块关键部位的顶面图，及半导体模块中的肖特基二极管的剖视图。
图6是表示第3实施方式的半导体模块关键部位的顶面图。
图7是表示第4实施方式的半导体模块中相邻接区段的一部分结构的剖视图。
具体实施方式
(实施方式1)
图1是表示第1实施方式的半导体模块(半导体器件)关键部位顶面图。如图1所示，本实施方式的半导体模块具备芯片5，芯片5形成在SiC衬底上，设置多个(在本实施方式中是9个)尺寸为1.5mm×1.5mm(2.25mm2)的区段1(半导体元件)。各区段1具备设置在SiC衬底主面侧上的源电极焊接区2及栅电极焊接区3，以及设置在SiC背面侧上的漏电极焊接区(图中未显示)。
各区段1具有电流容量2(A)，工作时流过每个区段的电流用直流换算是2(A)。如下述的图2所示，相邻接的区段1彼此之间的元件隔离，是在SiC衬底20的主侧面中、腐蚀区段1彼此之间的边界区域，形成沟槽，使各区段成为台式结构来进行的。使相邻接的区段1彼此之间的间隔d大于10μm，就能够在共同的SiC衬底20上设置多个能够确保耐压600V、并能够个别工作的区段1。
图2是表示相邻接的区段的一部分结构的剖视图。图3是表示区段的一部分中的栅电极、源电极、杂质扩散层等的平面形状的俯视图。
如图2所示，本实施方式的半导体模块具备：包含高浓度n型杂质的主面是(0001)解理面的SiC衬底20(6H-SiC衬底)；设置在外延层(有源区)内、包含低浓度n型杂质的n-SiC层23(漂移区)，外延层形成在SiC衬底20的上面上；设置在外延层上面上的栅绝缘膜26及绝缘膜26上的栅电极27；设置在外延层的上面上、包围栅电极27的源电极28；设置在SiC衬底20的下面上的漏电极29；在从外延层中的源电极28的下方区域到栅电极27的端部下方区域上、掺杂p型杂质形成的p-SiC层24；从外延层中的源电极27的端部下方到栅电极27的端部下方的整个区域上，掺杂n型杂质形成的源区25；在外延层的表面部中，位于栅电极27的下方的区域，导入低浓度的n型杂质形成的沟道区21。
如图3所示，栅电极27是在纵方向及横方向上、以一定间隔设置的具有开口而且连续连接而成的单一的部件。另一方面，源电极28是孤立地设置在栅电极27的开口中的多个部件。而且，源区25平面性地包围源电极28的周围，与源电极27的下方区域重叠。即在从各源区25到栅电极27的一部分区域上形成MISFET单元。一个MISFET单元的大小是数十平方微米量级。
另外，在外延层的上面设置由BPSG膜构成的第1层间绝缘膜33和源布线30及栅布线31。源布线30通过贯通第1层间绝缘膜33的插头30a与各源电极28连接，栅布线31通过贯通第1层间绝缘膜33的插头31a与栅电极27连接。进而，在第1层间绝缘膜33的上面设置由BPSG膜构成的第2层间绝缘膜34。而且，源电极焊接区2和栅电极焊接区3形成在第2层间绝缘膜34的上面上，源电极焊接区2通过贯通第2层间绝缘膜34的插头2a与源布线30连接，栅电极焊接区3通过贯通第2层间绝缘膜34的插头3a与栅布线31连接。插头2a仅仅形成在位于图1所示的源电极焊接区2的下方的区域，在本实施方式中，与所有的源电极28连接的源布线30通过插头2a与源电极焊接区2连接。另外，插头3a仅仅形成在图1所示的栅电极焊接区3的下方，由于栅电极27是整体连续的一个部件，栅电极焊接区3没有必要与所有的栅电极布线31连接。另外，在SiC衬底20的背面上设置与SiC衬底成欧姆接触的漏电极焊接区(漏电极)29。而且，在芯片5的上面中，第2层间绝缘膜34中没有被源电极焊接区2或者栅电极焊接区3覆盖的区域和源电极焊接区2及栅电极焊接区3的端部，被由氮化硅膜构成的钝化膜36覆盖。
进而，设置顺序贯通第2层间绝缘膜34、第2层间绝缘膜33、外延层，到达SiC衬底20的某一深度的沟槽Tre，用该沟槽Tre，将半导体模块区划成9个区段1。
使该半导体模块的各区段1导通时，在栅电极27上施加5V左右的电压、将源电极28接地、在漏电极焊接区29上施加600V左右的电压。而且，从源电极28供给的载流子(在本实施方式中是电子)，从源区25、通过沟道区21、流向n-SiC层23、SiC衬底20，到达漏电极焊接区29。
本实施方式的半导体器件(半导体模块)中，一个区段1整体由共同的栅偏置和源-漏电极间的电压而工作，作为单一的DMOS器件发挥功能。而且，本实施方式的各区段1是载流子从SiC的主面侧渡越到背面侧的纵向半导体元件，作为所谓的ACCUFET(Accumulation Mode FET；累加模式FET)发挥功能。
而且，本实施方式的特征在于：对半导体模块中的多个区段(半导体元件)进行是否正常工作的检查，不使用不能正常工作的区段，而且，使使用的区段(特定半导体元件)的个数为一定值。但是，也可以将所有正常工作的区段都作为特定半导体元件使用，由此构成半导体器件。在图1所示的实例中，作为特定半导体元件的区段限定为7个，不使用不能正常工作的区段1′和即使能够正常工作但成为多余的区段1″。因此，如图1所示，对各区段1、1′、1″，虽然共同的漏电极焊接区29用芯片焊接连接在漏电极端子42上，但仅仅对7个正常工作的区段1进行引线焊接，对区段1′、1″不进行引线焊接。即仅仅区段1的各源电极焊接区2用0.3mmφ的引线6(铝制)与源电极端子41连接，仅仅区段1的各栅电极焊接区3用0.25mmφ的引线7(铝制)与电极端子43连接。而且，各部件密封在图中虚线所示的密封树脂内，组装在一个管壳内。
但是，如果特定半导体元件以外的半导体元件(本实施方式中的区段1′、1″)的电极焊接区2、3、29中至少一个电极焊接区不与电极端子41、42、43连接，半导体元件(区段)就不工作，能够发挥本发明的效果。
图4(a)、(c)是表示本实施方式的半导体模块制造工序的俯视图。
首先，是图4(a)所示的工序，在2英寸直径的SiC晶片中的多个模块用区域Mod上，形成具有图2及图3所示结构的MISFET单元。在图4(a)中虽然没有表示，在该时刻，模块用区域Mod由沟槽Tre区划成多个区段1(在本实施方式中区划成9个区段)。
其次，是图4(b)所示的工序，用切割法，从SiC晶片切割出包含3×3＝9个区段1的模块用区域Mod作为芯片5。而且，对各芯片5确认各区段1的工作。其结果是确认在9个区段1中包含1个不工作的区段。该工作不良是由于包含在衬底中的微管引起的。
再次，是图4(c)所示的工序，进行将芯片5的漏电极焊接区29焊接在漏电极端子42上的工作，在不能正常工作的区段1′和能够正常工作但成为多余的区段1″上不进行引线焊接，不进行连线地保存下来，仅仅对剩余的7个区段1连线，作为功率器件封装。这时，对各个区段1，将φ0.3mm的引线6(铝制)每个一根地焊接在源电极焊接区2和源电极端子41之间上。另外，使用φ0.25mm的引线7(铝制)，将相同列配置的多个区段1的栅电极焊接区3串联连接，在栅电极焊接区3和栅电极端子43之间进行焊接。
然后，在使源电极端子41、漏电极端子42及栅电极端子43的各端部露出的状态下，将各部件密封在通用的密封树脂(参照图4(c)所示的虚线)内，由此完成作为树脂密封封装的半导体器件(半导体模块)。
本实施方式的半导体模块具有额定电流15(A)，作为耐压600V的功率器件发挥功能，使多个MISFET(区段)并联工作，流通电流，确认电流没有集中在特定的MISFET上，能够稳定地工作。另外，形成在共同的SiC衬底上的多个MISFET中，由于仅仅选择经特性检查能够正常工作的MISFET进行引线焊接，能够得到使用宽禁带宽度半导体，又能够确保高成品率、以低成本制造的半导体模块。
另外，在已焊接了的多个区段中的一个击穿的情况下，当瞬间流通超过30(A)的过剩电流时，φ0.3mm的引线6熔断、作为保险丝部件发挥功能，过剩电流不能继续流通。因此，能够确认本实施方式的半导体模块具有故障自动保险的可靠性。
根据本实施方式，在作为一个树脂密封封装设置的半导体模块(半导体器件)中，多个区段1、1′、1″(半导体元件)中，由于不能正常工作的区段1′不进行引线焊接、不能使用，仅仅使没有微管等晶体缺陷、具有良好电气特性的多个区段1(特定半导体元件)并联工作，能够使半导体模块作为一个功率器件发挥功能。因此，使用宽禁带宽度半导体，能够一面确保高成品率、又以低成本制造控制大电流实现低损耗的半导体模块。
例如，晶片的微管密度是10个/cm2时，在面积100mm2左右的半导体器件(半导体模块)中，几率性地包含10个微管，不能期待它有高的成品率。但是，即使是相同的微管密度，将半导体模块区划成多个小面积的区段，设置能够个别工作的、由100个每个面积1mm2的区段构成的半导体模块，100个中仅仅10个包含微管，剩余的90个能够正常的工作。因此，半导体模块的成品率能够维持在高成品率。
进而，预先将实际使用的区段(特定半导体元件)的个数设定为比90个少的一定的个数(例如85个)，即使用比从经验得知的缺陷的平均密度预测的区段的平均不合格数更少个数的区段，能够进一步谋求成品率的提高。在这种情况下，虽然即使是合格品也不使用的区段从整体上说使成品率降低，在也考虑上述情况的基础上，如果使用经验上使成品率成为最高的个数的区段数即可。
在本实施方式中，表示了用腐蚀法形成的沟槽Tre(元件隔离区)，使各区段具有台式结构，因而能够阻止相互的电气干涉、使个别工作成为可能的结构的情况，但是不是仅限于上述情况，使用由离子注入法形成的p型区构成的保护环等，也可以制作阻止各区段1彼此间电气干涉的结构。
另外，在本实施方式中，各区段1形成在共同的SiC衬底20上，物理学上没有分离，但是也可以在图4(b)所示的工序中，预先将SiC晶片每个区段1地分离，经检查，预先仅仅选择能正常工作的区段1，在图4(c)所示的工序中，将芯片焊接在共同的漏电极端子上。
另外，也能够是用检查每个个别的MISFET单元是否正常工作的方法，代替每个区段检查的方法，用激光等切断不能正常工作的MISFET单元和剩余的源布线(保险丝布线)那样的结构。例如，也能够在形成图2所示的第2层间绝缘膜34之前，从栅布线28、源布线30及漏电极焊接区29施加检查用电压，预先进行各MISFET单元的工作检查，用激光切断不能正常工作的MISFET单元、剩余的MISFET的源布线30。这种情况下，由于不需要将芯片5区划成多个区段，因而不需要形成沟槽Tre。因此，由于不要沟槽Tre，与本实施方式相比，能够使芯片5整体小型化。这种情况下，源布线连接在源电极焊接区上的MISFET单元是特定的半导体元件。
此外，本发明的半导体模块的各区段没有必要是本实施方式那样的、作为ACCUFET的功能的MISFET。例如，也可以是具有国际专利申请PCT/JP01/07810号的图9(a)、(b)和图10所示结构的MISFET。也可以是具有在形成在外延层上的沟槽上埋入栅绝缘膜和栅电极结构的MISFET。
(实施方式2)
图5(a)、(b)依次分别是表示第2实施方式的半导体模块(半导体器件)关键部位的顶面图，以及半导体模块中的肖特基二极管的剖视图。
如图5(a)、(b)所示，本实施方式的半导体模块在SiC衬底上具备3个区段1和3个区段8，3个区段1发挥作为尺寸2mm×2mm(4mm2)的MISFET的功能，3个区段8发挥作为尺寸2mm×2mm(4mm2)的肖特基二极管的功能。在本实施方式中，3个区段1(MISFET)和3个肖特基二极管(区段8)全部是特定半导体元件。发挥作为MISFET功能的区段1具备设置在SiC衬底主面侧上的源电极焊接区2及栅电极焊接区3，和设置在SiC背面侧上的漏电极焊接区(没有图示)。另外，如图5(b)所示，发挥作为肖特基二极管功能的区段8具备：设置在SiC衬底上、包含低浓度n型杂质的外延层；与外延层的上面肖特基接触的肖特基电极37；与SiC衬底20的背面欧姆接触的欧姆电极38。发挥作为MISFET功能的区段1的结构如图2、图3所示。发挥作为MISFET功能的区段1具有电流容量10(A)，1个区段工作时流过的电流用直流换算是10(A)。另外，发挥作为肖特基二极管功能的1个区段8具有电流容量10(A)，1个区段工作时流过的电流用直流换算是10(A)。
而且，在本实施方式中，在1个晶片上仅仅形成多个发挥作为MISFET功能的区段1，在另外的晶片上仅仅形成多个发挥作为肖特基二极管功能的区段8。而且，在晶片的状态下，进行各区段1、8的特性检查后，进行划片，切割成使各个芯片包含1个区段1或者8，如图5所示，用芯片焊接的方法，将3个包含正常工作的区段1的芯片和3个包含正常工作的区段8的芯片搭载在漏电极端子42上。而且，在各区段1中，0.3mmφ的引线(铝制)每个一根地直接焊接在源电极焊接区2和源电极端子41之间上。同样地，在各区段8中，0.3mmφ的引线6(铝制)每个一根地直接焊接在肖特基电极焊接区37和源电极端子41之间上。另外，用0.25φ的引线7(铝制)串联连接同列配置的多个区段1的栅电极焊接区3，进而，用引线7连接端部的区段1的栅电极焊接区3和栅电极端子43之间。进而，在使源电极端子41、漏电极端子42及栅电极端子43的各端部露出的状态下，将各部件密封在通用的密封树脂(参照图5(a)所示的虚线)内，设置作为树脂密封封装的半导体模块。
本实施方式的半导体模块(功率模块)具有额定电流30(A)，发挥作为耐压600V的功率模块的功能。而且，多个MISFET(区段1)及肖特基二极管(区段8)并联工作流过电流，电流不集中在特定的MISFET或者肖特基二极管中，确认能够稳定地工作。另外，多个MISFET及肖特基二极管中，进行特性检查仅仅选择正常工作的芯片，进行芯片焊接，因而，能够使用SiC衬底得到既确保高成品率、又能够以低成本制造的半导体模块。
另外，在已焊接了的多个MISFET(区段1)及肖特基二极管(区段8)中有一个击穿的情况下，瞬间流过超过30(A)的过电流，由于0.3mmφ的引线熔断发挥作为保险丝的功能，过电流不能持续流过。因此，能够确认本实施方式的半导体模块具有故障自动保险的可靠性。
在本实施方式中，表示了由包含MISFET的3个芯片和包含肖特基二极管的3个芯片构成的半导体模块，但是元件数没有限定，可以根据额定电流适当设定元件数。
另外，在第1实施方式及第2实施方式中，多个区段1或者8和各电极端子41、42、43最好使用当流过的电流超过一定值时就熔断的材料构成的连接部件(引线等)进行连接。这种情况下，即使多个区段1或者8中的一个因绝缘击穿成为短路状态，由于电流超过一定值时，连接短路状态的区段和电极端子的连接部件就熔断，电流被切断，该连接部件起到作为保险丝的功能，短路状态的区段成为开路状态，流过的电路为零。因此，由于流过半导体模块的过电流被抑制，因而能够防止过电流流过用半导体模块控制的仪器主体。因此，不会因过电流对仪器主体带来坏的影响，满足故障自动保险的要求，能够提供可靠性优秀的半导体模块。例如，在需要控制数十(A)以上的大电流、使用在驱动电气汽车(HEV)的电动机的倒相器中的半导体模块中，这种半导体模块是十分有效的。
流过的电流超过一定值就熔断的材料可以举出金属、导电性高分子膜等，其中，特别希望是金属。能够使用的金属可以举出Mg、Al、Au、Ag、Cu、Pb、Sn等。
这里，在一个半导体器件中，也可以是各区段1、8不被切断，在共同的SiC衬底20上，以相互电气不干涉的元件隔离状态进行连接。这样做时，与第1实施方式同样，各区段1、8中虽然存在不被使用的区段，但具有能够简化将各区段1、8芯片焊接在一个漏电极端子42上的工序的优点。
(实施方式3)
图6是表示第3实施方式的半导体模块(半导体器件)关键部位的顶面图。
如图6所示，本实施方式的半导体模块在SiC衬底上具备3个区段1和3个区段8，区段1发挥作为尺寸为2mm×2mm(4mm2)的MISFET的功能，区段8发挥作为尺寸为2mm×2mm(4mm2)的肖特基二极管的功能。作为MISFET功能的区段1具备：设置在SiC衬底主面侧上的源电极焊接区2及栅电极焊接区3，和设置在SiC衬底背面侧上的漏电极焊接区(没有图示)。另外，作为肖特基二极管功能的区段8具备：与外延层的上面肖特基接触的肖特基电极焊接区37、和与SiC衬底的背面欧姆接触的欧姆电极38。作为MISFET功能的区段1的结构如图2、图3所示。作为肖特基二极管功能的区段8的结构如第2实施方式中的图5(b)所示。作为MISFET功能的一个区段1和作为肖特基二极管功能的一个区段8的各电流容量和每一个区段工作时流过的电流与第2实施方式相同。
本实施方式的半导体模块与第2实施方式的不同点在于，不是引线焊接而是使用球焊。在作为MISFET功能的各区段1的源电极焊接区2和源电极端子41上，设置0.3mmφ的球9(铝制)，在这些球9上按压金属板10，用超声波焊接法进行焊接。同样，在作为肖特基二极管功能的各区段8的肖特基电极焊接区37和源电极端子41上，设置0.3mmφ的球9(铝制)，将金属板10按压在这些球9上，用超声波焊接法进行焊接。另外，在各区段1的栅电极焊接区3和栅电极端子43上，设置φ0.25mm的球11(铝制)，将金属板按压在这些球11上，用超声波焊接法进行焊接。然后，将各部件密封在密封树脂(参照图6所示的虚线)内，组装在一个封装中。
本实施方式的半导体模块具有额定电流30(A)，作为耐压600V的功率模块发挥功能，使多个MISFET及肖特基二极管并联工作地流过电流。这时，能够确认电流不是集中在特定的MISFET(区段1)及肖特基二极管(区段8)上，能够稳定地进行工作。
另外，与实施方式2同样，形成在各晶片上的多个MISFET(区段1)及肖特基二极管(区段2)中，由于进行特性检查、仅仅选择包含正常工作的元件的芯片进行芯片焊接，使用SiC衬底，能够得到既确保高成品率、又能够以低成本制造的半导体模块。
另外，在已经焊接了的多个MISFET(区段1)及肖特基二极管(区段2)中有一个被击穿的情况下，瞬间流过超过30(A)的过电流，由于0.3mmφ的球9熔断发挥作为保险丝的功能，过电流不持续流过。因此，能够确认本实施方式的半导体模块具有故障自动保险的可靠性。
流过的电流超过一定值时就熔断的材料，可以举出金属、导电性高分子膜等，其中，最好是金属。能够使用的金属可以举出Mg、Al、Au、Ag、Cu、Pb、Sn等。
此外，在本实施方式中，是由作为MISFET功能的3个区段1和作为肖特基二极管功能的3个区段8构成半导体模块的，但是半导体模块(半导体器件)中的区段数没有限定，能够根据额定电流适当设定区段数。
(实施方式4)
图7是表示第4实施方式的半导体模块(半导体器件)中相邻接的区段的一部分结构的剖视图。本实施方式中的平面结构基本上与图1相同。
如图2所示，本实施方式的半导体模块具有与图2所示的第1实施方式的半导体模块同样结构的区段1。
本实施方式的半导体模块的特征在于：与第1实施方式不同，元件隔离区不是沟槽，而是由肖特基二极管构成的。即，在本实施方式中，相邻接的区段1彼此间的元件隔离是由在相邻接的区段1彼此之间上形成作为肖特基二极管45功能的区域进行的，以此代替用腐蚀法形成台式结构。
具体地说，在SiC衬底20的主面侧中，从区段1(MIDFET)隔开10μm，沿各区段1的边界部蒸发宽度为100μm的Ni膜，设置与外延层肖特基接触的肖特基电极40。即配置该肖特基电极40使之包围各区段1(MISFET)，由肖特基二极管45使相邻接的区段1彼此之间电隔离。另外，在外延层内位于肖特基电极40两端部下方的区域上，设置包含p型杂质的绝缘用扩散层42。
这里，即使在本实施方式中，也与第1实施方式同样，各区段1是由并列配置数百个以上数微米到数十微米四角形左右大小的MISFET单元构成，数百个以上的MISFET单元的源电极28，通过源布线30、各插头30a、2a及源布线30，连接在源电极焊接区2上，数百个以上的MISFET单元的栅电极27，通过各插头31a、3a及栅布线31与栅电极焊接区3连接。
而且，在第1层间绝缘膜33的上面上设置栅布线41，栅布线41通过插头41a与肖特基电极40连接，与此同时，通过插头2a与源电极焊接区2连接。即肖特基电极40与区段1(MISFET)的内部源电极28电连接。
本实施方式的半导体模块基本上具有与第1实施方式同样的效果。而且，在作为MISFET功能的区段1的内部中，由于肖特基电极40与源电极28电连接，区段1(MISFET)与肖特基二极管45在半导体模块中成为并联连接，因而，作为倒相器模块能够实现小型化、低成本化。特别是，最好进一步在肖特基电极40的边缘部下方上形成绝缘用扩散层42，就能够设定更高的绝缘耐压。
而且，根据下述理由，具备设置在共同的衬底(SiC衬底20)上的多个区段1(MISFET)，在多个区段1中的一部分的区段1′、1″(特定半导体元件以外的半导体元件)没有与电极端子41、43电连接的情况下(参照图1)，最好设置作为作为肖特基二极管发挥功能的区域，以作为使各区段1、1′、1″彼此间电隔离的元件隔离区。
这样做时，由于在作为肖特基二极管功能的区域上，施加逆向偏置电压，耗尽层扩展，该区域作为多个区段1(MISFET)彼此之间的元件隔离保护环发挥功能。进而，能够实现能够高速工作的肖特基二极管45与MISFET(区段1)在芯片上并联封装的半导体模块。因此，作为元件隔离区，仅仅具有确保MISFET(区段1)的耐压功能的区域，丝毫不损坏作为元件隔离区的功能，进而，也能够作为高度工作的肖特基二极管的功能。
由此，根据本实施方式的半导体模块，与由第1实施方式中的腐蚀形成的台式结构相比，能够由使用简单工艺的单纯结构形成元件隔离区。
另外，现在，例如在倒相器等中使用的Si半导体模块，由6个IGBT和MISFET等功率开关元件与二极管并联连接的单元构成，使各自的定时一致、进行开关，使电动机有效地旋转。这种情况下，由于需要二极管地高速工作，使用了称为快速恢复二极管的高速二极管。这种情况下，由于功率开关元件需要的半导体层的特性和快速恢复二极管需要的半导体层的特性，在寿命等方面差别很大，实现使功率开关元件和二极管单片化的小型模块困难，因而由封装不同的芯片构成模块。
与此相反，根据本实施方式的半导体模块，作为开关元件功能的多个MISFET(区段1)和作为高速二极管功能的肖特基二极管45在芯片上一体化，能够实现小型化、低成本化。
在本实施方式的半导体模块中，就在区段的电极焊接区和电极端子的连线上使用引线焊接的情况作了说明，和第3实施方式同样，也可以使用用金属球和金属棒的球焊。
这里，就上述各实施方式中的区段个数的适当数值，说明如下。
设使相互电学不干涉地元件隔离，电学地能够个别的工作的区段(半导体元件)的面积为Cmm2，在衬底中包含的缺陷密度为n个/cm2，成品率，即在区段(半导体元件)中不包含缺陷的比例，由下式(1)表示：
(100/C-n)/(100/C)＝1-n·C/100         (1)
即，每1cm2形成(100/C)个区段(半导体元件)，其中的n个是包含缺陷的几率，成为不合格品。考虑到今后由宽禁带宽度半导体构成的晶片衬底质量的提高，在实现缺陷密度1个/cm2左右的情况下，为确保50％以上的成品率，由上式(1)可知，最好使各个区段的面积在50mm2以下。同样地，当缺陷密度是5个/cm2左右的情况下，半导体元件的面积最好是10mm2以下，在缺陷密度是10个/cm2左右的情况下，半导体元件的面积最好是5mm2以下。
另外，当区段的面积小于0.1mm2时，由于实施电极焊接区和电极端子之间电连接的引线焊接困难，区段的面积最好是0.1mm2以上。进而，当区段的面积是0.4mm2以上时，能够使用0.3mmφ以上粗细的引线焊接，由于能够流过更大的电流，最好使用这样的区段面积。
进而，一个半导体模块中的区段的数目，也要考虑作为元件隔离区的沟槽的面积和肖特基二极管的面积，能够尽可能决定最适当的区段数目。
另外，在半导体模块中的各区段(半导体元件)中，正常工作时流过的电流在直流换算下最好是100(A)以下，这样做时，作为电连接各区段的电极焊接区和电极端子的连接部件，使用1mmφ的焊接引线和球等，焊接引线和球等不熔融，能够使半导体模块稳定地工作。
另外，因区段的绝缘击穿流过超过100(A)电流的情况下，由于连接部件熔断，发挥作为已经说明过的保险丝的功能。进而，在各区段中，当正常工作时流过的电流在直流换算下是30(A)以下时，由于能够使用0.3mmφ的焊接引线和球，从能够使半导体模块小型化这点考虑是最希望的。在流过区段的电流是脉冲状的情况下，正常工作时流过的电流最好保持在直流换算下100(A)以下，最好100(A)以上的电流不连续流过1秒以上。
此外，在本说明书中，「宽禁带宽度半导体」意味着是导带的下端和价带的上端的能量差，即禁带宽度是2.0eV以上的半导体，那样宽禁带宽度的半导体能够举出SiC、GaN和AlN等III族氮化物、金刚石等。在这些材料中，综合性地考虑电学特性和产品化的进展状况，现在，宽禁带宽度半导体最好的是SiC。
在本发明的半导体模块中，作为区段(半导体元件)没有特别的限制，能够使用已熟知的半导体元件，例如，可以举出肖特基二极管、pn结二极管、MISFET、MESFET、J-FET、晶闸管等。
另外，作为封装也没有特别的限制，能够使用熟知的封装，例如，可以举出树脂密封封装、陶瓷封装、金属封装、玻璃封装等。
在现有的、使用主要由Si构成的半导体元件的半导体模块中，由于Si晶片几乎是无缺陷的，通常是由具有大面积的元件形成大电流的半导体元件。另外，在像Si-IGBT那样的低损耗功率元件中，为使p/n结电气传导，元件电阻Ron的温度系数是负值，在并联使用的情况下引起电流集中，因而将特定的元件击穿。因此，在现有的半导体模块中，像本发明的半导体模块那样，使多个小面积的半导体元件并联工作，由此流过大电流的方法没有被考虑过。
与此相反，根据本发明的半导体器件(半导体模块)，例如，即使在MISFET、JFET等单极元件中，也能够实现耐高压、而且充分小的导通阻抗，即使不施加特别的控制，纵向半导体元件(区段)的并联连接也是可能的。
(产业上的应用领域)
本发明的半导体器件能够应用于由碳化硅(SiC)、GaN、金刚石等宽禁带宽度半导体构成的半导体元件中，例如，搭载在电子仪器上的MOSFET、ACCUFET、JFET等器件，特别是应用于功率器件中。

Claims (13)

1、一种半导体器件，其特征在于：
具备：由宽禁带宽度半导体构成的有源区；具有至少2个施加工作用电压的电极焊接区、能够相互独立地工作的多个半导体元件；
多个电极端子；
用于电连接上述多个半导体元件中至少一部分的特定的多个半导体元件的各电极焊接区和上述多个电极端子的多个连接部件，
上述特定的多个半导体元件相互并联工作。
2、根据权利要求1所述的半导体器件，其特征在于：
上述多个连接部件由在流过超过一定值的电流时就熔断的材料构成。
3、根据权利要求2所述的半导体器件，其特征在于：
上述多个连接部件由金属构成。
4、根据权利要求1～3中任一权利要求所述的半导体器件，其特征在于：
上述多个半导体元件形成在共同的衬底上，
上述多个半导体元件中上述特定半导体元件以外的半导体元件的至少一个电极焊接区，不与上述多个电极端子的任何一个电连接。
5、根据权利要求4所述的半导体器件，其特征在于：
上述多个半导体元件中，上述特定半导体元件以外的半导体元件，包含经检查确认工作不良的半导体元件。
6、根据权利要求5所述的半导体器件，其特征在于：
上述多个半导体元件中，上述特定半导体元件以外的半导体元件，包含经检查确认工作良好的半导体元件，上述特定的半导体元件的个数规定为一定值。
7、根据权利要求4所述的半导体器件，其特征在于：
具备用于电隔离上述多个半导体元件彼此之间的、作为肖特基二极管功能的元件隔离区。
8、根据权利要求1～7中任一权利要求所述的半导体器件，其特征在于：
上述各半导体元件的面积在0.1mm2～50mm2的范围内。
9、根据权利要求1～8中任一权利要求所述的半导体器件，其特征在于：
上述半导体元件是MISFET或者肖特基二极管中的至少一方的元件。
10、根据权利要求1～9中任一权利要求所述的半导体器件，其特征在于：
上述宽禁带宽度半导体是碳化硅。
11、一种半导体器件制造方法，其特征在于：包含下述工序：
形成具有由宽禁带宽度半导体构成的有源区和施加工作用电压的至少2个电极焊接区，能够相互独立地工作的多个半导体元件的工序(a)；
判定上述多个半导体元件的工作良否的工序(b)；
在上述工序(b)中，使确认为工作良好的特定的多个半导体元件的各电极焊接区分别与电极端子连接的工序(c)；
在上述工序(c)后，至少将上述多个特定的半导体元件封装在一个封装中的工序(d)。
12、根据权利要求11所述的半导体器件制造方法，其特征在于：
在上述工序(a)中，将上述多个半导体元件形成在共同的衬底上；
在上述工序(c)中，使上述多个半导体元件中上述特定半导体元件以外的半导体元件的至少一个电极焊接区不与上述多个电极端子的任何一个电连接；
在上述工序(d)中，将上述多个半导体元件的所有元件组装进一个封装中。
13、根据权利要求11所述的半导体器件制造方法，其特征在于：
在上述工序(a)中，形成上述多个半导体元件，使之在物理学上相互隔离；
在上述工序(d)中，仅仅将上述多个半导体元件中确认为工作良好的半导体元件组装进一个封装中。
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