CN103117309A - 一种横向功率器件结构及其制备方法 - Google Patents

一种横向功率器件结构及其制备方法 Download PDF

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CN103117309A
CN103117309A CN2013100579433A CN201310057943A CN103117309A CN 103117309 A CN103117309 A CN 103117309A CN 2013100579433 A CN2013100579433 A CN 2013100579433A CN 201310057943 A CN201310057943 A CN 201310057943A CN 103117309 A CN103117309 A CN 103117309A
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semiconductor regions
groove
lateral power
preparation
groove structure
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郭宇锋
徐琴
黄示
徐光明
张长春
夏晓娟
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Nanjing Post and Telecommunication University
Nanjing University of Posts and Telecommunications
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Abstract

本发明提出了一种横向功率器件结构及其制备方法，所述结构不仅可以有效缩小器件尺寸，提高器件的集成度，同时也可优化漂移区浓度，提高击穿电压。而且由于器件尺寸的缩小以及漂移区浓度优化值的提高，其导通电阻也能显著减小，从而整体提高了器件的击穿电压与导通电阻的比值。此外，该结构的漂移区可由浅沟槽隔离技术直接制作而成，将源区、沟道或漏区制作于浅沟槽隔离工艺形成的沟槽中，工艺简单，且其工艺与标准CMOS工艺完全兼容，也降低了器件的制造成本。

Description

一种横向功率器件结构及其制备方法
技术领域
本发明属于半导体功率器件和半导体工艺技术领域，尤其涉及一种横向功率器件结构及其制备方法，如横向扩散场效应晶体管LDMOS、横向高压二极管、横向绝缘栅双极型晶体管LIGBT等。
背景技术
功率器件是现代电力电子***的核心，它对提高***的各项技术指标和性能起着至关重要的作用。理想的功率器件，应当具有下列理想的静态和动态特性：在截止状态时能承受高电压；在导通状态时具有大电流和很低的压降；在开关转换时具有短的开、关时间。
功率半导体器件按工作方式可分为两类:一类是传统的双极型器件，它是电流控制型器件，包括晶闸管（SCR）、功率双极型晶体管（GTR）等；另一类是新型的电压控制型器件，包括金属-氧化物-半导体场效应晶体管（MOSFET）、绝缘栅双极型晶体管（IGBT）和MOS控制晶闸管（MCT）等。功率MOS晶体管与功率双极型晶体管有相似的输出伏安特性，但功率MOS晶体管没有少子存贮效应的影响，因而工作频率比双极型晶体管的高；而且功率MOS晶体管是电压控制器件，其驱动电流非常小，故其驱动电路也比双极型器件简单得多。并且功率MOS管具有负的电流温度系数，它不存在功率双极型晶体管的二次击穿现象，其安全工作区也比功率双极型晶体管宽。正是因为功率MOS器件具有胜过功率双极型器件的一系列优点，以MOSFET为主的压控型功率器件得到了快速发展，在电力电子装置中获得了广泛的应用。
MOS功率晶体管可以分成两种基本类型：垂直导电的功率MOS和横向高压功率MOS。H.W.Collins等人在1979年发表的文章“Power MOSFET technology”（Proceedings of International Electron Devices Meeting,pp.79-85）中提出了垂直双扩散功率MOS（Vertical Double Diffused Metal Oxide Semiconductor Field EffectTransistor，VDMOS），其结构图1所示，结构底部为具有高掺杂浓度的n型半导体区域103，结构顶部包括一个具有高掺杂浓度的n型半导体区域104和p型半导体区域101，半导体区域101和半导体区域103二者之间通过一个具有低掺杂浓度的n型半导体区域102隔开，这里，半导体区域104构成VDMOS的源区，半导体区域103构成VDMOS的漏区，半导体区域101构成VDMOS的沟道区，半导体区域102构成VDMOS的漂移区。采用该种垂直结构，可减小器件尺寸，降低器件的导通电阻。
虽然VDMOS器件的工艺简单，但由于其采用垂直结构，难以应用于硅的平面集成工艺中，James Victory等人在1997年9月发表的文章“A3D,PhysicallyBased Compact Model for IC VDMOS Transistors”（Proc.21st InternationalConference on Microelecs,vol.1,pp.14-17）中提出了适用于IC集成工艺的VDMOS结构，如图2所示。它主要由p型半导体衬底区域100、p型半导体区域101、重掺杂的p型半导体区域105、轻掺杂n型半导体区域102、重掺杂n型的半导体区域103、104等组成。这种结构与VDMOS结构的主要区别在于在底部n+埋氧层上连接了一个深沟槽n+区，以提供表面漏极接触，将漏极从器件底部转移到了器件表面。但是这种IC VDMOS结构的深沟槽n+区在实际工艺中难以精确制作，增加了工艺的复杂和成本，同时容易影响器件的性能。
和VDMOS器件不同，横向扩散场效应晶体管（Lateral Double DiffusedMetal Oxide Semiconductor Field Effect Transistor，LDMOS）是一种和集成电路工艺完全兼容的器件结构，如图3所示。该结构包括一个具有高掺杂浓度的n型半导体区域103、104以及p型半导体区域101，半导体区域101和半导体区域103二者之间通过一个具有低掺杂浓度的n型半导体区域102隔开，这里，半导体区域104构成VDMOS的源区，半导体区域103构成VDMOS的漏区，半导体区域101构成VDMOS的沟道区，半导体区域102构成VDMOS的漂移区。LDMOS结构通过横向双扩散技术形成导电沟道区，很好地解决了提高耐压与增大电流之间的矛盾，是目前十分常用的一类功率器件。
LDMOS虽然更容易集成，但是和VDMOS相比，其缺点是芯片面积大、导通电阻大。本发明提供一种新型的横向功率器件，它不但和CMOS工艺完全兼容，而且像VDMOS一样采用垂直漂移区，因此同时具有芯片面积小、导通电阻低的优点。
发明内容
本发明针对上述背景技术中存在的技术问题，提出一种横向功率器件结构及其制备方法。
本发明为解决上述技术问题，采用如下技术方案：
一种横向功率器件结构，所述结构包括衬底区域，在衬底区域上具有一个沟槽结构，所述沟槽结构具有一个p型半导体区域和一个高掺杂浓度的n型半导体区域、以及间隔p型半导体区域和n型半导体区域的一个低掺杂浓度的n型半导体区域；当在该沟槽结构底部配置p型半导体区域时，则在该沟槽结构顶部配置高掺杂浓度的n型半导体区域；当在该沟槽结构底部配置高掺杂浓度的n型半导体区域时，则在该沟槽结构顶部配置一个p型半导体区域。
所述低掺杂浓度的n型半导体区域作为漂移区，其浓度分布是均匀的、或者是横向变掺杂的、或者是纵向变掺杂、或者是横向和纵向均为变掺杂。
所述沟槽壁是垂直面、或者是倾斜面、或者是阶梯面。
所述衬底区域是半导体材料、或者是二氧化硅氧化层SOI。
所述的横向功率器件的具体形式是横向扩散场效应晶体管LDMOS、或者是横向PN二极管、或者是横向绝缘栅双极型晶体管LIGBT、或者是横向晶闸管。
一种横向功率器件结构的制备方法，采用浅沟槽隔离技术与CMOS工艺相结合的制备方法，该制备方法包括以下步骤：
步骤A，在p型衬底材料上，采用浅沟槽隔离技术制作氧化硅沟槽；
步骤B，涂胶、光刻，去除用于制造垂直漂移区沟槽中的氧化硅，制备出沟槽结构；
步骤C，采用标准CMOS工艺制作器件其余部分。
所述一种横向功率器件结构的制备方法，所述步骤A中，具体包含以下工艺步骤：
步骤A-1，在P型硅衬底，进行氧化硅隔离层生长，并淀积氮化硅；
步骤A-2，光刻掩膜，在氧化硅和氮化硅层上刻蚀窗口，接着在窗口处腐蚀出指定深度的沟槽；
步骤A-3，侧墙氧化，在沟槽内部生长出一层氧化硅膜，接着采用化学气相沉积法（CVD）在沟槽中淀积二氧化硅；
步骤A-4，通过化学机械抛光法（CMP）平坦化，去除器件表面的氮化硅和氧化硅。
所述一种横向功率器件结构的制备方法，所述步骤C中，具体包含以下工艺步骤：
步骤C-1，在硅衬底的器件有源区域进行n型离子注入，形成比衬底浓度高的中等浓度n型掺杂区，并进行高温扩散推进；
步骤C-2，利用光刻掩膜和硼离子注入，制备p阱，并进行高温推结；
步骤C-3，热生长栅氧，淀积多晶硅，涂胶光刻，形成多晶硅栅；
步骤C-4，多晶硅栅形成后，加掩膜版在源漏区进行涂胶光刻，然后进行n型源漏区的砷离子注入，形成源漏区；
步骤C-5，涂胶光刻出P型源区，硼离子注入，形成p型体接触；
步骤C-6，淀积场氧，涂胶然后显影、刻蚀，露出接触孔区域，形成欧姆接触；
步骤C-7，溅射硅铝，光刻并湿法刻蚀硅铝，形成金属电极，接着光刻形成PAD接触，然后再进行合金和钝化合金，形成最终的器件结构。
所述一种横向功率器件结构的制备方法，采用湿法刻蚀或者反应离子刻蚀方法在p型衬底材料上制作沟槽结构。
有益效果：本发明提出的一种横向功率器件结构及其制备方法，采用该结构不仅可以有效缩小器件尺寸，提高器件的集成度，同时也可优化漂移区浓度，提高击穿电压。而且由于器件尺寸的缩小以及漂移区浓度优化值的提高，其导通电阻也能显著减小，从而整体提高了器件的击穿电压与导通电阻的比值。此外，该结构的漂移区可由浅沟槽隔离技术直接制作而成，将源区、沟道或漏区制作于浅沟槽隔离工艺形成的沟槽中，工艺简单，且其工艺与标准CMOS工艺完全兼容，也降低了器件的制造成本。
附图说明
图1是VDMOS结构示意图。
图2是适用于集成电路的VDMOS结构示意图。
图3是LDMOS结构示意图。
图4是本发明提供的具有垂直漂移区的LDMOS器件结构示意图。
图5是本发明提供的采用浅沟槽隔离工艺和传统CMOS工艺相结合制造的器件结构示意图。
图6是本发明的具有垂直漂移区的LDMOS结构的一种形式。
图7是本发明的具有垂直漂移区PN二极管结构示意图。
图8是本发明的具有垂直漂移区LTGBT结构示意图。
图9是具有相同结构参数的常规LDMOS、具有垂直漂移区结构的LDMOS的等势线分布示意图。其中图9a对应于常规LDMOS结构，图9b对应于具有垂直漂移区的LDMOS结构。
图10是具有相同结构参数的常规LDMOS与垂直漂移区LDMOS结构的击穿电压、导通电阻对比图。
具体实施方式
下面将参照附图更详细地描述本发明一种横向功率器件结构及其制备方法。
本发明提供了一种使用浅沟槽隔离技术制备的具有漂移区结构的横向功率器件。图5是该结构的示意图，通过浅沟槽隔离技术在p型衬底区域100上制作得到了沟槽结构，在沟槽底部形成p型半导体区域101和高掺杂浓度的n型半导体区域104，在沟槽顶部形成高掺杂浓度的n型半导体区域103，半导体区域101和103通过沟槽侧壁低掺杂浓度的n型半导体区域102相连，半导体区域101为沟道区，半导体区域103、104分别为漏区和源区，半导体区域102为LDMOS的垂直漂移区。
需要说明的是：
（1）所述的具有低掺杂浓度的n型的半导体区域102的浓度分布既可以是均匀的，也可以是非均匀的；
（2）所述的衬底区域100可以是轻掺杂的半导体（体硅），也可以是二氧化硅氧化层（SOI）；
（3）所述的垂直漂移区结构还可以用于横向PN二极管（如图8）、LIGBT（如图9）、横向晶闸管等功率器件，以同时改善器件的击穿特性和导通特性。
本发明的工作原理：
图9和图10分别是根据初步仿真结果得到的常规LDMOS结构与具有垂直漂移区LDMOS结构的等势线分布对比图及击穿电压对比图。这两种结构的结构参数相同，而对其漂移区浓度分布进行了优化。从图9a可以看出，对于常规结构，在漂移区两端的表面等线较为密集，从而导致两端出现电场峰值，降低了击穿电压。而对于比图9b中的垂直漂移区结构，其漂移区等势线分布较为均匀，表面电场接近常数，从而提高了击穿电压。从图10a可以看出垂直漂移区结构较常规结构，其击穿电压有所提高，且漂移区浓度优值也更高。并且从图10a中直观反映出由于本发明的LDMOS漂移区采用浅沟槽隔离工艺制作垂直漂移区结构后，漂移区浓度优化值大幅提高，而且器件的长度相对于常规结构得到大幅减小。从图10b可见，该结构的导通电阻比之常规结构也达到了大幅减小的效果，说明了本发明提供的垂直漂移区结构使其击穿电压和导通电阻达到了良好的折中效果。
根据本发明提供的使用浅沟槽隔离技术制备的垂直漂移区结构，可以制作出特性优良的横向功率器件，举例如下：
1）具有垂直漂移区的LDMOS结构，如图4、图6。图4是本发明提供的具有垂直漂移区的LDMOS器件结构示意图，该结构在p型半导体衬底区域100上有一沟槽结构：位于沟槽底部的p型半导体区域101构成LDMOS的沟道区，p型半导体区域101上具有高掺杂浓度的n型半导体区域104构成LDMOS的源区，位于沟槽顶部的高掺杂浓度的n型半导体区域103构成LDMOS的漏区，沟道区101和漏区103之间通过侧壁区低掺杂浓度的具有低掺杂浓度的n型的半导体区域102相连接，半导体区域102即为LDMOS的漂移区。图6是本发明的具有垂直漂移区的LDMOS结构的一种形式，该结构在p型半导体衬底100上有一沟槽结构：沟槽顶部包括p型半导体区域101，一个高掺杂浓度的p型半导体区域105，高掺杂浓度n型的半导体区域104一侧连接半导体区域101，另一侧连接半导体区域105；沟槽底部为高掺杂浓度的n型半导体区域103；侧壁区为具有低掺杂浓度的n型半导体区域102，连接半导体区域101和半导体区域103。这里，半导体区域102构成LDMOS的漂移区，半导体区域101构成LDMOS的沟道区，半导体区域104构成LDMOS的源区，半导体区域103构成LDMOS的漏区。
半导体区域102用做垂直漂移区，其浓度分布式是均匀的，或者是横向变掺杂或纵向变掺杂，或是横向和纵向均为变掺杂。
2）具有垂直漂移区的PN二极管结构，如图7所示。它包括半导体衬底100，在衬底上包含一个沟槽结构，在沟槽底部具有一个p型半导体区域101作为阳极区，在沟槽顶部具有一个高掺杂浓度n型的半导体区域103作为阴极区，两者之间通过沟槽侧壁区一个具有低掺杂浓度的n型半导体区域102隔开。半导体区域102即为PN二极管的垂直漂移区，其浓度分布是均匀的，或者是横向变掺杂或纵向变掺杂，或是横向和纵向均为变掺杂。
3）具有垂直漂移区的绝缘栅双极型功率晶体管，简称LIGBT，如图8所示。它包括一个p型衬底区域100，在衬底上方具有一个沟槽结构。在沟槽底部包含一个p型半导体区域101、一个高掺杂浓度的n型半导体区域104、一个高掺杂浓度的p型半导体区域105，在沟槽顶部包含一个高掺杂浓度n型的半导体区域103以及一个高掺杂浓度p型的半导体区域106，半导体区域101和半导体区域103通过沟槽侧壁区一个具有低掺杂浓度的n型半导体区域102隔离。其中半导体区域101构成沟道区，一侧与半导体区域104相连，另一侧与半导体区域102相连，其中104构成器件的阴极区，102构成器件的漂移区。半导体区域103的一侧与半导体区域102相连，另一侧与半导体区域106相连，半导体区域106构成器件的阳极区，半导体区域105用作体接触。半导体区域102的浓度分布是均匀的，或者是横向变掺杂或纵向变掺杂，或是横向和纵向均为变掺杂。
需要说明的是，本发明提出的一种横向功率器件结构除了可以应用于上述所列几类横向功率器件外，还可用于横向晶闸管、静电诱导晶体管（SIT）等其他未列的横向功率器件。

Claims (9)

1.一种横向功率器件结构，其特征在于，所述结构包括衬底区域（100），在衬底区域上具有一个沟槽结构，所述沟槽结构具有一个p型半导体区域（101）和一个高掺杂浓度的n型半导体区域（103）、以及间隔p型半导体区域（101）和n型半导体区域（103）的一个低掺杂浓度的n型半导体区域（102）；当在该沟槽结构底部配置p型半导体区域（101）时，则在该沟槽结构侧壁顶部配置高掺杂浓度的n型半导体区域（103）；当在该沟槽结构底部配置高掺杂浓度的n型半导体区域（103）时，则在该沟槽结构侧壁顶部配置一个p型半导体区域（101）。
2.根据权利要求1所述的一种横向功率器件结构，其特征在于，所述低掺杂浓度的n型半导体区域（102）作为漂移区，其浓度分布是均匀的、或者是横向变掺杂的、或者是纵向变掺杂、或者是横向和纵向均为变掺杂。
3.根据权利要求1所述的一种横向功率器件结构，其特征在于，所述沟槽结构测壁是垂直面、或者是倾斜面、或者是阶梯面。
4.根据权利要求1或2或3所述的一种横向功率器件结构，其特征在于，衬底区域（100）是半导体材料、或者是二氧化硅氧化层。
5.根据权利要求1所述的一种横向功率器件结构，其特征在于，所述横向功率器件的具体形式是横向扩散场效应晶体管LDMOS、或者是横向PN二极管、或者是横向绝缘栅双极型晶体管LIGBT、或者是横向晶闸管。
6.一种基于权利要求1所述的横向功率器件结构的制备方法，其特征在于，该制备方法包括以下步骤：
步骤A，在 P型硅衬底（100）上，采用浅沟槽隔离STI技术制作氧化硅沟槽结构；
步骤B，涂胶、光刻，去除用于制造沟槽结构的沟槽中的氧化硅，制备出沟槽结构；
步骤C，采用标准CMOS工艺制作器件。
7.根据权利要求6所述的一种横向功率器件结构的制备方法，其特征在于，所述步骤A中，具体包含以下工艺步骤：
步骤A-1，在 P型硅衬底（100）上，进行氧化硅隔离层生长，然后在氧化硅隔离层上淀积氮化硅；
步骤A-2，光刻掩膜，在氧化硅和氮化硅层上刻蚀窗口，接着在窗口处腐蚀出指定深度的沟槽；
步骤A-3，侧墙氧化，在沟槽内部生长出一层氧化硅膜，接着采用化学气相沉积法CVD在沟槽中淀积二氧化硅；
步骤A-4，通过化学机械抛光法CMP平坦化，去除器件表面的氮化硅和氧化硅。
8.根据权利要求6所述的一种横向功率器件结构的制备方法，其特征在于，所述步骤C中，具体包含以下工艺步骤：
步骤C-1，在p型硅衬底（100）上进行n型轻掺杂离子注入，形成比衬底浓度高的中等浓度n型掺杂区（102），并进行高温扩散推进；
步骤C-2，利用光刻掩膜和硼离子注入，制备p阱（101），并进行高温推结；
步骤C-3，热生长栅氧，淀积多晶硅，涂胶光刻，形成多晶硅栅；
步骤C-4，多晶硅栅形成后，加掩膜版在源漏区进行涂胶光刻，然后进行n型重掺杂砷离子注入，形成源区（104）和漏区（103）；
步骤C-5，涂胶光刻出P型源区，进行重掺杂硼离子注入，形成p型体接触区（105）；
步骤C-6，淀积场氧，涂胶然后显影、刻蚀，露出接触孔区域，形成欧姆接触；
步骤C-7，溅射硅铝，光刻并湿法刻蚀硅铝，形成金属电极，完成器件制作。
9. 一种基于权利要求1所述的横向功率器件结构的制备方法，其特征在于，包括如下步骤：
步骤（1），采用湿法刻蚀或者反应离子刻蚀方法在p型衬底（100）上制作沟槽结构；
步骤（2），采用标准CMOS工艺制作器件。
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Application publication date: 20130522