CN102184945A - 一种槽栅型mosfet器件 - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 8
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 4
- 230000001939 inductive effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
本申请公开了一种新型槽栅型MOSFET器件及其制造方法。所述体区与所述半导体衬底之间形成凹形界面,使得所述体区在源极金属接触下方的部分的厚度比所述体区的其他部分更小。所述凹形界面的最凹处E位于源极金属接触下方,使得反向电场聚集在最凹处。在体区中还可以形成位于源极金属接触下方的重掺杂区域以减小其电阻。在MOSFET的关断时产生反向电流从最凹处流经重掺杂区域到达源极金属接触,减小了等效寄生三极管B对MOSFET的关断的影响,并且产生了较小的压降。本发明的槽栅型MOSFE器件有效地控制了寄生三极管的失控,提高了槽栅型MOSFET的UIS性能。
Description
技术领域
本发明涉及一种MOSFET器件,更具体地,涉及一种槽栅型MOSFET器件。
背景技术
槽栅型金属氧化物半导体场效应晶体管(MOSFET)器件由于其高效能、低成本等优点而广泛应用于电源管理领域。当槽栅型MOSFET器件被应用于具有感性负载的电路中时,其非钳位电感性开关(UIS)性能是影响槽栅型MOSFET器件效能的一个重要参数。
如图1所示,当MOSFET M导通时,电感L通过MOSFET M放电。而当MOSFET M关断时,由于电感电流不能突变,则MOSFET M中的寄生二极管A被击穿,电感电流通过寄生二极管A放电。UIS就是指MOSFET输出端外接有一不能被其他电路钳制电位的感性器件时,当MOSFET从导通向外输出能量转化到关断时,感性器件内部存贮的能量需要通过MOSFET体内的二极管释放到接地端的过程。UIS能力的大小通常使用MOSFET能够承受的最大UIS能量表征。
图2示出现有技术中的多个连续N型槽栅型MOSFET器件。如图2所示,以其中一个单独的N型槽栅型MOSFET器件为例,所述槽栅型MOSFET器件包括作为漏极D的N型衬底N-sub以及生长于N型衬底N-sub之上的N型外延层N-epi。在N型外延层N-epi内包括栅介质层GOX,以及位于栅介质层内的多晶硅区域Poly,作为所述槽栅型MOSFET器件的栅极G。所述槽栅型MOSFET器件还包括和栅介质层GOX相邻的P型体区P-body、位于P型体区P-body上的N型重掺杂区作为所述MOSFET器件的源极,以及源极金属接触S。另外,所述槽栅型MOSFET器件还包括一位于源极金属接触S下方的P型重掺杂区域,且所述P型重掺杂区域和所述源极金属接触S相接触。
如图2所示,在N型槽栅型MOSFET器件内,等效寄生二极管A位于N型外延层N-epi和P型体区P-body之间。另外,在该MOSFET器件中还存在等效寄生三极管B,其基极位于P型体区P-body,发射极位于N型重掺杂区,且其集电极位于N型外延层N-epi内。
当在UIS工作条件下发生寄生二极管反向击穿时,对于图2所示现有技术中的N型槽栅型MOSFET器件来说,反向电流由漏极D流向源极S,如图3所示。此时,将在P型体区P-body与N型重掺杂区之间产生一正向压降。由于P型体区为轻掺杂,其电阻较大,因而所述正向压降亦较大,大于等效寄生三极管B的基极发射极导通压降VBEon,从而使寄生三极管B导通,对电流进行放大,导致失控发生。此时,栅极电压将不再能够关断MOSFET器件,使得MOSFET器件永久性损坏。
因此,如何提高槽栅型MOSFET器件的UIS性能已成为当今MOSFET器件研究的一个重大课题。
发明内容
本发明的目的在于提供一种提高了UIS性能的新型槽栅型MOSFET器件。
根据本发明的一方面,提供一种槽栅型MOSFET器件,包括:第一导电类型的半导体衬底;在所述半导体衬底上形成的具有第一导电类型的外延层;在所述外延层内形成的栅介质层;在所述栅介质层内形成的栅极;在所述外延层内形成的体区,所述体区与所述栅介质层相邻,具有第二导电类型;在所述体区上部形成第一导电类型的源极;在所述源极中形成源极金属接触,所述源极金属接触伸入所述体区内;在所述体区内形成位于所述源极金属接触下方的至少一个第二导电类型重掺杂区域,其中,所述第一导电类型与所述第二导电类型相反;其特征在于,所述体区与所述半导体衬底之间形成凹形界面,使得所述体区在源极金属接触下方的部分的厚度比所述体区的其他部分更小。
根据本发明的另一方面,提供一种制造槽栅型MOSFET器件的方法,包括:提供第一导电类型的半导体衬底;在所述半导体衬底上形成第一导电类型的外延层;在所述外延层内形成栅介质层;在所述栅介质层内形成栅极;在所述半导体衬底内形成与栅介质层相邻的体区,所述体区具有第二导电类型;在所述体区的上部形成第一导电类型的源极;形成穿过所述源极并到达所述体区内一定深度的凹槽;在所述体区内形成位于凹槽下方的第二导电类型的重掺杂区域;以及在所述凹槽中填充金属而形成源极金属接触,其特征在于,所述体区与所述半导体衬底之间形成凹形界面,使得所述体区在所述源极金属接触下方的部分的厚度比所述体区的其他部分更小。
根据本发明提出的新型槽栅型MOSFET器件及其制造方法,在MOSFET的关断时产生反向电流从最凹处流经重掺杂区域到达源极金属接触,减小了等效寄生三极管B对MOSFET的关断的影响,并且产生了较小的压降。本发明的槽栅型MOSFE器件有效地控制了寄生三极管的失控,提高中了槽栅型MOSFET的UIS性能。
附图说明
图1示出槽栅型MOSFET器件用于感性负载电路中的电路图。
图2示出图1所示槽栅型MOSFET器件的一种现有技术中的内部结构图。
图3示出图2所示现有技术中的槽栅型MOSFET器件在UIS工作条件下的反向电流流向示意图。
图4示出依据本发明第一实施例的新型槽栅型MOSFET器件的内部结构图。
图5示出依据本发明第二实施例的改进的新型槽栅型MOSFET器件的内部结构图。
图6(a)~6(h)示出制造依据本发明第二实施例的改进的新型槽栅型MOSFET器件的一种方法。
图7示出制造依据本发明第二实施例的改进的新型槽栅型MOSFET器件的另一种方法。
图8示出制造依据本发明第二实施例的改进的新型槽栅型MOSFET器件的另一种方法。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。
下面详细说明本发明实施例的新型槽栅型MOSFET器件。在接下来的说明中,一些具体的细节,例如实施例中的具体掺杂类型,都用于对本发明的实施例提供更好的理解。本技术领域的技术人员可以理解,即使在缺少一些细节或者其他方法、材料等结合的情况下,本发明的实施例也可以被实现。
本发明提出了一种新型槽栅型金属氧化物半导体场效应晶体管(MOSFET)器件。所述槽栅型MOSFET器件的未钳位电感性开关(UIS)性能和现有技术中的槽栅型MOSFET器件相比有极大的提高。
图4示出依据本发明第一实施例的新型槽栅型MOSFET器件的内部结构图。如图4所示,和现有技术中的槽栅型MOSFET器件相比,本发明提出的新型槽栅型MOSFET器件的不同之处在于该P型体区P-body与N型外延层N-epi之间形成凹形界面,使得该P型体区P-body在源极金属接触S下方的部分的厚度比P型体区P-body的其他部分更小。因而,P型体区P-body的最凹处E位于源极金属接触S下方。
如图4所示,当在UIS工作条件下发生寄生二极管A反向击穿时,所述凹形界面使得电场聚集在最凹处E,因此,最凹处E电场最高。从而,大部分反向电流被限制在最凹处E上方的P型重掺杂区域内流过。
由于P型重掺杂区的掺杂浓度大于P型体区其它区域的掺杂浓度,因此,其电阻比P型体区的要小。因此,反向电流由最凹处E经P型重掺杂区流向源极金属接触S,其产生的压降较小,难以达到等效寄生三极管B的基极发射极导通压降VBEon,从而避免了失控的发生。
可见,依据本发明第一实施例的新型槽栅型MOSFET器件的UIS性能得到了提高。
图5示出依据本发明第二实施例的改进的新型槽栅型MOSFET器件的内部结构图。和图4所示新型槽栅型MOSFET器件相比,图5所示改进的新型槽栅型MOSFET器件的不同之处在于,其在P型体区P-body中形成位于源极金属接触S下方的两个或更多个P型重掺杂区域,且所述两个或更多个P型重掺杂区域纵向排列,最顶部的一个P型重掺杂区域和源极金属接触S相接触。
所述多个P型重掺杂区域使得反向电流流经P型重掺杂区域时产生的压降更小,更不易达到等效寄生三极管B的基极发射极导通压降VBEon,从而,更有效地避免了失控的发生,提高了槽栅型MOSFET器件的UIS性能。
图4和图5分别示出了依据本发明第一和第二实施例的新型槽栅型MOSFET器件的内部结构图,其中示出了多个并列设置的新型槽栅型MOSFET器件,相邻的两个新型槽栅型MOSFET器件共用源极金属接触S。由图4和图5可以看出,所述最凹处E位于相邻的两个新型槽栅型MOSFET器件的栅极之间的中心处。然而,本领域的普通技术人员应当理解,上述实施例只是示例性的,所述最凹处E可以位于相邻的两个新型槽栅型MOSFET器件的栅极之间的任何位置,只要设置在源极金属接触的下方即可。优选地,所述最凹处E位于相邻的两个新型槽栅型MOSFET器件的栅极之间的中心处。
图6(a)~6(h)示出制造依据本发明第二实施例的改进的新型槽栅型MOSFET器件的一种方法。其具体步骤如下:
步骤a:在N型衬底N-sub上生长N型外延层N-epi,且在N型外延层N-epi上进行沟槽刻蚀,如图6(a)所示;
步骤b:在所述沟槽中生长栅介质层GOX,并在栅介质层GOX内生长多晶硅区域Poly,如图6(b)所示;
步骤c:在相邻两栅介质层GOX之间的台面上形成光致抗蚀剂PR,然后进行P型离子注入,如图6(c)所示;
步骤d:去除光致抗蚀剂PR,然后进行P型体区的热推进,如图6(d)所示;
步骤e:在P型体区P-body的上部进行N型离子重掺杂,如图6(e)所示;
步骤f:在将要形成源极金属接触的位置,刻蚀出穿过N型离子重掺杂区域并到达P型体区P-body内一定深度的凹槽,如图6(f)所示;
步骤g:通过凹槽,使用不同能量在P型体区P-body内进行多次P型离子重掺杂注入,如图6(g)所示;
步骤h:在凹槽中填充金属而形成源极金属接触S,如图6(h)所不。
在上述步骤c中,光致抗蚀剂PR仅仅遮挡N型外延层N-epi位于相邻的两个新型槽栅型MOSFET器件的栅极之间的中间的一部分区域。因而,在后续热推进d中,P型体区P-body与N型外延层N-epi之间形成凹形界面,使得该P型体区P-body在源极金属接触S下方的部分的厚度比P型体区P-body的其他部分更小。
在另一实施例中,如图7所示,在步骤c中采用较高的能量进行P型体区P-body的P型离子注入,以使得光致抗蚀剂PR不能完全阻止P型离子注入进其下方区域,而是使该区域内P型离子深度小于P型体区P-body内其它区域的P型离子深度。之后,再进行热推进。这样,同样能形成凹形界面,提高槽栅型MOSFET器件的UIS性能。
在另一实施例中,如图8所示,在步骤c中,采用多次对P型体区P-body进行P型离子注入,以使得光致抗蚀剂PR不能完全阻止P型离子注入进其下方区域,而是使该区域内P型离子深度小于P型体区P-body内其它区域的P型离子深度。之后,再进行热推进。这样,同样能形成凹形界面,提高槽栅型MOSFET器件的UIS性能。
图6(a)~6(h)、图7和图8示出制造依据本发明第二实施例的改进的新型槽栅型MOSFET器件的方法。利用所述方法,亦可实现依据本发明第一实施例中新型槽栅型MOSFET器件结构的制造。同样可以利用图6(a)~6(h)的步骤,只是在步骤6(g)中只进行一次P型离子注入。
上述步骤示出了制作本发明提出的新型槽栅型MOSFET器件的方法。然而,本领域的技术人员应当理解,上述步骤只是示例性的,在缺少上述某一步骤或某几个步骤,或更变上述步骤的顺序,或变换上述步骤中的材料或工艺方法,本发明提出的新型槽栅型MOSFET器件也是可以实现的。例如,在步骤c中,亦可采用其它具有掩模功能的物体,如氧化物的硬掩模,代替光致抗蚀剂以阻止所述部分区域的离子注入,以使得该所述区域无离子注入或注入离子的深度小于其它区域注入离子的深度。
在上述实施例中,均以N型槽栅型MOSFET器件为例对新型槽栅型MOSFET器件的结构及其制造方法进行了说明。然而,本领域的普通技术人员应当理解,上述实施例只是示例性的,本发明提出的新型槽栅型MOSFET器件结构和制造方法同样也适用于P型槽栅型MOSFET器件。
上述本发明的说明书和实施方式仅仅以示例性的方式对本发明实施例的槽栅型MOSFET器件及其制作方法进行了说明,并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的,其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。
Claims (10)
1.一种槽栅型MOSFET器件,包括:
第一导电类型的半导体衬底;
在所述半导体衬底上形成的具有第一导电类型的外延层;
在所述外延层内形成的栅介质层;
在所述栅介质层内形成的栅极;
在所述外延层内形成的体区,所述体区与所述栅介质层相邻,具有第二导电类型;
在所述体区上部形成第一导电类型的源极;
在所述源极中形成源极金属接触,所述源极金属接触伸入所述体区内;
在所述体区内形成位于所述源极金属接触下方的至少一个第二导电类型重掺杂区域,其中,所述第一导电类型与所述第二导电类型相反;
其特征在于,所述体区与所述半导体衬底之间形成凹形界面,使得所述体区在源极金属接触下方的部分的厚度比所述体区的其他部分更小。
2.如权利要求1所述的槽栅型MOSFET器件,其特征在于,所述至少一个第二导电类型重掺杂区域包括纵向排列的两个或更多个第二导电类型重掺杂区域。
3.如权利要求1所述的槽栅型MOSFET器件,其特征在于,所述至少一个第二导电类型重掺杂区域中的最顶部的一个和所述源极金属接触相接触。
4.一种制造槽栅型MOSFET器件的方法,包括:
提供第一导电类型的半导体衬底;
在所述半导体衬底上形成第一导电类型的外延层;
在所述外延层内形成栅介质层;
在所述栅介质层内形成栅极;
在所述半导体衬底内形成与栅介质层相邻的体区,所述体区具有第二导电类型;
在所述体区的上部形成第一导电类型的源极;
形成穿过所述源极并到达所述体区内一定深度的凹槽;
在所述体区内形成位于凹槽下方的第二导电类型的重掺杂区域;以及
在所述凹槽中填充金属而形成源极金属接触,
其特征在于,所述体区与所述半导体衬底之间形成凹形界面,使得所述体区在所述源极金属接触下方的部分的厚度比所述体区的其他部分更小。
5.如权利要求4所述的方法,其特征在于,在所述形成重掺杂区域的步骤中形成至少一个第二导电类型重掺杂区域。
6.如权利要求5所述的方法,其特征在于,所述至少一个第二导电类型重掺杂区域中的最顶部的一个和所述源极金属接触相接触。
7.如权利要求4所述的方法,其特征在于,所述形成体区的步骤包括在所述源极上部使用掩模以在半导体衬底中进行至少一次离子注入。
8.如权利要求7所述的方法,其特征在于,所述掩模为光刻胶或氧化物。
9.如权利要求7所述的方法,其特征在于,所述至少一次离子注入包括使用第一能量进行离子注入,使所述半导体衬底位于所述掩模下方的部分不具有注入的离子。
10.如权利要求7所述的方法,其特征在于,所述至少一次离子注入包括使用同一个掩模进行的不同深度的离子注入,使所述半导体衬底位于所述掩模下方的部分注入离子的深度小于所述体区的未遮挡部分的注入离子的深度。
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