CN106158973A - 一种积累型dmos - Google Patents
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- 238000009825 accumulation Methods 0.000 title claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000011982 device technology Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 20
- 238000000206 photolithography Methods 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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Abstract
本发明涉及功率半导体器件技术领域，具体涉及到一种积累型DMOS。本发明的积累型DMOS，其特征在于通过引入积累型区域，降低阈值电压和导通电阻；该结构体内嵌入场板，可以实现电荷平衡，在击穿电压相同的情况下，降低器件的导通电阻；槽型栅电极底部采用的厚氧结构，栅漏电容可以得到有效的降低。采用本发明可以在不影响反向击穿电压和泄漏电流的情况下，具有较大的正向电流、较小的阈值电压、较小的导通电阻以及较小的栅漏电容等特性。
Description
技术领域
本发明涉及功率半导体器件技术领域，具体涉及到一种积累型DMOS(双扩散金属氧化物半导体场效应晶体管)。
背景技术
功率MOS器件的发展是在MOS器件自身优点的基础上，努力提高耐压和降低损耗的过程。
VDMOS兼有双极晶体管和普通MOS器件的优点。与双极晶体管相比，它的开关速度快，开关损耗小；输入阻抗高，驱动功率小；频率特性好；跨导高度线性。特别值得指明出的是，大电流时它具有负的温度系数，没有双极功率器件的二次击穿问题，安全工作区大。但是对于VDMOSFET结构而言，由于其内部JFET区的存在，使VDMOS的导通电阻较大。TRENCHMOSFET结构上采用U型沟槽结构，导电沟道为纵向沟道，消除了JFET区电阻，所以其导通电阻更小。
在低压和超低压方向，漏源通态电阻(specific on-resistance)Rds(on)和单位面积栅极电荷Qg是两个重要参数。减小源漏通态电阻有利于降低通态损耗，减小栅极电荷则有利于降低开关损耗。但是，现在很难对两个参数同时进行大幅度的优化，这是因为以现有的工艺，优化其中的任何一个参数必将对另一个参数带来一定不利的影响。为了提高DMOS的性能，国内外提出了Trench底部厚SiO2结构(BOX)和分栅结构(Split-gate)等新型结构。一般情况下，BOX结构的“Miller”电荷比Split-gate的高，但它的栅极电荷比Split-gate的低。但是，由于Split-gate结构可利用其第一层多晶层(Shield)作为“体内场板”来降低漂移区的电场，所以Split-gate结构通常具有更低的导通电阻和更高的击穿电压，并可用于较高电压(20V-250V)的TRENCH MOS产品。
虽然国内外公司在优化导通电阻和栅电荷方面取得了较大的进展，但是近年来，激烈的市场竞争对器件的性能要求越来越高，所以如何采用先进的MOSFET结构设计同时降低器件Rds(on)及Qg仍然是各个厂家努力的方向。本发明提出的结构可以进一步改善器件的通态损耗和开关损耗。
发明内容
本发明的目的是提供一种槽型电荷平衡的积累型DMOS，在槽型电荷平衡的DMOS中引入积累型区域，使得DMOS的阈值电压较低、导通电阻较小且栅漏电容较小。
本发明所采用的技术方案：一种积累型DMOS，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11；所述N-漂移区3上层具有N-型轻掺杂区8和P型掺杂区9，所述N-型轻掺杂区8位于P型掺杂区9之间；所述N-型轻掺杂区8正上方具有N+重掺杂区7，所述P型掺杂区9正上方具有P+重掺杂区10；所述N+重掺杂区7和P+重掺杂区10的上表面与金属化源极11接触；还包括第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区7上表面中部垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中；所述第二沟槽沿P+重掺杂区10上表面垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中；所述第一沟槽和第二沟槽中填充有氧化层5，所述第一沟槽中具有栅电极4，所述第二沟槽中具有场板6，所述场板6的上表面与金属化源极11接触。
进一步的，所述氧化层5为二氧化硅或者二氧化硅和氮化硅的复合材料。
进一步的，所述栅电极4的材料为多晶硅。
进一步的，所述场板6的材料为多晶硅或者金属。
本发明的有益效果为，本发明所提供的槽型电荷平衡的积累型DMOS，具有较大的正向电流、阈值电压较小、导通电阻降低、栅漏电流改善以及较小的栅漏电容等优良特性。
附图说明
图1是本发明的积累型DMOS的剖面结构示意图；
图2是本发明的积累型DMOS在外加零电压时，耗尽线示意图；
图3是本发明的积累型DMOS外加电压到达阈值电压时的电流路径示意图；
图4图13是本发明的积累型DMOS的一种制造工艺流程的示意图；
图14至图23是本发明的积累型DMOS的另一种制造工艺流程的示意图。
具体实施方式
下面结合附图，详细描述本发明的技术方案：
如图1所示，本发明的一种积累型DMOS，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11；所述N-漂移区3上层具有N-型轻掺杂区8和P型掺杂区9，所述N-型轻掺杂区8位于P型掺杂区9之间；所述N-型轻掺杂区8正上方具有N+重掺杂区7，所述P型掺杂区9正上方具有P+重掺杂区10；所述N+重掺杂区7和P+重掺杂区10的上表面与金属化源极11接触；其特征在于，还包括第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区7上表面中部垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中；所述第二沟槽沿P+重掺杂区10上表面垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中；所述第一沟槽和第二沟槽中填充有氧化层5，所述第一沟槽中具有栅电极4，所述第二沟槽中具有场板6，所述场板6的上表面与金属化源极11接触。
本发明的工作原理为：
(1)器件的正向导通
本发明所提供的槽型电荷平衡的积累型DMOS，其正向导通时的电极连接方式为：槽型栅电极4接正电位，金属化漏极1接正电位，金属化源极11接零电位。当槽型栅电极4为零电压或所加正电压非常小时，由于P型掺杂区9的掺杂浓度大于N-型轻掺杂区8的掺杂浓度，P型掺杂区9和N-型轻掺杂区8所构成的PN结的内建电势会使得P型掺杂区9和栅氧化层5之间的N-型轻掺杂区8耗尽，电子通道被阻断，如图2所示，此时积累型DMOS仍处于关闭状态。
随着槽型栅电极4所加正电压的增加，P型掺杂区9和N-型轻掺杂区8所构成的PN结的内建势垒区逐渐缩小。由于N-型轻掺杂区8的存在，器件更容易开启，从而降低了阈值电压。当槽型栅电极4所加正电压等于或大于开启电压之后，由于栅氧化层5侧面处的N-型轻掺杂区8内产生多子电子的积累层，这为多子电流的流动提供了一条低阻通路，导通电阻从而得到降低，如图3所示，此时积累型DMOS导通，多子电子在金属化漏极1正电位的作用下从N+重掺杂区7流向金属化漏极1。另外，由于槽型栅电极4底部的栅氧化层5采取厚氧工艺，所以栅漏电容Cgd得到较大的改善。
(2)器件的反向阻断
本发明所提供的槽型电荷平衡的积累型DMOS，其反向阻断时的电极连接方式为：槽型栅电极4和金属化源极11短接且接零电位，金属化漏极1接正电位。
由于零偏压时P型掺杂区9和栅氧化层5之间的N-型轻掺杂区8已经被完全耗尽，多子电子的导电通路被夹断。增大反向电压时，由于体内场板6的存在，体内场板6和N-漂移区3构成横向电场，体内场板6和栅氧化层5之间的N-漂移区3首先耗尽，承受反向电压。继续增大反向电压时，耗尽层边界将向靠近金属化漏极1一侧的N-漂移区3扩展以承受反向电压。与普通的槽型DMOS相比，在N-漂移区3掺杂浓度相同的情况下，由于体内场板6的存在，N-漂移区3内可以实现电荷平衡，形成横向电场，在击穿电压相同时，槽型电荷平衡的积累型DMOS的导通电阻更小，且栅漏电流更小。
本发明的积累型DMOS的一种制造工艺流程如下：
1、单晶硅准备及外延生长。如图4，采用N型重掺杂单晶硅衬底2，晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3。
2、离子注入。如图5，利用光刻板进行P型柱区硼注入，形成P型掺杂区9，进行N型柱区磷注入，此处磷的注入剂量应较低，形成N型轻掺杂区8。
3、刻槽。如图6，淀积硬掩膜(如氮化硅)，利用光刻板刻蚀硬掩膜，进行深槽刻蚀，刻蚀出槽栅区和体内场板区，具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀。
4、二氧化硅的填充。如图7，用二氧化硅填充槽栅区和体内场板区。
5、体内场板中二氧化硅的刻蚀。如图8，利用光刻板先对体内场板区中的二氧化硅进行刻蚀。
6、二氧化硅的刻蚀。如图9，移去光刻板，对槽栅区和体内场板区中的二氧化硅同时进行刻蚀，去掉硬掩膜，此时槽栅区中仍留有较厚的二氧化硅5。
7、氧化层热生长。如图10，对槽栅区和体内场板区侧壁进行氧化层热生长，其中槽栅区形成侧壁栅氧化层5。
8、多晶硅的淀积与刻蚀。如图11，淀积多晶硅，多晶硅的厚度要保证能够填满槽型区域。利用光刻板对槽栅区的多晶硅刻蚀，并槽栅区上方淀积二氧化硅，并刻蚀表面二氧化硅。
9、离子注入。如图12，P型重掺杂区硼注入，形成P+重掺杂区10，N型重掺杂区砷注入，形成N+重掺杂区7。
10、金属化。如图13，正面金属化，金属刻蚀，背面金属化，钝化等等。
本发明的积累型DMOS的另一种制造工艺流程如下：
1、单晶硅准备及外延生长。如图14，采用N型重掺杂单晶硅衬底2，晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3。
2、刻槽。如图15，淀积硬掩膜(如氮化硅)，利用光刻板刻蚀硬掩膜，进行深槽刻蚀，刻蚀出槽栅区和体内场板区，具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀。
3、二氧化硅的填充。如图16用二氧化硅填充槽栅区和体内场板区。
4、体内场板中二氧化硅的刻蚀。如图17，利用光刻板先对体内场板区中的二氧化硅进行刻蚀。
5、二氧化硅的刻蚀。如图,18，移去光刻板，对槽栅区和体内场板区中的二氧化硅同时进行刻蚀，去掉硬掩膜，此时槽栅区中仍留有较厚的二氧化硅5。
6、氧化层热生长。如图19，对槽栅区和体内场板区侧壁进行氧化层热生长，其中槽栅区形成侧壁栅氧化层5。
7、多晶硅的淀积与刻蚀。如图20，淀积多晶硅，多晶硅的厚度要保证能够填满槽型区域。利用光刻板对槽栅区的多晶硅刻蚀，并槽栅区上方淀积二氧化硅，并刻蚀表面二氧化硅。
8、扩散掺杂。如图21，利用光刻板进行P型柱区扩散掺杂，形成P型掺杂区9，进行N型柱区扩散掺杂，此处磷的掺杂剂量应较低，形成N型轻掺杂区8。
9、离子注入。如图22，P型重掺杂区硼注入，形成P+重掺杂区10，N型重掺杂区砷注入，形成N+重掺杂区7。
10、金属化。如图23，正面金属化，金属刻蚀，背面金属化，钝化等等。
制作器件时，还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。
采用本发明的一种槽型电荷平衡的积累型DMOS，具有较大的正向电流、阈值电压较小、导通电阻降低、栅漏电流改善以及较小的栅漏电容等优良特性。
Claims (4)
1.一种积累型DMOS，包括从下至上依次层叠设置的金属化漏极(1)、N+衬底(2)、N-漂移区(3)和金属化源极(11)；所述N-漂移区(3)上层具有N-型轻掺杂区(8)和P型掺杂区(9)，所述N-型轻掺杂区(8)位于P型掺杂区(9)之间；所述N-型轻掺杂区(8)正上方具有N+重掺杂区(7)，所述P型掺杂区(9)正上方具有P+重掺杂区(10)；所述N+重掺杂区(7)和P+重掺杂区(10)的上表面与金属化源极(11)接触；还包括第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区(7)上表面中部垂直向下依次贯穿N+重掺杂区(7)和N-型轻掺杂区(8)后延伸入N-漂移区(3)中；所述第二沟槽沿P+重掺杂区(10)上表面垂直向下依次贯穿N+重掺杂区(7)和N-型轻掺杂区(8)后延伸入N-漂移区(3)中；所述第一沟槽和第二沟槽中填充有氧化层(5)，所述第一沟槽中具有栅电极(4)，所述第二沟槽中具有场板(6)，所述场板(6)的上表面与金属化源极(11)接触。
2.根据权利要求1所述的一种积累型DMOS，其特征在于，所述氧化层(5)为二氧化硅或者二氧化硅和氮化硅的复合材料。
3.根据权利要求1所述的一种积累型DMOS，其特征在于，所述栅电极(4)的材料为多晶硅。
4.根据权利要求1所述的一种积累型DMOS，其特征在于，所述场板(6)的材料为多晶硅或者金属。
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