CN113035863B - 一种引入纵向沟道结构的功率集成芯片 - Google Patents

一种引入纵向沟道结构的功率集成芯片 Download PDF

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CN113035863B
CN113035863B CN202110235396.8A CN202110235396A CN113035863B CN 113035863 B CN113035863 B CN 113035863B CN 202110235396 A CN202110235396 A CN 202110235396A CN 113035863 B CN113035863 B CN 113035863B
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盛况
刘立
王珏
于浩
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Zhejiang University ZJU
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Abstract

本发明涉及一种引入纵向沟道结构的功率集成芯片，包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N‑横向漂移区和纵向沟道区；P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方一边设置MOSFET，纵向耐压区上方另一边设置二极管区域。本发明的有益效果是：通过加入纵向沟道区并适当调节其沟道长度，来增加纵向耗尽层在N型层的极限深度；当漏极/阳极对源极/参考地形成高压降时，避免了因耗尽层边界扩展到二极管阳极而出现的纵向穿通问题。纵向沟道区提升了功率集成芯片的纵向耐压能力和整体耐压水平，拓宽了芯片的应用范围。

Description

一种引入纵向沟道结构的功率集成芯片
技术领域
本发明属于功率集成芯片领域，尤其涉及一种引入纵向沟道结构的功率集成芯片。
背景技术
常规功率集成芯片的结构示意图如图4-1所示。芯片在工作模态II时，二极管阳极对参考地之间有较高的压降。由于N-型层(横向漂移层)厚度有限，导致该层在对地高压降时处于耗尽的状态，阳极与参考地出现纵向穿通的问题。在图4-2-1和图4-2-2中，漏极/阳极对源极/参考地之间的压降在未达到雪崩击穿电压时，从阳极到参考地之间已经有一道明显的纵向漏电流路径，说明纵向已经处于穿通状态了。
因此，为了提升器件整体的纵向耐压能力，提出一种引入纵向沟道结构的功率集成芯片，就显得尤为重要。
发明内容
本发明的目的是克服现有技术中的不足，提供一种引入纵向沟道结构的功率集成芯片。
一种引入纵向沟道结构的功率集成芯片，见图1，包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区和纵向沟道区；其中P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方一边设置MOSFET，纵向耐压区上方另一边设置二极管区域，MOSFET和二极管区域之间设有隔离区；隔离区左右两侧均为N-横向漂移区，N-横向漂移区作为承担横向耐压的主要区域，同时也与纵向耐压区共同承担纵向压降，但纵向耐压区作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区部分嵌入纵向耐压区，二极管区域的纵向沟道区位于二极管靠近隔离区的一侧，纵向沟道区紧贴隔离区设置，纵向沟道区部分嵌入位于隔离区右侧的N-横向漂移区；纵向沟道区的沟道长度可调。
一种引入纵向沟道结构的功率集成芯片，见图3(a),包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区和纵向沟道区；其中P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方靠左设置MOSFET，纵向耐压区上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区；隔离区左右两侧均为N-横向漂移区，N-横向漂移区作为承担横向耐压的主要区域，同时也与纵向耐压区共同承担纵向压降，但纵向耐压区作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区部分嵌入纵向耐压区，二极管区域的纵向沟道区位于二极管靠近隔离区的一侧，纵向沟道区紧贴隔离区设置，纵向沟道区部分嵌入位于隔离区右侧的N-横向漂移区；纵向沟道区的沟道长度可调；还在二极管的阴极下方增加了阴极纵向延伸区,使得阴极N+位于二极管槽底以上；也在不增加元胞宽度的同时，不仅能延长二极管阴极与阳极之间距离，还能改善电场分布(在阴极N+附近的高电场得到缓解)，进而增加二极管耐压能力。
一种引入纵向沟道结构的功率集成芯片，见图3(b),包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区和纵向沟道区；其中P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方靠左设置MOSFET，纵向耐压区上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区；隔离区左右两侧均为N-横向漂移区，N-横向漂移区作为承担横向耐压的主要区域，同时也与纵向耐压区共同承担纵向压降，但纵向耐压区作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区部分嵌入纵向耐压区，二极管区域的纵向沟道区位于二极管靠近隔离区的一侧，纵向沟道区紧贴隔离区设置，纵向沟道区部分嵌入位于隔离区右侧的N-横向漂移区；纵向沟道区的沟道长度可调；二极管阳极的金属场板往下延伸到纵向沟道区,形成纵向场板；金属(Mental)-介质层(Oxide)-沟道区(Semiconductor)一同形成类似于TMBS(沟槽型MOS结构肖特基二极管)的结构；二极管阻断时，沟道区域的耗尽层扩散，将增强肖特基接触结位置的电场屏蔽，降低了漏电流。
一种引入纵向沟道结构的功率集成芯片，见图3(c),包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区和纵向沟道区；其中P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方靠左设置MOSFET，纵向耐压区上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区；隔离区左右两侧均为N-横向漂移区，N-横向漂移区作为承担横向耐压的主要区域，同时也与纵向耐压区共同承担纵向压降，但纵向耐压区作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区部分嵌入纵向耐压区，二极管区域的纵向沟道区位于二极管靠近隔离区的一侧，纵向沟道区紧贴隔离区设置，纵向沟道区部分嵌入位于隔离区右侧的N-横向漂移区；纵向沟道区的沟道长度可调；二极管阳极下方的纵向沟道区内紧贴二极管阳极处还增加了P+区，在二极管阻断时，增强了肖特基接触结处的屏蔽效果，有助于降低器件漏电流。
一种引入纵向沟道结构的功率集成芯片，见图3(d),包括：P型衬底区、纵向耐压区、隔离区、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区和纵向沟道区；其中P型衬底区位于芯片底部，P型衬底区上方设置纵向耐压区，纵向耐压区上方靠左设置MOSFET，纵向耐压区上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区；隔离区左右两侧均为N-横向漂移区，N-横向漂移区作为承担横向耐压的主要区域，同时也与纵向耐压区共同承担纵向压降，但纵向耐压区作为主要的纵向耐压区域；隔离区部分嵌入纵向耐压区，二极管区域的纵向沟道区位于二极管靠近隔离区的一侧，纵向沟道区紧贴隔离区设置，纵向沟道区部分嵌入位于隔离区右侧的N-横向漂移区；纵向沟道区的沟道长度可调；MOSFET内的沟道为垂直沟道(沟槽栅)，沟槽栅结构能够减小元胞的宽度，有利于增加功率密度。
作为优选，MOSFET和二极管在同一片晶圆上横向制造，并且在元胞层面互连。
作为优选，MOSFET的源极接地，MOSFET的漏极短接二极管阳极形成MOSFET的漏极与二极管阳极短接部分，MOSFET的漏极与二极管阳极短接部分位于隔离区上方；MOSFET和二极管的其他电极引出后与外电路连接。
作为优选，MOSFET为横向MOSFET(LDMOS)，二极管为肖特基二极管。
本发明的有益效果是：本发明通过加入纵向沟道区并适当调节其沟道长度，来增加纵向耗尽层在N型层的极限深度；当漏极/阳极对源极/参考地形成高压降时，避免了因耗尽层边界扩展到二极管阳极而出现的纵向穿通问题。纵向沟道区提升了功率集成芯片的纵向耐压能力和整体耐压水平，拓宽了芯片的应用范围。
附图说明
图1为引入纵向沟道结构的Boost功率集成芯片元胞结构图；
图2-1为引入纵向沟道结构的Boost电路示意图；
图2-2为沟槽型MOS结构肖特基二极管(TMBS)结构示意图；
图2-3为引入纵向沟道结构的Boost功率集成芯片在工作模态II时的电势分布(左图)与漏电流分布(右图)，对应图2-5中的B点(LDMOS击穿前，未穿通)；
图2-4为引入纵向沟道结构的Boost功率集成芯片在工作模态II时的电势分布(左图)与漏电流分布(右图)，对应图2-5的C点，(LDMOS击穿时，未穿通)；
图2-5为引入纵向沟道结构的Boost功率集成芯片与常规Boost功率集成芯片的耐压对比结果图；
图3中(a)为在阴极下方增加阴极纵向延伸区的引入纵向沟道结构的Boost功率集成芯片示意图；(b)为在MOSFET的漏极与二极管的阳极短接部分设置纵向场板的引入纵向沟道结构的Boost功率集成芯片示意图；(c)为在二极管的阳极下方增加了P+区的引入纵向沟道结构的Boost功率集成芯片示意图；(d)为将MOSFET的沟道方向由横向沟道变成了垂直沟道的引入纵向沟道结构的Boost功率集成芯片示意图；
图4-1为常规Boost功率集成芯片元胞结构图；
图4-2-1为常规Boost功率集成芯片在工作模态II时的电势分布图；
图4-2-2为常规Boost功率集成芯片在工作模态II时的漏电流分布图，对应图2-5的A点。
附图标记说明：
源极1、栅极2、MOSFET的漏极与二极管的阳极短接部分3、二极管阴极4、N-横向漂移区5、隔离区6、纵向沟道区7、纵向耐压区8、P型衬底区9、MOSFET的漏极10、二极管阳极11、半导体12、介质层13、金属层14、MOSFET15、阴极纵向延伸区16、纵向场板17、沟槽栅结构18。
具体实施方式
下面结合实施例对本发明做进一步描述。下述实施例的说明只是用于帮助理解本发明。应当指出，对于本技术领域的普通人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干修饰，这些改进和修饰也落入本发明权利要求的保护范围内。
实施例1：
一种引入纵向沟道结构的功率集成芯片，如图1所示，包括：P型衬底区9、纵向耐压区8、隔离区6、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区5和纵向沟道区7；其中P型衬底区9位于芯片底部，P型衬底区9上方设置纵向耐压区8，纵向耐压区8上方靠左设置MOSFET，纵向耐压区8上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区6；隔离区6左右两侧均为N-横向漂移区5，N-横向漂移区5作为承担横向耐压的主要区域，同时也与纵向耐压区8共同承担纵向压降，但纵向耐压区8作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区6部分嵌入纵向耐压区8，二极管区域的纵向沟道区7位于二极管靠近隔离区6的一侧，纵向沟道区7紧贴隔离区6设置，纵向沟道区7部分嵌入位于隔离区6右侧的N-横向漂移区5；纵向沟道区7的沟道长度可调。
如图2-1所示，MOSFET的源极1接地，MOSFET的漏极10短接二极管阳极11形成MOSFET的漏极与二极管阳极短接部分3，MOSFET的漏极与二极管阳极短接部分3位于隔离区6上方；MOSFET和二极管的其他电极引出后与外电路连接。
针对纵向穿通问题，本实施例在二极管阳极11位置加入一个纵向沟道区(Vertical Channel)。纵向沟道区增加了耗尽层在N-型层的极限深度，来阻止耗尽层边界扩展到二极管阳极，进而提升了器件整体的纵向耐压能力。纵向沟道区可以通过刻蚀工艺形成，与阳极直接形成类似于TMBS(沟槽型MOS结构肖特基二极管)的结构，如图2-2所示。在二极管阴极对阳极进行反偏阻断时，与MOS接触的耗尽区扩散，将肖特基接触结夹断，起到了电场屏蔽的效果，有助于降低肖特基接触结的漏电流。
图2-3中左图为引入纵向沟道区的器件，在模态II工作时的电势分布，其中VD＝VA≈VK＝1200V，LDMOS处于未击穿的状态，此时器件几乎无纵向漏电流，如图2-3中右图所示；对应图2-5中的B点(LDMOS击穿前，未穿通)；
如图2-4中左右两图所示，当VD＝VA≈VK＝1222V，LDMOS器件因碰撞电离导致载流子雪崩倍增，进而出现击穿现象。虽然其漏极对参考地/源极的漏电流急剧增加，但是阳极对参考地并未出现穿通现象；对应图2-5的C点，(LDMOS击穿时，未穿通)；
因此，对于外延设计为TP＝10um,nP＝1e15cm-3；TN＝1.0um,nN＝5e16cm-3的常规结构器件，仿真得到的最高纵向耐压为320V，此时阳极对参考地出现了纵向穿通现象。而采用纵向沟道区的器件，则能保证其具有较高的纵向耐压水平。如图2-5所示，如果沟道长度为2um，采用新结构的芯片即便在LDMOS部分已经击穿的时候(C点，阳极对参考地压降为1222V)，仍然能够确保阳极对参考地的状态是不穿通的。
实施例2：
一种引入纵向沟道结构的功率集成芯片，如图3(a)所示，包括：P型衬底区9、纵向耐压区8、隔离区6、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区5和纵向沟道区7；其中P型衬底区9位于芯片底部，P型衬底区9上方设置纵向耐压区8，纵向耐压区8上方靠左设置MOSFET，纵向耐压区8上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区6；隔离区6左右两侧均为N-横向漂移区5，N-横向漂移区5作为承担横向耐压的主要区域，同时也与纵向耐压区8共同承担纵向压降，但纵向耐压区8作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区6部分嵌入纵向耐压区8，二极管区域的纵向沟道区7位于二极管靠近隔离区6的一侧，纵向沟道区7紧贴隔离区6设置，纵向沟道区7部分嵌入位于隔离区6右侧的N-横向漂移区5；纵向沟道区7的沟道长度可调；还在二极管阴极4下方增加了阴极纵向延伸区16,使得阴极N+位于二极管槽底以上；也在不增加元胞宽度的同时，不仅能延长二极管阴极与阳极之间距离，还能改善电场分布(在阴极N+附近的高电场得到缓解)，进而增加二极管耐压能力。
实施例3：
一种引入纵向沟道结构的功率集成芯片，如图3(b)所示，包括：P型衬底区9、纵向耐压区8、隔离区6、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区5和纵向沟道区7；其中P型衬底区9位于芯片底部，P型衬底区9上方设置纵向耐压区8，纵向耐压区8上方靠左设置MOSFET，纵向耐压区8上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区6；隔离区6左右两侧均为N-横向漂移区5，N-横向漂移区5作为承担横向耐压的主要区域，同时也与纵向耐压区8共同承担纵向压降，但纵向耐压区8作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区6部分嵌入纵向耐压区8，二极管区域的纵向沟道区7位于二极管靠近隔离区6的一侧，纵向沟道区7紧贴隔离区6设置，纵向沟道区7部分嵌入位于隔离区6右侧的N-横向漂移区5；纵向沟道区7的沟道长度可调；二极管阳极11的金属场板往下延伸到纵向沟道区7,形成纵向场板17；金属(Mental)-介质层(Oxide)-沟道区(Semiconductor)一同形成类似于TMBS(沟槽型MOS结构肖特基二极管)的结构；二极管阻断时，沟道区域的耗尽层扩散，将增强肖特基接触结位置的电场屏蔽，降低了漏电流。
实施例4：
一种引入纵向沟道结构的功率集成芯片，如图3(c)所示，包括：P型衬底区9、纵向耐压区8、隔离区6、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区5和纵向沟道区7；其中P型衬底区9位于芯片底部，P型衬底区9上方设置纵向耐压区8，纵向耐压区8上方靠左设置MOSFET，纵向耐压区8上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区6；隔离区6左右两侧均为N-横向漂移区5，N-横向漂移区5作为承担横向耐压的主要区域，同时也与纵向耐压区8共同承担纵向压降，但纵向耐压区8作为主要的纵向耐压区域；MOSFET内的沟道为横向沟道(平面栅)；隔离区6部分嵌入纵向耐压区8，二极管区域的纵向沟道区7位于二极管靠近隔离区6的一侧，纵向沟道区7紧贴隔离区6设置，纵向沟道区7部分嵌入位于隔离区6右侧的N-横向漂移区5；纵向沟道区7的沟道长度可调；二极管阳极11下方的纵向沟道区7内紧贴二极管阳极11处还增加了P+区，在二极管阻断时，增强了肖特基接触结处的屏蔽效果，有助于降低器件漏电流。
实施例5：
一种引入纵向沟道结构的功率集成芯片，如图3(d)所示，包括：P型衬底区9、纵向耐压区8、隔离区6、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区5和纵向沟道区7；其中P型衬底区9位于芯片底部，P型衬底区9上方设置纵向耐压区8，纵向耐压区8上方靠左设置MOSFET，纵向耐压区8上方靠右设置二极管区域，MOSFET和二极管区域之间设有隔离区6；隔离区6左右两侧均为N-横向漂移区5，N-横向漂移区5作为承担横向耐压的主要区域，同时也与纵向耐压区8共同承担纵向压降，但纵向耐压区8作为主要的纵向耐压区域；隔离区6部分嵌入纵向耐压区8，二极管区域的纵向沟道区7位于二极管靠近隔离区6的一侧，纵向沟道区7紧贴隔离区6设置，纵向沟道区7部分嵌入位于隔离区6右侧的N-横向漂移区5；纵向沟道区7的沟道长度可调；MOSFET内的沟道为垂直沟道(沟槽栅)，沟槽栅结构能够减小元胞的宽度，有利于增加功率密度。

Claims (4)

1.一种引入纵向沟道结构的功率集成芯片，其特征在于，包括：P型衬底区(9)、纵向耐压区(8)、隔离区(6)、MOSFET和二极管区域；所述二极管区域包括二极管、N-横向漂移区(5)和纵向沟道区(7)；其中P型衬底区(9)位于芯片底部，P型衬底区(9)上方设置纵向耐压区(8)，纵向耐压区(8)上方一边设置MOSFET，纵向耐压区(8)上方另一边设置二极管区域，MOSFET和二极管区域之间设有隔离区(6)；隔离区(6)左右两侧均为N-横向漂移区(5)；MOSFET内的沟道为横向沟道；隔离区(6)部分嵌入纵向耐压区(8)，二极管区域的纵向沟道区(7)位于二极管靠近隔离区(6)的一侧，纵向沟道区(7)紧贴隔离区(6)设置，纵向沟道区(7)部分嵌入位于隔离区(6)右侧的N-横向漂移区(5)；纵向沟道区(7)的沟道长度可调；
二极管阳极(11)的金属场板往下延伸到纵向沟道区(7),形成纵向场板(17)。
2.根据权利要求1所述引入纵向沟道结构的功率集成芯片，其特征在于：MOSFET和二极管在同一片晶圆上横向制造，并且在元胞层面互连。
3.根据权利要求1所述引入纵向沟道结构的功率集成芯片，其特征在于：MOSFET的源极(1)接地，MOSFET的漏极(10)短接二极管阳极(11)形成MOSFET的漏极与二极管阳极短接部分(3)，MOSFET的漏极与二极管阳极短接部分(3)位于隔离区(6)上方；MOSFET和二极管的其他电极引出后与外电路连接。
4.根据权利要求1所述引入纵向沟道结构的功率集成芯片，其特征在于：MOSFET为横向MOSFET，二极管为肖特基二极管。
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