CN106098777A - 一种***栅积累型dmos器件 - Google Patents
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Abstract
本发明属于功率半导体技术领域,涉及一种***栅积累型DMOS器件。本发明主要在于通过引入积累型区域,降低阈值电压和导通电阻;同时,本发明具有Split‑gate结构的优点。采用本发明可以具有较大的正向电流、较小的阈值电压、较小的导通电阻以及更高的抗漏极电压震荡对栅极影响的能力等特性。
Description
技术领域
本发明属于功率半导体技术领域,涉及一种***栅积累型DMOS器件。
背景技术
功率MOS器件的发展是在MOS器件自身优点的基础上,努力提高耐压和降低损耗的过程。
VDMOSFET是一种采用双扩散工艺的平面结构,它是第一个成功商业应用的功率MOSFET,对功率MOSFET的发展起到了关键的推动作用。在VDMOSFET结构中,不需要昂贵的掩模板而是通过控制两个结的深度形成沟道。但由于其内部JFET区的存在,使VDMOSFET的导通电阻较大,这也为槽栅功率器件的发展提供了机会。Trench MOSFET结构采用U型沟槽结构,导电沟道为纵向沟道,和VDMOSFET一样,Trench MOSFET也是高元胞密度器件,但是Trench MOSFET消除了JFET区电阻,所以其导通电阻更小,这使其在商业应用中较受欢迎。
在低压和超低压方向,漏源通态电阻(specific on-resistance)Rds(on)和单位面积栅极电荷Qg是两个重要参数。减小源漏通态电阻有利于降低通态损耗,减小栅极电荷则有利于降低开关损耗。但是,现在很难对两个参数同时进行大幅度的优化,这是因为以现有的工艺,优化其中的任何一个参数必将对另一个参数带来一定不利的影响。为了提高DMOS的性能,国内外提出了浮岛单极器件和分栅结构(Split-gate)等新型结构。浮岛单极器件通过在N-外延层中增加P型分压岛,从而漂移区的最大电场被分成两部分,在同样的外延层掺杂浓度下,击穿电压可以有所上升。而Split-gate结构可利用其第一层多晶层(Shield)作为“体内场板”来降低漂移区的电场,所以Split-gate结构通常具有更低的导通电阻和更高的击穿电压,并可用于较高电压(20V-250V)的TRENCH MOS产品。
虽然浮岛单极器件和分栅结构(Split-gate)等新型结构在优化导通电阻和栅电荷方面取得了较大的进展。但是近年来,激烈的市场竞争对器件的性能要求越来越高,所以如何采用先进的MOSFET结构设计同时降低器件Rds(on)及Qg仍然是各个厂家努力的方向。
发明内容
本发明所要解决的,就是针对上述问题,提出一种***栅积累型DMOS器件。
本发明的技术方案是:如图1所示,一种***栅积累型DMOS器件,包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11;所述N-漂移区3中具有氧化层6、条形N-型轻掺杂区7、P型掺杂区8、P+重掺杂区9和N+重掺杂区10;所述氧化层6位于两侧的N-型轻掺杂区7和N+重掺杂区10之间,氧化层6的上表面与金属化源极11接触;所述N+重掺杂区10位于N-型轻掺杂区7的正上方并与N-型轻掺杂区7接触,N+重掺杂区10的上表面与金属化源极11接触;所述N-型轻掺杂区7远离氧化层的一侧与P型掺杂区8接触,P型掺杂区8的结深与N-型轻掺杂区7的结深相同,所述P+重掺杂区9位于P型掺杂区8的正上方并与P型掺杂区8接触,P+重掺杂区9的上表面与金属化源极11接触;所述氧化层6中具有控制栅电极4和屏蔽栅电极5,所述控制栅电极4位于屏蔽栅电极5的上方,所述控制栅电极4上表面的结深小于N+重掺杂区10下表面的结深,控制栅电极4下表面的结深大于N-型轻掺杂区7下表面的结深。
进一步的,所述氧化层6采用的材料为二氧化硅或者二氧化硅和氮化硅的复合材料。
进一步的,所述控制栅电极4和屏蔽栅电极5采用的材料为多晶硅。
本发明的有益效果为,相比于传统结构,本发明的结构具有较大的正向电流、较小的阈值电压、较小的导通电阻以及更高的抗漏极电压震荡对栅极影响的能力等特性。
附图说明
图1是本发明的***栅积累型DMOS器件的剖面结构示意图;
图2是本发明的***栅积累型DMOS器件在外加零电压时,耗尽线示意图;
图3是本发明的***栅积累型DMOS器件外加电压到达阈值电压时的电流路径示意图;
图4-图12是本发明的***栅积累型DMOS器件的一种制造工艺流程的示意图;
图13-图21是本发明的***栅积累型DMOS器件的另一种制造工艺流程的示意图。
具体实施方式
下面结合附图,详细描述本发明的技术方案:
如图1所示,本发明提出的一种***栅积累型DMOS器件,包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11;所述N-漂移区3中具有氧化层6、条形N-型轻掺杂区7、P型掺杂区8、P+重掺杂区9和N+重掺杂区10;所述氧化层6位于两侧的N-型轻掺杂区7和N+重掺杂区10之间,氧化层6的上表面与金属化源极11接触;所述N+重掺杂区10位于N-型轻掺杂区7的正上方并与N-型轻掺杂区7接触,N+重掺杂区10的上表面与金属化源极11接触;所述N-型轻掺杂区7远离氧化层的一侧与P型掺杂区8接触,P型掺杂区8的结深与N-型轻掺杂区7的结深相同,所述P+重掺杂区9位于P型掺杂区8的正上方并与P型掺杂区8接触,P+重掺杂区9的上表面与金属化源极11接触;所述氧化层6中具有控制栅电极4和屏蔽栅电极5,所述控制栅电极4位于屏蔽栅电极5的上方,所述控制栅电极4上表面的结深小于N+重掺杂区10下表面的结深,控制栅电极4下表面的结深大于N-型轻掺杂区7下表面的结深。
本发明的工作原理为:
本发明所提供的***栅积累型DMOS器件,其正向导通时的电极连接方式为:控制栅电极4接正电位,金属化漏极1接正电位,金属化源极11接零电位。当控制栅电极4为零电压或所加正电压非常小时,由于P型掺杂区8的掺杂浓度大于N-型轻掺杂区7的掺杂浓度,P型掺杂区8和N-型轻掺杂区7所构成的PN结的内建电势会使得P型掺杂区8和二氧化硅栅氧化层6之间的N-型轻掺杂区7耗尽,电子通道被阻断,如图2所示,此时积累型DMOS仍处于关闭状态。
随着控制栅电极4所加正电压的增加,P型掺杂区8和N-型轻掺杂区7所构成的PN结的内建势垒区逐渐缩小。由于N-型轻掺杂区7的存在,器件更容易开启,从而降低了阈值电压。当控制栅电极4所加正电压等于或大于开启电压之后,由于二氧化硅氧化层6侧面处的N-型轻掺杂区7内产生多子电子的积累层,这为多子电流的流动提供了一条低阻通路,如图3所示,此时积累型DMOS导通,多子电子在金属化漏极1正电位的作用下从N+重掺杂区10流向金属化漏极1。另外,由于屏蔽栅电极5的作用,栅漏电容Cgd有一部分被耦合为栅源电容Cgs,所以该结构具有更高的输入电容(Ciss)和“Miller”电容(Cgd)比值,从而拥有更高的抗漏极电压震荡对栅极影响的能力。
本发明的***栅积累型DMOS器件,其反向阻断时的电极连接方式为:控制栅电极4和金属化源极11短接且接零电位,金属化漏极1接正电位。
由于零偏压时P型掺杂区8和氧化层6之间的N-型轻掺杂区7已经被完全耗尽,多子电子的导电通路被夹断。增大反向电压时,耗尽层边界将向靠近金属化漏极1一侧的N-漂移区3扩展以承受反向电压。与普通的槽型DMOS相比,在N-漂移区3掺杂浓度相同的情况下,由于屏蔽栅电极5的存在,具有Split-gate结构的积累型DMOS的N-漂移区3内可以实现电荷平衡,形成横向电场,漂移区电场得到改善。在击穿电压相同时,具有Split-gate结构的积累型DMOS的导通电阻更小,且栅漏电流更小。
本发明所示的***栅积累型DMOS器件的一种制造工艺流程为:
1单晶硅准备及外延生长;如图4,采用N型重掺杂单晶硅衬底2,晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3;
2离子注入;如图5,利用光刻板进行P型柱区硼注入,形成P型掺杂区8,进行N型柱区磷注入,此处磷的注入剂量应较低,形成N型轻掺杂区7;
3刻槽;如图6,淀积硬掩膜(如氮化硅)作为后续挖槽的阻挡层,利用光刻板进行深槽刻蚀,刻蚀出槽栅区,具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀;
4二氧化硅的填充;如图7,去掉硬掩膜,在槽内生长厚二氧化硅层6;
5多晶硅的淀积与刻蚀;如图8,淀积屏蔽栅多晶硅5;利用光刻板刻掉厚氧化层和屏蔽栅多晶硅的上半部分;
6热氧化层生长;如图9,对槽栅区进行氧化层热生长,形成侧壁栅氧化层和屏蔽栅顶部的氧化层;
7多晶硅的淀积与刻蚀;如图10,淀积控制栅多晶硅4,多晶硅的厚度要保证能够填满槽型区域;利用光刻板对控制栅多晶硅刻蚀,并在控制栅多晶硅上方淀积二氧化硅,刻蚀表面二氧化硅;
8离子注入;如图11,P型重掺杂区硼注入,形成P+重掺杂区9,N型重掺杂区砷注入,形成N+重掺杂区10;
9金属化;如图12,正面金属化,金属刻蚀,背面金属化,钝化等等。
本发明所示的***栅积累型DMOS器件的另一种制造工艺流程为:
1单晶硅准备及外延生长;如图13,采用N型重掺杂单晶硅衬底2,晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3;
2刻槽;如图14,淀积硬掩膜(如氮化硅)作为后续挖槽的阻挡层,利用光刻板进行深槽刻蚀,刻蚀出槽栅区,具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀;
3二氧化硅的填充;如图15,去掉硬掩膜,在槽内生长厚二氧化硅层6;
4多晶硅的淀积与刻蚀;如图16,淀积屏蔽栅多晶硅5。利用光刻板刻掉厚氧化层和屏蔽栅多晶硅的上半部分;
5热氧化层生长;如图17,对槽栅区进行氧化层热生长,形成侧壁栅氧化层和屏蔽栅顶部的氧化层;
6多晶硅的淀积与刻蚀;如图18,淀积控制栅多晶硅4,多晶硅的厚度要保证能够填满槽型区域。利用光刻板对控制栅多晶硅刻蚀,并在控制栅多晶硅上方淀积二氧化硅,刻蚀表面二氧化硅;
7扩散掺杂;如图19,利用光刻板进行P型柱区扩散掺杂,形成P型掺杂区8,进行N型柱区扩散掺杂,此处磷的掺杂剂量应较低,形成N型轻掺杂区7;
8离子注入;如图20,P型重掺杂区硼注入,形成P+重掺杂区9,N型重掺杂区砷注入,形成N+重掺杂区10;
9金属化;如图21,正面金属化,金属刻蚀,背面金属化,钝化等等。
制作器件时,还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。
采用本发明所提供的具有Split-gate结构的积累型DMOS,具有较大的正向电流、较小的阈值电压、较小的导通电阻以及更高的抗漏极电压震荡对栅极影响的能力等特性。
Claims (3)
1.一种***栅积累型DMOS器件,包括从下至上依次层叠设置的金属化漏极(1)、N+衬底(2)、N-漂移区(3)和金属化源极(11);所述N-漂移区(3)中具有氧化层(6)、条形N-型轻掺杂区(7)、P型掺杂区(8)、P+重掺杂区(9)和N+重掺杂区(10);所述氧化层(6)位于两侧的N-型轻掺杂区(7)和N+重掺杂区(10)之间,氧化层(6)的上表面与金属化源极(11)接触;所述N+重掺杂区(10)位于N-型轻掺杂区(7)的正上方并与N-型轻掺杂区(7)接触,N+重掺杂区(10)的上表面与金属化源极(11)接触;所述N-型轻掺杂区(7)远离氧化层的一侧与P型掺杂区(8)接触,P型掺杂区(8)的结深与N-型轻掺杂区(7)的结深相同,所述P+重掺杂区(9)位于P型掺杂区(8)的正上方并与P型掺杂区(8)接触,P+重掺杂区(9)的上表面与金属化源极(11)接触;所述氧化层(6)中具有控制栅电极(4)和屏蔽栅电极(5),所述控制栅电极(4)位于屏蔽栅电极(5)的上方,所述控制栅电极(4)上表面的结深小于N+重掺杂区(10)下表面的结深,控制栅电极(4)下表面的结深大于N-型轻掺杂区(7)下表面的结深。
2.根据权利要求1所述的一种***栅积累型DMOS器件,其特征在于,所述氧化层(6)采用的材料为二氧化硅或者二氧化硅和氮化硅的复合材料。
3.根据权利要求1所述的一种***栅积累型DMOS器件,其特征在于,所述控制栅电极(4)和屏蔽栅电极(5)采用的材料为多晶硅。
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