CN101933139B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN101933139B
CN101933139B CN2008801209553A CN200880120955A CN101933139B CN 101933139 B CN101933139 B CN 101933139B CN 2008801209553 A CN2008801209553 A CN 2008801209553A CN 200880120955 A CN200880120955 A CN 200880120955A CN 101933139 B CN101933139 B CN 101933139B
Authority
CN
China
Prior art keywords
insulating resin
circuit pattern
semiconductor chip
semiconductor device
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008801209553A
Other languages
English (en)
Other versions
CN101933139A (zh
Inventor
鹤冈纯司
青木一雄
小野正树
吉原克彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin AW Co Ltd
Fuji Electric Co Ltd
Original Assignee
Aisin AW Co Ltd
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin AW Co Ltd, Fuji Electric Co Ltd filed Critical Aisin AW Co Ltd
Publication of CN101933139A publication Critical patent/CN101933139A/zh
Application granted granted Critical
Publication of CN101933139B publication Critical patent/CN101933139B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/8421—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/84214—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Laser Beam Processing (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明提供如下的半导体装置及其制造方法：能够防止在激光焊接中产生的飞溅物附着于电路图案或半导体芯片，能够防止电气特性的劣化。利用焊锡(13)在形成于陶瓷(4)上的铜箔上固定连接导体(14)，在该连接导体(14)的上部面(P)的下方填充树脂(17a)并进行激光焊接，然后填充树脂(17b)，由此，能够防止在激光焊接中产生的飞溅物(21)附着于电路图案(5)、(6)或半导体芯片(8)的情况。由此，能够防止电气特性劣化。

Description

半导体装置及其制造方法
技术领域
本发明涉及IGBT（Insulated Gate Bipolar Transistor）或PIM（PowerIntegrated Module）等的半导体装置及其制造方法。
背景技术
图9是现有的半导体装置的主要部分剖面图。说明现有的半导体装置的组装步骤。通过焊锡2来接合由背面铜箔3、陶瓷4、电路图案5和电路图案6构成的绝缘电路基板的背面铜箔3和铜基体1，通过焊锡7来接合电路图案5和半导体芯片8。半导体芯片8是开关元件即IGBT或FWD（Free Wheeling Diode）等。
通常，利用一次加热步骤来进行这些焊锡接合。然后，利用超声波振动，利用键合线9（铝线等）来连接半导体芯片8上部的未图示的发射极电极和电路图案6。
接着，利用未图示的硅酮系粘接剂将嵌入成型有外部端子11的端子外壳10和铜基体1加热粘接。然后，对电路图案5和外部端子11以及电路图案6和外部端子11进行点激光焊接。该情况下的激光焊接中的激光的照射位置为外部端子11的上侧。然后，填充树脂17来覆盖半导体芯片8的表面。这样来制作现有的半导体装置。
并且，在专利文献1中公开了如下的半导体元件搭载用基板：该半导体元件搭载用基板是通过激光来接合形成了用于搭载半导体元件的布线图案的基板和引线来形成的，其中，与基板的电极衬垫接合的引线的前端部分形成为比引线的其他部分薄。
并且，在专利文献2中公开了如下的半导体装置的制造方法：该半导体装置具有：树脂密封体；第1半导体芯片和第2半导体芯片，其位于所述树脂密封体内部，且在表面背面中的表面形成有电极；第1引线，其在所述树脂密封体的内外延伸，与所述第1半导体芯片的电极电连接；以及第2引线，其在所述树脂密封体的内外延伸，与所述第2半导体芯片的电极电连接，其中，在使所述第1引线、第2引线各自重合的状态下形成所述树脂密封体，然后，对所述第1引线、第2引线各自进行激光焊接，由此，防止分散的飞溅物向半导体芯片的电路形成面飞来的情况。
专利文献1：日本特开平7-94845号公报
专利文献2：日本特开2006-74073号公报
在覆盖树脂17之前进行所述图9所示的激光焊接，进行该激光焊接时，如图10所示，飞散的飞溅物21使形成于绝缘基板（陶瓷4）的电路图案5、6（还包含未图示的布线图案）等短路，或者切断（溶断）键合线9等的布线，或者损伤半导体芯片8。
即，飞溅物21飞散，由此，引起绝缘基板（陶瓷4）的绝缘不良、电路图案5、6彼此的短路、引线布线的断线、针对半导体芯片8的物理损伤（溶融痕迹、细微的瑕疵、细微裂缝等）、以及半导体芯片8的电气特性不良（短路等）。
发明内容
本发明的目的在于，解决所述课题，提供如下的半导体装置及其制造方法：能够防止在激光焊接中产生的飞溅物附着于电路图案或半导体芯片，能够防止电气特性的劣化。
为了达成所述目的，
（1）半导体装置由以下部分构成：电路图案，其形成于绝缘基板上；半导体芯片，其固定于所述电路图案上；连接导体，其固定于所述电路图案或所述半导体芯片的至少一方；绝缘树脂，其使所述连接导体的焊接部露出，并覆盖所述电路图案、所述半导体芯片；外部端子，其使主电流流入所述半导体芯片的主电极；以及外部连接导体，其利用激光焊接分别与该外部端子和所述连接导体的所述焊接部接合。
（2）在所述绝缘树脂上具有上层绝缘树脂，该上层绝缘树脂覆盖所述连接导体的露出部、所述外部端子和所述外部连接导体。
（3）所述半导体芯片除了所述主电极以外，还具有一个或多个信号电极，所述绝缘树脂至少覆盖键合线，该键合线连接所述信号电极和向外部导出的信号端子。
（4）所述连接导体是使所述固定的面和所述焊接部隔开空间存在的弯曲构造。
（5）半导体装置的制造方法包含以下步骤：在形成于绝缘基板上的电路图案上固定半导体芯片的步骤；在所述电路图案或所述半导体芯片的至少一方固定连接导体的步骤；覆盖步骤，使所述连接导体的焊接部露出，并利用绝缘树脂覆盖所述电路图案、所述半导体芯片；在所述覆盖步骤之后，利用激光焊接将外部连接导体分别与使主电流流入所述半导体芯片的主电极的外部端子和所述连接导体的所述焊接部接合的步骤；以及填充步骤，在所述绝缘树脂上填充上层绝缘树脂，该上层绝缘树脂覆盖所述连接导体的露出部、所述外部端子和所述外部连接导体。
（6）所述绝缘树脂是固化性树脂，所述覆盖步骤包含使所述固化性树脂固化的步骤，在所述填充步骤之前，具有去除所述绝缘树脂的表面异物的去除步骤。
（7）所述绝缘树脂和上层绝缘树脂是固化性树脂，在所述填充步骤之后，具有使所述绝缘树脂和所述上层绝缘树脂同时固化的固化步骤。
（8）通过所述绝缘树脂来覆盖与所述半导体芯片的信号电极导通的信号端子的至少一部分或与所述信号端子导通的键合线。
根据本发明，分为两次进行绝缘树脂的填充，第一次的填充为进行激光焊接的下侧部件的上部面的下方，在该状态下进行激光焊接，然后，进一步填充追加的绝缘树脂，由此，即使存在在激光焊接时产生的飞溅物的分散，电路图案或半导体芯片以及键合线等也不会由于该飞溅物而受到物理损伤（瑕疵、破损、切断等），能够防止电气特性的劣化（耐压降低、断线引起的不导通）。
本发明的上述以及其他目的、特征以及优点通过表示作为本发明的例子而优选的实施方式的附图和相关的以下说明而更加清楚。
附图说明
图1是本发明的第1实施例的半导体装置的主要部分剖面图。
图2是示出第1实施例的半导体装置的变形例的主要部分剖面图。
图3是示出第1实施例的半导体装置的又一变形例的主要部分剖面图。
图4是示出图1的半导体装置的制造方法的图，（a）和（b）是按照步骤顺序示出的主要部分制造步骤剖面图。
图5是端子外壳和连接导体的距离大时的A部的结构图，该图（a）是伸长外部端子时的图，该图（b）是使用外部连接导体时的图。
图6是本发明的第2实施例的半导体装置的主要部分剖面图。
图7是本发明的第3实施例的半导体装置的结构图，（a）是主要部分剖面图，（b）是按照（a）的Y-Y线切断的主要部分剖面图。
图8是本发明的第4实施例的半导体装置的主要部分结构图，（a）是主要部分剖面图，（b）是按照（a）的Y-Y线切断的主要部分剖面图，（c）是（a）的B部构造不同的主要部分剖面图，（d）是（a）的C部构造不同的主要部分剖面图。
图9是现有的半导体装置的主要部分剖面图。
图10是示出飞溅物飞散的状况的图。
标号说明
1：铜基体；2、7、13：焊锡；3：背面铜箔；4：陶瓷（绝缘基板）；5、5’、6：电路图案；8：半导体芯片；9：键合线（铝线）；10：端子外壳；11：外部端子；11’：信号端子；12：焊接部；14：连接导体；15：U字型连接导体；17、17a、17b：树脂；19：外部连接导体；20：Ω型连接导体；21：飞溅物；22：衬垫；90、91：键合线；P：上部面。
具体实施方式
利用以下的实施例来说明实施方式。另外，对与现有技术的图9的部位相同的部位标注同一标号。
<实施例1>
图1是本发明的第1实施例的半导体装置的主要部分剖面图。基本构造与图9所示的现有的半导体装置相同，但是，不同之处在于，在电路图案5和外部端子11之间、以及电路图案6和外部端子11之间***连接导体14。
通过焊锡2来接合由陶瓷4（绝缘基板）、形成于该陶瓷4的背侧的背面铜箔3、形成于陶瓷4的表侧的电路图案5和电路图案6构成的绝缘电路基板的背面铜箔3和铜基体1，通过焊锡7来接合电路图案5和半导体芯片8。并且，利用焊锡13来接合块状的连接导体14与电路图案5和电路图案6。基于该焊锡2和焊锡13的接合当然也可以是超声波接合。
接着，利用超声波振动，利用键合线9（铝线等）来连接半导体芯片8上部的未图示的发射极电极和电路图案6。
接着，利用未图示的硅酮系粘接剂将嵌入成型有外部端子11的端子外壳10和铜基体1加热粘接。然后，以连接导体14的上部面P露出、键合线9埋没的方式填充树脂17a（参照图4（a））。
然后，对连接导体14和外部端子11进行点激光焊接。该情况下的激光焊接中的激光的照射位置为外部端子11的上侧。连接导体14选择容易与电路图案接合、容易与外部端子11激光焊接的金属，外部端子11选择容易与连接导体14激光焊接的金属。从向外部流出主电流的观点来看，期望导电性良好，优选铜或铜合金。并且，分别考虑接合性，也可以对表面实施镀镍等。
对外部端子11照射激光，利用焊接部12来焊接外部端子11和连接导体14。由于激光的照射，外部端子11溶融，其一部分作为飞溅物21飞散。飞散的飞溅物21附着于树脂17a上。然后，进一步填充树脂17b作为上层的绝缘树脂（参照图4（b））。所述树脂17a和树脂17b是硅酮凝胶或环氧树脂，两者是相同材质的树脂。树脂17a在激光焊接时可以是液状，也可以是固化的状态。并且，两者的树脂当然也可以是不同的材质。
在填充树脂17b之前，也可以增加去除附着于树脂17a上的飞溅物21的步骤。例如，对树脂17a上吹出空气，去除飞溅物21。在激光照射之前使树脂17a固化时，通过空气等去除飞溅物21是很容易的。
这样制作本发明的半导体装置。飞溅物21附着于树脂17a上，该树脂17a作为掩模，使飞溅物21不会到达电路图案5、电路图案6等或半导体芯片8上以及键合线9，所以，不会对它们造成损伤。
即，在激光焊接时，即使产生飞溅物21并飞散，也能够防止电路图案5、6或半导体芯片8以及键合线9由于该飞溅物21而受到物理损伤（瑕疵、破损、切断等），能够防止电气特性的劣化（耐压降低、断线引起的不导通）。
这里，说明在电路图案5上安装IGBT等的具有一个或多个信号电极的半导体芯片8的变形例。
图2示出第1实施例的半导体装置的变形例。这里，图（a）和图（b）示出步骤顺序的主要部分剖面。
半导体芯片8除了主电极以外，在配置有所述主电极的半导体芯片8的主面还具有一个或多个信号电极。而且，独立于将所述主电极与电路图案6连接而流入主电流的键合线9，连接有将所述信号电极与信号端子11’连接的信号用的键合线90。而且，如图（a）所示，通过树脂17a覆盖与半导体芯片8的信号电极导通的信号端子11’的至少一部分、或者与所述信号端子11’导通的键合线90。
流过主电流的键合线9通常比与信号电极连接的键合线90粗，相对于一个主电极而连接多条。根据流入主电极的电流的大小或每一条键合线9所能够流通的电流的大小，来选择键合线9的粗细和条数。
在与信号电极连接的键合线90中，不会像与主电极连接的键合线9那样流入大电流，并且信号电极小，所以使用细线。
为了防止飞溅物21对键合线的影响，优选所述树脂17a覆盖全部的键合线。
流入主电流的键合线9比与信号电极连接的键合线90粗且刚性大，所以，与和信号电极连接的键合线90相比，难以受到飞溅物21的碰撞的影响。并且，接近的键合线9并列连接多条，所以，即使飞溅物21附着于键合线9，也难以受到短路的影响。
由于线的刚性的差异，键合线9的线圈高度比与信号电极连接的键合线90高，所以，设所述树脂17a的填充高度至少为覆盖与信号电极连接的键合线90的高度。决定所述焊接部12的位置H以便成为该高度时，如图2所示，能够降低半导体装置的高度。并且，能够可靠地保护与信号电极连接的键合线90不受飞溅物21的影响。
如上所述，所述连接导体14利用焊锡13与电路图案5的表面和电路图案6的表面接合。能够在与铜基体1和背面铜箔3的焊锡接合、电路图案5和半导体芯片8的焊锡接合相同的步骤中，实施该连接导体14与电路图案5和电路图案6的焊锡接合。
即，不用新增加焊锡接合步骤，就能够对连接导体14进行焊锡接合。
将连接导体14与绝缘电路基板的电路图案5和电路图案6焊锡接合后，对外部端子11和连接导体14进行点激光焊接。这里使用的连接导体14的厚度为外部端子11的厚度以上，由此，焊接部12不会到达位于连接导体14下方的绝缘电路基板的电路图案5和电路图案6或未图示的电路布线等的电路图案，能够实现基于可靠性高的激光焊接的稳定且牢固的接合。
并且，在包含该信号端子11’的半导体装置的形式中，也可以是图3所示的形式。
图3示出第1实施例的半导体装置的又一变形例。在图3中，示出信号端子11’周边的半导体装置的主要部分剖面图。另外，在图3中没有显示铜基体1。
例如如图（a）所示，在端子外壳10中一体成型（密封）的信号端子11’和半导体芯片8的信号电极通过键合线90直接电连接。
并且，如图（b）所示，在陶瓷4上设置独立于电路图案5的电路图案5’，该电路图案5’和半导体芯片8的信号电极通过键合线90直接电连接。而且，在端子外壳10中一体成型的信号端子11’和电路图案5’通过键合线90电连接。
并且，如图（c）所示，也可以经由焊锡13在电路图案5’中接合信号端子11’。而且，信号端子11’和半导体芯片8的信号电极也可以通过键合线90直接电连接。
也可以是这种半导体装置的形式。
图4是说明图1的半导体装置的制造方法的图，该图（a）、该图（b）是按照步骤顺序示出的主要部分制造步骤剖面图。在所述图1中进行步骤的说明。
在激光焊接之前填充树脂17a，所以，在激光焊接时产生的飞溅物21附着于树脂17a的表面，而不会附着于电路图案5、6或半导体芯片8。因此，防止了电气特性的劣化。并且，然后填充树脂17b，所以，飞溅物21混入树脂17的位置是树脂17a和树脂17b的界面，飞溅物21在该界面中分散存在。
图5是端子外壳和连接导体的距离大时的A部的结构图，该图（a）是伸长外部端子时的图，该图（b）是使用外部连接导体时的图。如图所示，在端子外壳10和连接导体14之间的距离大的情况下，如该图（a）所示使外部端子11伸长到连接导体14即可，或者如该图（b）所示利用外部连接导体19对外部端子11和连接导体14进行搭桥即可。
<实施例2>
图6是本发明的第2实施例的半导体装置的主要部分剖面图。与图1时的差异在于，与外部端子11进行点激光焊接的连接导体的形状为U字型的连接导体15。这里，称为U字型是因为，是将“U”的文字横向放倒后的形状。与电路图案5焊锡接合的面和在焊接部12中焊接的面（P）是通过从电路图案面上升的部分（连接部）而隔开空间连接的形状。连接导体15为U字形状，由此，在激光焊接时，利用位于上侧的外部连接导体（引线框）来压入位于下侧的U字型连接导体15的上部平板部（上部面P），由此，上部平板部弯曲，在激光焊接面中，连接导体15和外部端子11牢固地密接，能够进行良好的激光焊接。
并且，在U字型连接导体15的厚度和它们的材料的表面状态或激光功率产生变动的情况下，在激光焊接时，有时U字型的上部的平板部a溶融，在该焊接部12的中心形成贯通孔。该情况下，激光经由该贯通孔照射到U字型的下侧的平板部b。
但是，在U字型的下侧的平板部b没有结成激光的焦点，所以，激光的能量弱，U字型的下侧的平板部b没有溶融。这样，***U字型连接导体15，由此，能够防止焊接部12到达绝缘电路基板的电路图案5和电路图案6。因此，能够实现基于可靠性高的激光焊接的稳定且牢固的接合。
该情况下，与第1实施例同样，在激光焊接之前，在U字型的上侧的平板部的表面（上部面P）下方，以覆盖键合线9的方式填充树脂17a，在激光焊接结束后，再次在树脂17a上填充树脂17b。这样，防止了在激光焊接时产生的飞溅物21附着于绝缘基板的电路图案（电路图案5或电路图案6或未图示的电路布线图案）或半导体芯片8的表面、或者切断键合线9的情况。
<实施例3>
图7是本发明的第3实施例的半导体装置的结构图，该图（a）是主要部分剖面图，该图（b）是按照该图（a）的Y-Y线切断的主要部分剖面图。与图1和图6时的差异在于，连接导体的形状为Ω型的Ω型连接导体16。称为Ω型是因为，形状与Ω的文字相似。与电路图案5焊锡接合的面和在焊接部12中焊接的面（P）是通过从电路图案面上升的部分（连接部）而隔开空间连接的形状。Ω型连接导体16利用外部端子11和基于激光焊接的焊接部12进行固定。在该激光焊接之前，以位于Ω型连接导体16的上侧的平坦部表面（上部面P）下方的方式填充树脂17a。由此来防止飞溅物21引起的损伤或不良。在激光焊接后，在树脂17a上填充树脂17b。
该Ω型连接导体16通过焊锡13与电路图案5和电路图案6接合。该情况下也同样不焊接薄的电路图案5和电路图案6与厚的外部端子11，而在其间***厚的Ω型连接导体16，由此，与***U字型连接导体的情况相同，能够防止焊接部12到达绝缘电路基板的电路图案5和电路图案6。因此，能够实现基于可靠性高的激光焊接的稳定且牢固的接合。此时的Ω型连接导体16的厚度为外部端子11的厚度以上。
不限于在所述第2、第3实施例中示出的U字型或Ω型，虽然没有图示，但是，在与连接导体14的电路图案或半导体芯片接合的面和激光焊接的面之间设置空间，使该空间位于激光光路的延长线上，由此，能够得到同样的效果。并且，当然也可以切去圆筒或四棱柱的侧壁的一部分而形成未图示的狭缝状的开口部。
或者，当然也可以构成为，切断剖面为□字状的棱状的管，一个面与电路图案5或电路图案6焊锡接合，对置的面与外部端子11进行点激光焊接。
该棱状的管切断长条的管即可，所以，能够低价地准备。并且，剖面为□字状，所以，在激光光路的延长线上存在空隙，能够得到同样的效果。
<实施例4>
图8是本发明的第4实施例的半导体装置的主要部分结构图，该图（a）是主要部分剖面图，该图（b）是按照该图（a）的Y-Y线切断的主要部分剖面图，该图（c）是该图（a）的B部构造不同的主要部分剖面图，该图（d）是该图（a）的C部构造不同的主要部分剖面图。该图是如下情况下的图：利用Ω型连接导体20来连接2个半导体芯片，对该Ω型连接导体20和外部连接导体19（引线框）进行激光焊接。该图（b）示出Ω型连接导体20在2条附近利用焊锡13分别固定2个半导体芯片8（例如IGBT芯片和二极管芯片等）的状态。该图（c）是外部端子11埋入端子外壳10中、与键合线9连接的部位从端子外壳10中露出的情况。通常的外壳构造采用该图（c）这种构造。
并且，Ω型连接导体20利用外部连接导体19（与外部端子11连接的金属板或引线框）和基于激光焊接的焊接部12进行固定。在该激光焊接之前，以位于Ω型连接导体20的上侧的平坦部表面（上部面P）下方的方式填充树脂17a。由此来防止飞溅物21引起的损伤或不良。在激光焊接后，在树脂17a上填充树脂17b。利用键合线9来连接外部端子11和形成于陶瓷4的衬垫22（选通用衬垫等），该键合线9埋没于树脂17a中。
在该图（a）中，利用外部连接导体19来连接Ω型连接导体20和外部端子11，但是，如该图（d）所示，也可以不使用外部连接导体19，使外部端子11伸长到Ω型连接导体20，利用外部端子11直接连接Ω型连接导体20。
另外，作为所述连接导体14、U字型连接导体15、Ω型连接导体16、20以及未图示的棱状的管等的连接导体的材质，可以使用低电阻材料（电传导率大的材料）即铜、铜合金。并且，在所述半导体芯片8的上侧键合有铝线，但是，有时为基于引线框的布线等。
并且，在所述点激光焊接中使用的激光的波长可以是0.19μm～10.6μm。
上述仅示出本发明的原理。进而，对本领域技术人员来说能够进行多个变形、变更，本发明不限于上述示出并说明的准确结构和应用例，对应的全部变形例和等同物也视为基于所附权利要求及其等同物的本发明的范围。

Claims (8)

1.一种半导体装置，其特征在于，该半导体装置具有：
电路图案，其形成于绝缘基板上；
半导体芯片，其固定于所述电路图案上；
连接导体，其固定于所述电路图案或所述半导体芯片的至少一方；
绝缘树脂，其使所述连接导体的焊接部露出，并覆盖所述电路图案、所述半导体芯片；
外部端子，其使主电流流入所述半导体芯片的主电极；以及
外部连接导体，其利用激光焊接分别与该外部端子和所述连接导体的所述焊接部接合。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述绝缘树脂上具有上层绝缘树脂，该上层绝缘树脂覆盖所述连接导体的露出部、所述外部端子和所述外部连接导体。
3.根据权利要求1所述的半导体装置，其特征在于，
所述半导体芯片除了所述主电极以外，还具有一个或多个信号电极，所述绝缘树脂至少覆盖键合线，该键合线连接所述信号电极和向外部导出的信号端子。
4.根据权利要求1所述的半导体装置，其特征在于，
所述连接导体是使所述固定的面和所述焊接部隔开空间存在的弯曲构造。
5.一种半导体装置的制造方法，其特征在于，该半导体装置的制造方法具有以下步骤：
在形成于绝缘基板上的电路图案上固定半导体芯片的步骤；
在所述电路图案或所述半导体芯片的至少一方固定连接导体的步骤；
覆盖步骤，使所述连接导体的焊接部露出，并利用绝缘树脂覆盖所述电路图案、所述半导体芯片；
在所述覆盖步骤之后，利用激光焊接将外部连接导体分别与使主电流流入所述半导体芯片的主电极的外部端子和所述连接导体的所述焊接部接合的步骤；以及
填充步骤，在所述绝缘树脂上填充上层绝缘树脂，该上层绝缘树脂覆盖所述连接导体的露出部、所述外部端子和所述外部连接导体。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述绝缘树脂是固化性树脂，所述覆盖步骤包含使所述固化性树脂固化的步骤，在所述填充步骤之前，具有去除所述绝缘树脂的表面异物的去除步骤。
7.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述绝缘树脂和上层绝缘树脂是固化性树脂，在所述填充步骤之后，具有使所述绝缘树脂和所述上层绝缘树脂同时固化的固化步骤。
8.根据权利要求5所述的半导体装置的制造方法，其特征在于，
通过所述绝缘树脂来覆盖与所述半导体芯片的信号电极导通的信号端子的至少一部分或与所述信号端子导通的键合线。
CN2008801209553A 2007-12-20 2008-12-09 半导体装置及其制造方法 Active CN101933139B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007-328641 2007-12-20
JP2007328641 2007-12-20
PCT/JP2008/072314 WO2009081723A1 (ja) 2007-12-20 2008-12-09 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN101933139A CN101933139A (zh) 2010-12-29
CN101933139B true CN101933139B (zh) 2012-11-07

Family

ID=40801030

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008801209553A Active CN101933139B (zh) 2007-12-20 2008-12-09 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US8710666B2 (zh)
JP (1) JP5183642B2 (zh)
CN (1) CN101933139B (zh)
DE (1) DE112008003425B4 (zh)
WO (1) WO2009081723A1 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5164962B2 (ja) * 2009-11-26 2013-03-21 三菱電機株式会社 電力変換装置
EP2408260A1 (de) * 2010-07-13 2012-01-18 Saint-Gobain Glass France Glasscheibe mit einem elektrischen Anschlusselement
JP5633581B2 (ja) * 2011-01-07 2014-12-03 富士電機株式会社 半導体装置およびその製造方法
FI3576491T3 (en) 2011-05-10 2023-12-11 Saint Gobain PANEL EQUIPPED WITH ELECTRICAL CONNECTION ELEMENT
MY184545A (en) 2011-05-10 2021-04-01 Saint Gobain Pane with an electrical connection element
BR112013028110A2 (pt) 2011-05-10 2017-09-19 Saint Gobain painel com um elemento de conexão elétrica
JP5790196B2 (ja) * 2011-06-23 2015-10-07 富士電機株式会社 半導体装置の製造方法
EP2698817B1 (en) 2011-08-10 2018-10-24 Fuji Electric Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
CN102403419B (zh) * 2011-11-09 2013-08-21 东莞勤上光电股份有限公司 一种大功率led散热结构的制作工艺
FR2986902A1 (fr) * 2012-02-09 2013-08-16 Pixinbio Procede d'assemblage d'un dispositif portable d'analyse d'echantillon biologique
CN102738099A (zh) * 2012-06-05 2012-10-17 嘉兴斯达微电子有限公司 一种新型高可靠功率模块
US9622368B2 (en) * 2012-08-24 2017-04-11 Mitsubishi Electric Corporation Semiconductor device
CN103208473B (zh) * 2012-12-15 2016-01-20 南京银茂微电子制造有限公司 采用激光焊接端子的功率模块
CN103887300A (zh) * 2012-12-20 2014-06-25 浙江大学 具有高可靠性导热绝缘基板的功率igbt模块
CN103887246A (zh) * 2012-12-20 2014-06-25 浙江大学 具有新型接合层的电力电子模块散热结构
CN103035590A (zh) * 2012-12-25 2013-04-10 浙江大学 一种igbt功率模块
JP6028592B2 (ja) * 2013-01-25 2016-11-16 三菱電機株式会社 半導体装置
JP6171586B2 (ja) * 2013-06-04 2017-08-02 富士電機株式会社 半導体装置
JP6398399B2 (ja) * 2013-09-06 2018-10-03 富士電機株式会社 半導体装置およびその製造方法
JP2015119072A (ja) 2013-12-19 2015-06-25 富士電機株式会社 レーザ溶接方法、レーザ溶接治具、半導体装置
CN103785980A (zh) * 2014-01-27 2014-05-14 江苏德丽斯特半导体科技有限公司 大功率晶闸管导电柱和门极线焊接夹具
DE102014219585A1 (de) * 2014-09-26 2016-03-31 Robert Bosch Gmbh Kontaktanordnung mit einem Schaltungsträger und einem Verbindungselement
JP6325975B2 (ja) * 2014-12-19 2018-05-16 新光電気工業株式会社 リードフレーム、半導体装置
CN105990265B (zh) * 2015-02-26 2019-04-05 台达电子工业股份有限公司 功率转换电路的封装模块及其制造方法
CN105047624B (zh) * 2015-07-01 2017-11-24 四川广义微电子股份有限公司 Igbt芯片导热模块及其制备方法
JP6711001B2 (ja) * 2016-02-17 2020-06-17 富士電機株式会社 半導体装置及び製造方法
JP6750394B2 (ja) 2016-08-18 2020-09-02 富士電機株式会社 半導体装置及び半導体装置製造方法
DE102017115879B4 (de) * 2017-07-14 2021-07-22 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines leistungselektronischen Submoduls mittels eines Schweißenverfahrens
JP6987031B2 (ja) * 2018-08-08 2021-12-22 三菱電機株式会社 電力用半導体装置及びその製造方法、並びに、電力変換装置
CN110418518B (zh) * 2019-07-18 2020-12-11 烟台台芯电子科技有限公司 一种提高igbt模块端子焊接强度的工艺方法
JP7280789B2 (ja) 2019-09-24 2023-05-24 株式会社東芝 パワーモジュール
JP6866913B2 (ja) * 2019-10-24 2021-04-28 三菱電機株式会社 半導体装置
JP2021144984A (ja) * 2020-03-10 2021-09-24 富士電機株式会社 製造方法、製造装置、治具アセンブリ、半導体モジュールおよび車両
DE112022000173T5 (de) 2021-06-23 2023-07-20 Fuji Electric Co., Ltd. Halbleitermodul und verfahren zu dessen herstellung
EP4278380A1 (en) * 2022-04-08 2023-11-22 Hitachi Energy Switzerland AG Arrangement for a power module, power module and method for producing an arrangement for a power module
CN115227956A (zh) * 2022-07-26 2022-10-25 空芯微医疗科技(上海)有限责任公司 空心微针的制备方法
WO2024075463A1 (ja) * 2022-10-07 2024-04-11 住友電気工業株式会社 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1237785A (zh) * 1998-06-01 1999-12-08 株式会社日立制作所 半导体器件和半导体器件的制作方法
JP2000068447A (ja) * 1998-08-26 2000-03-03 Toyota Central Res & Dev Lab Inc パワーモジュール
JP2007165690A (ja) * 2005-12-15 2007-06-28 Fuji Electric Holdings Co Ltd ヒートスプレッダと金属板との接合方法

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3747051A (en) * 1970-07-16 1973-07-17 Amp Inc Welding method and means using foil electrode
JPS59181627A (ja) 1983-03-31 1984-10-16 Toshiba Corp 半導体装置の製造方法
US4751199A (en) * 1983-12-06 1988-06-14 Fairchild Semiconductor Corporation Process of forming a compliant lead frame for array-type semiconductor packages
JPS60157243A (ja) 1984-01-25 1985-08-17 Mitsubishi Electric Corp 半導体装置
JPS632360A (ja) * 1986-06-20 1988-01-07 Fujitsu Ltd 回路部品の外部リ−ド接続方法
SG52794A1 (en) * 1990-04-26 1998-09-28 Hitachi Ltd Semiconductor device and method for manufacturing same
JP2816239B2 (ja) * 1990-06-15 1998-10-27 株式会社日立製作所 樹脂封止型半導体装置
JPH0577944A (ja) 1991-09-19 1993-03-30 Canon Inc 手差し給紙装置
JPH0577944U (ja) * 1992-03-24 1993-10-22 シチズン時計株式会社 水晶発振器
JPH0629459A (ja) * 1992-07-08 1994-02-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2721093B2 (ja) * 1992-07-21 1998-03-04 三菱電機株式会社 半導体装置
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
JP3329073B2 (ja) * 1993-06-04 2002-09-30 セイコーエプソン株式会社 半導体装置およびその製造方法
JPH0794845A (ja) 1993-09-20 1995-04-07 Toppan Printing Co Ltd 半導体素子搭載用基板および半導体装置
JPH07147347A (ja) * 1993-11-25 1995-06-06 Matsushita Electric Ind Co Ltd 集積回路装置
US5473190A (en) * 1993-12-14 1995-12-05 Intel Corporation Tab tape
KR0147259B1 (ko) * 1994-10-27 1998-08-01 김광호 적층형 패키지 및 그 제조방법
JP3201187B2 (ja) 1994-12-08 2001-08-20 富士電機株式会社 半導体装置
US5661337A (en) * 1995-11-07 1997-08-26 Vlsi Technology, Inc. Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages
US5844308A (en) * 1997-08-20 1998-12-01 Cts Corporation Integrated circuit anti-bridging leads design
JP3756338B2 (ja) * 1999-03-02 2006-03-15 株式会社ルネサステクノロジ 半導体装置の製造方法
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
JP3406270B2 (ja) * 2000-02-17 2003-05-12 沖電気工業株式会社 半導体装置及びその製造方法
US6368899B1 (en) * 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
NO20011677L (no) * 2000-04-04 2001-10-05 Tokin Corp Elektronisk komponent for demping av höy frekvens og forbindelsesledning for komponenten
US6818968B1 (en) * 2000-10-12 2004-11-16 Altera Corporation Integrated circuit package and process for forming the same
JP3563387B2 (ja) * 2001-01-23 2004-09-08 Ｎｅｃエレクトロニクス株式会社 半導体装置用導電性硬化樹脂及び半導体装置
US6791168B1 (en) * 2002-07-10 2004-09-14 Micron Technology, Inc. Semiconductor package with circuit side polymer layer and wafer level fabrication method
JP4078993B2 (ja) * 2003-01-27 2008-04-23 三菱電機株式会社 半導体装置
TWI244173B (en) * 2003-11-12 2005-11-21 Optimum Care Int Tech Inc Semiconductor chip package structure
US6972372B1 (en) * 2004-05-28 2005-12-06 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using outer lead portions and exposed inner lead portions to provide interconnection
DE102004058305B3 (de) * 2004-12-02 2006-05-18 Infineon Technologies Ag Halbleiterbauteil mit einem eine Passivierungsschicht aufweisenden Halbleiterchip sowie Verfahren zur Herstellung desselben
DE102005037321B4 (de) * 2005-08-04 2013-08-01 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauteilen mit Leiterbahnen zwischen Halbleiterchips und einem Schaltungsträger
TWI284407B (en) * 2005-11-03 2007-07-21 Cyntec Co Ltd Package device with electromagnetic interference shield
JP4335203B2 (ja) 2005-11-30 2009-09-30 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4842118B2 (ja) 2006-01-24 2011-12-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7298038B2 (en) * 2006-02-25 2007-11-20 Stats Chippac Ltd. Integrated circuit package system including die stacking
US8004075B2 (en) * 2006-04-25 2011-08-23 Hitachi, Ltd. Semiconductor power module including epoxy resin coating
JP5103863B2 (ja) * 2006-10-16 2012-12-19 富士電機株式会社 半導体装置
JP2008227131A (ja) * 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置及びその製造方法
US7868471B2 (en) * 2007-09-13 2011-01-11 Stats Chippac Ltd. Integrated circuit package-in-package system with leads
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1237785A (zh) * 1998-06-01 1999-12-08 株式会社日立制作所 半导体器件和半导体器件的制作方法
JP2000068447A (ja) * 1998-08-26 2000-03-03 Toyota Central Res & Dev Lab Inc パワーモジュール
JP2007165690A (ja) * 2005-12-15 2007-06-28 Fuji Electric Holdings Co Ltd ヒートスプレッダと金属板との接合方法

Also Published As

Publication number Publication date
DE112008003425T5 (de) 2010-10-28
CN101933139A (zh) 2010-12-29
DE112008003425B4 (de) 2023-08-31
US20100295187A1 (en) 2010-11-25
JP5183642B2 (ja) 2013-04-17
US8710666B2 (en) 2014-04-29
JPWO2009081723A1 (ja) 2011-05-06
WO2009081723A1 (ja) 2009-07-02

Similar Documents

Publication Publication Date Title
CN101933139B (zh) 半导体装置及其制造方法
US7772031B2 (en) Semiconductor apparatus manufacturing method
JP5176507B2 (ja) 半導体装置
US7884455B2 (en) Semiconductor device
US20160005675A1 (en) Double sided cooling chip package and method of manufacturing the same
JP4614586B2 (ja) 混成集積回路装置の製造方法
CN108364918A (zh) 薄轮廓引线半导体封装
JP5292779B2 (ja) 半導体装置
CN105575825A (zh) 芯片封装方法及封装组件
CN104380460A (zh) 基台和密封完毕的半导体元件以及它们的制作方法
KR20100064629A (ko) 외부 본딩 영역을 구비하는 반도체 파워 모듈 패키지
US20120306064A1 (en) Chip package
JP2005167075A (ja) 半導体装置
US11211373B1 (en) Double-sided chip stack assembly
CN102315135A (zh) 芯片封装及其制作工艺
JP2010287726A (ja) 半導体装置
JP2010141163A (ja) 半導体装置及び半導体装置の製造方法
KR20000033885A (ko) 금속 터미널을 구비하는 전력 반도체 모쥴, 전력 반도체 모쥴의금속 터미널 제조방법 및 전력 반도체 모쥴의 제조방법
CN101521164B (zh) 引线键合芯片级封装方法
JP2009224529A (ja) 半導体装置およびその製造方法
CN114981940A (zh) 在坚固的封装衬底中具有分割裸片垫的经封装电子装置
JP2002118191A (ja) 半導体装置およびその製造方法
JP5359135B2 (ja) 発光装置
US20140021640A1 (en) Method for electrically connecting vertically positioned substrates
JP2013034022A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant