JP6750394B2 - 半導体装置及び半導体装置製造方法 - Google Patents
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Description
特許文献1 特開2015−198227号公報
特許文献2 国際公開第2009/081723号
特許文献3 特開2011−77280号公報
特許文献4 国際公開第2013/146212号
Claims (19)
- それぞれが半導体素子(12,13)、前記半導体素子(12,13)を封止するユニット筐体(11)、および前記ユニット筐体(11)の上面に設けられた第1凹部(11a)内に露出する第1ユニット端子(16)を有する複数の半導体ユニット(20A〜20C)と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して前記第1ユニット端子(16)に接続される第1接続端子(43S)、複数の前記第1接続端子(43S)間を接続する第1接続導体(43S0)、および、前記第1接続導体(43S0)を封止し前記複数の第1接続端子(43S)を露出させる第1接続導体封止部(40a0)を有する第1ユニット接続部(40a)と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して、前記第1凹部(11a)の凹み内において、前記第1ユニット端子(16)および前記第1接続端子(43S)の間の接続部をそれぞれ封止する複数の第1凹み封止部(45a)と、
を備える半導体装置。 - 前記第1接続導体封止部(40a0)は、前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して、前記第1凹部(11a)の内部に向かって突出して前記第1接続導体(43S0)における前記第1接続端子(43S)への延伸部分を封止する第1突出部(41a0)を有し、
前記複数の第1凹み封止部(45a)のそれぞれは、前記第1ユニット接続部(40a)における対応する前記第1接続端子(43S)から前記第1突出部(41a0)に至る部分を封止する
請求項1に記載の半導体装置。 - 前記第1ユニット接続部(40a)は、前記複数の半導体ユニット(20A〜20C)のそれぞれに対応する前記第1接続端子(43S)が、上面視において、前記第1接続導体(43S0)および前記第1接続導体封止部(40a0)によって少なくとも一部が隠蔽されない位置に設けられる請求項1または2に記載の半導体装置。
- 前記第1接続端子(43S)は、前記第1接続導体(43S0)および前記第1接続導体封止部(40a0)から離れた端部を有する請求項3に記載の半導体装置。
- 前記第1接続導体封止部(40a0)は、上面視において前記複数の半導体ユニット(20A〜20C)のそれぞれに対応する前記第1接続端子(43S)に対応する位置に、前記第1接続端子(43S)の少なくとも一部を露出させるための第1貫通孔(41a)を有する請求項3または4に記載の半導体装置。
- 前記複数の第1接続端子(43S)に対応する複数の前記第1貫通孔(41a)の上側をそれぞれ覆う複数の第1蓋部(46a)を更に備える請求項5に記載の半導体装置。
- 前記複数の半導体ユニット(20A〜20C)のそれぞれは、前記ユニット筐体(11)の上面に設けられた第2凹部(11b)内に露出する第2ユニット端子(17)を更に有し、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して前記第2ユニット端子(17)に接続される第2接続端子(43D)、複数の前記第2接続端子(43D)間を接続する第2接続導体(43D0)、および、前記第2接続導体(43D0)を封止し前記複数の第2接続端子(43D)を露出させる第2接続導体封止部(40b0)を有する第2ユニット接続部(40b)と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して、前記第2凹部(11b)の凹み内において、前記第2ユニット端子(17)および前記第2接続端子(43D)の間の接続部をそれぞれ封止する複数の第2凹み封止部(45b)と、
を備える請求項1から6のいずれか一項に記載の半導体装置。 - 前記複数の半導体ユニット(20A〜20C)のそれぞれは、前記ユニット筐体(11)の上面に設けられた第3凹部(11c)内に露出する第3ユニット端子(18)を更に有し、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して前記第3ユニット端子(18)に接続される第3接続端子(43T)、複数の前記第3接続端子(43T)間を接続する第3接続導体(43T0)、および、前記第3接続導体(43T0)を封止し前記複数の第3接続端子(43T)を露出させる第3接続導体封止部(40c0)を有する第3ユニット接続部(40c)と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して、前記第3凹部(11c)の凹み内において、前記第3ユニット端子(18)および前記第3接続端子(43T)の間の接続部をそれぞれ封止する複数の第3凹み封止部(45c)と、
を備える請求項7に記載の半導体装置。 - 前記複数の半導体ユニット(20A〜20C)のそれぞれは、前記第3凹部(11c)内に露出する第4ユニット端子(19)を更に有し、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して前記第4ユニット端子(19)に接続される第4接続端子(43G)、複数の前記第4接続端子(43G)間を接続する第4接続導体(43G0)、および、前記第4接続導体(43G0)を封止し前記複数の第4接続端子(43G)を露出させる第4接続導体封止部(40d0)を有する第4ユニット接続部(40d)と、
を更に備え、
前記複数の第3凹み封止部(45c)のそれぞれは、前記第3凹部(11c)の凹み内において、前記第3ユニット端子(18)および前記第3接続端子(43T)の間の接続部と前記第4ユニット端子(19)および前記第4接続端子(43G)の間の接続部とを封止する
請求項8に記載の半導体装置。 - 前記第1接続導体封止部(40a0)、前記第2接続導体封止部(40b0)、前記第3接続導体封止部(40c0)、および、前記第4接続導体封止部(40d0)のうちの少なくとも2つの接続導体封止部は、一体に形成される請求項9に記載の半導体装置。
- 前記第1接続導体(43S0)、前記第2接続導体(43D0)、前記第3接続導体(43T0)、および前記第4接続導体(43G0)のうち前記少なくとも2つの接続導体封止部に対応する少なくとも2つの接続導体は、上面視において、一体に形成された前記少なくとも2つの接続導体封止部の内部で少なくとも一部が重ねて配置される請求項10に記載の半導体装置。
- 前記複数の半導体ユニット(20A〜20C)のそれぞれは、前記第1凹部(11a)内に露出する互いに同電位の2以上の前記第1ユニット端子(16)を有する請求項1から11のいずれか一項に記載の半導体装置。
- 前記複数の半導体ユニット(20A〜20C)のそれぞれは、絶縁板(10a)の上面および下面に金属板(10b、10c)が貼り付けられ、上面側の前記金属板(10b)に前記半導体素子(12,13)が搭載される基板(10)を有し、
前記複数の半導体ユニット(20A〜20C)のそれぞれにおける前記基板(10)の下面の前記金属板(10c)に接する導体ベース(30)を更に備える請求項1から12のいずれか一項に記載の半導体装置。 - それぞれが半導体素子(12,13)、前記半導体素子(12,13)を封止するユニット筐体(11)、および前記ユニット筐体(11)の上面に設けられた第1凹部(11a)内に露出する第1ユニット端子(16)を有する複数の半導体ユニット(20A〜20C)を製造する段階と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して前記第1ユニット端子(16)に接続される第1接続端子(43S)、複数の前記第1接続端子(43S)間を接続する第1接続導体(43S0)、および、前記第1接続導体(43S0)を封止し前記複数の第1接続端子(43S)を露出させる第1接続導体封止部(40a0)を有する第1ユニット接続部(40a)を製造する段階と、
前記複数の半導体ユニット(20A〜20C)のそれぞれについて、前記第1凹部(11a)の凹み内において、前記第1ユニット端子(16)および前記第1接続端子(43S)を接続する段階と、
前記複数の半導体ユニット(20A〜20C)のそれぞれに対応して、前記第1凹部(11a)の凹み内において、前記第1ユニット端子(16)および前記第1接続端子(43S)の間の接続部をそれぞれ封止することにより複数の第1凹み封止部(45a)を形成する段階と、
を備える半導体装置製造方法。 - 前記第1ユニット接続部(40a)を製造する段階は、前記第1接続導体封止部(40a0)に、上面視において前記第1接続端子(43S)に対応する位置に、前記第1接続端子(43S)の少なくとも一部を露出させるための第1貫通孔(41a)を設ける段階を含む請求項14に記載の半導体装置製造方法。
- 前記第1接続端子(43S)を接続する段階は、前記第1ユニット端子(16)および前記第1接続端子(43S)を、前記第1貫通孔(41a)を介して接続処理する段階を含む請求項15に記載の半導体装置製造方法。
- 前記複数の第1凹み封止部(45a)を形成する段階は、前記第1貫通孔(41a)を介して前記第1凹部(11a)の凹み内に樹脂を充填する段階を含む請求項15又は16に記載の半導体装置製造方法。
- 前記第1貫通孔(41a)の上側を第1蓋部(46a)により覆う段階を更に備える請求項15から17のいずれか一項に記載の半導体装置製造方法。
- 前記複数の半導体ユニット(20A〜20C)のそれぞれは、絶縁板(10a)の上面および下面に金属板(10b、10c)が貼り付けられ、上面側の前記金属板(10b)に前記半導体素子(12,13)が搭載される基板(10)を更に有し、
前記複数の半導体ユニット(20A〜20C)を、導体ベース(30)上に、前記基板(10)の下面の前記金属板(10c)に接して搭載する段階を更に備える請求項14から18のいずれか一項に記載の半導体装置製造方法。
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