WO2014063414A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2014063414A1
WO2014063414A1 PCT/CN2012/086581 CN2012086581W WO2014063414A1 WO 2014063414 A1 WO2014063414 A1 WO 2014063414A1 CN 2012086581 W CN2012086581 W CN 2012086581W WO 2014063414 A1 WO2014063414 A1 WO 2014063414A1
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film
passivation layer
layer
insulating layer
oxide film
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PCT/CN2012/086581
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English (en)
French (fr)
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袁广才
李禹奉
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京东方科技集团股份有限公司
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Publication of WO2014063414A1 publication Critical patent/WO2014063414A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Oxide TFT is a kind of thin film transistor (TFT) with metal oxide semiconductor as active layer. It has the advantages of ultra-thin, low power consumption, etc. It can be used not only for the manufacture of liquid crystal display panels, but also for In the new generation of organic light-emitting display panel OLED (Organic Light-Emitting Diode).
  • OLED Organic Light-Emitting Diode
  • FIGS. 2A to 2M are cross-sectional views showing a manufacturing process of an Oxide TFT array substrate.
  • S101 ⁇ forms a gate metal film on the substrate.
  • a gate metal film 13 is formed on the substrate 12.
  • the gate metal film is mostly prepared by magnetron sputtering, and the material can be selected according to different device structures and process requirements.
  • the substrate 12 may be a transparent substrate based on an inorganic material such as a glass substrate or a quartz substrate, or may be a transparent substrate made of an organic flexible material.
  • S102 ⁇ patterns the gate metal film to form gate lines and gates.
  • the gate metal film 13 is patterned by wet etching to obtain a gate line (not shown), a gate electrode 13a and a common electrode line 13b. It is also possible to make a common electrode line depending on the specific design.
  • a gate is formed on a substrate with a gate pattern by a Pre-clean process (pre-film cleaning) or plasma enhanced chemical vapor deposition (PECVD) process.
  • Pre-clean process pre-film cleaning
  • PECVD plasma enhanced chemical vapor deposition
  • Oxide TFT fabrication is the most critical The link is the fabrication of an oxide semiconductor film.
  • Oxide semiconductors that are widely used today include indium gallium oxide (IGZO), indium gallium tin oxide (IGTO), indium oxide (IZO), and the like, and other complex ratios thereof.
  • the main methods of fabrication include magnetron sputtering (Sputter) and solution methods.
  • the oxide semiconductor film is patterned to obtain a pattern of the active layer 15a.
  • the active layer oxide semiconductor patterning process There are two main etching processes for the active layer oxide semiconductor patterning process, one is wet etching and the other is dry etching, but different methods will cause oxide semiconductor layers. Different injuries.
  • an Etch Stop Layer (ESL) 16 is formed for the purpose of reducing damage to the active layer formed by the oxide semiconductor during subsequent patterning of the data lines.
  • ESL Etch Stop Layer
  • patterning is performed to form the etch barrier layer 16a as shown in Fig. 2G.
  • a source/drain metal layer 17 is deposited, and then patterned by wet etching to form a source as shown in FIG. 17b, a drain 17a and a data line (not shown) formed integrally with the source 17b.
  • the source/drain metal layer is patterned to form a source, a drain, and a power supply line integrally formed or connected to the source.
  • a passivation layer 18 is formed over the entire surface.
  • the via hole is etched to form a via hole of 1% for realizing the connection of the drain electrode 17a to the pixel electrode, as shown in Fig. 2K.
  • a via hole may be formed above the source electrode 17b for connecting the source electrode 17b and the signal access terminal, for example, a data line or a power supply line which is formed separately from the source electrode 17b.
  • the pixel electrode layer 20 is formed, the material of which is now usually indium tin oxide (ITO), and patterned by wet etching to form the pixel electrode 20a. And the contact electrode 20b, as shown in Fig. 2M.
  • ITO indium tin oxide
  • the passivation layer is prevented from being doped with a hydrogen-containing group such as ruthenium-, H+, and hydrogen-absorbing elements.
  • H-containing groups are prone to breakage during the fabrication of the device and in the state in which the device is in operation, and are likely to diffuse into the oxide semiconductor layer over time and environmental changes.
  • the diffused ⁇ -, H 2 0, H+ and other substances will affect the stability of the device, causing a large drift in the threshold voltage (Vth) of the oxide thin film transistor device, and may even cause product failure.
  • Vth threshold voltage
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device to overcome the defects that the hydrogen group doped in the existing array substrate easily breaks the stability of the device, resulting in a product yield.
  • An aspect of the invention provides an array substrate including a substrate and a thin film transistor and a pixel electrode formed on the substrate, the thin film transistor including a gate, a gate insulating layer, an active layer, and a source and a drain, Further, a passivation layer is overlaid on the thin film transistor; an active layer of the thin film transistor is an oxide semiconductor; and the passivation layer includes at least one inorganic insulating film or an organic insulating film.
  • the passivation layer is a layer including a first passivation layer; the first passivation layer is an inorganic insulating layer or an organic insulating layer; and the inorganic insulating layer includes a silicon dioxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, a barium titanate film or a hafnium oxide film; the organic insulating layer comprises a resin-based insulating film or an acrylic insulating film .
  • the first passivation layer when the first passivation layer is an inorganic insulating layer, the first passivation layer has a thickness of 50 nm to 500 nm; when the first passivation layer is an organic insulating layer, the first blunt The thickness of the layer is 0.5 ⁇ 2.5 ⁇ tude
  • the first passivation layer is a passivation layer treated by an annealing process.
  • the passivation layer is two layers, including a first passivation layer and a second passivation layer; the first passivation layer is adjacent to the thin film transistor; the first passivation layer is a first inorganic insulating layer comprising a silicon oxide film, an aluminum oxide film, a tantalum trioxide film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film or a silicon oxynitride film;
  • the second passivation layer is a second inorganic insulating layer or a first organic insulating layer; the second inorganic insulating layer includes a silicon nitride film, a tantalum trioxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate film or a hafnium oxide film; the first organic insulating layer comprises a resin-based insulating film or an acrylic
  • the first passivation layer has a thickness of 50 nm to 600 nm.
  • the second passivation layer when the second passivation layer is an inorganic insulating layer, the second passivation layer has a thickness of 50 nm to 500 nm;
  • the thickness of the second passivation layer is 0.5 ⁇ 2.5 ⁇
  • the first passivation layer and the second passivation layer are both passivation layers processed by an annealing process.
  • the passivation layer is three layers, including a first passivation layer, a second passivation layer, and a third passivation layer disposed in sequence; the first passivation layer is adjacent to the thin film transistor
  • the first passivation layer is a first inorganic insulating layer; the first inorganic insulating layer comprises a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate a thin film or a hafnium oxide film;
  • the second passivation layer is a second inorganic insulating layer or a first organic insulating layer; the second inorganic insulating layer comprises a silicon oxynitride film, an aluminum oxynitride film, a zirconium oxynitride film, and a nitrogen a ruthenium oxide film or a ruthenium oxynitride film; the first organic
  • the first passivation layer has a thickness of 50 nm to 600 nm; when the second passivation layer is an inorganic insulating layer, the second passivation layer has a thickness of 50 nm 650 nm; When the layer is an organic insulating layer, the thickness of the second passivation layer is 0.5 ⁇ ! When the third passivation layer is an inorganic insulating layer, the third passivation layer has a thickness of 50 ⁇ to 500 ⁇ ; and when the third passivation layer is an organic insulating layer, The thickness of the second passivation layer is 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • the passivation layer is four layers, including a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer disposed in sequence;
  • the layer is adjacent to the thin film transistor;
  • the first passivation layer is a first inorganic insulating layer, and the first inorganic insulating layer comprises a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconium oxide film, and an oxidation Bismuth film, barium titanate film, hafnium oxide film, aluminum oxynitride film, zirconium oxynitride film, hafnium oxynitride film or a ruthenium oxynitride film;
  • the second passivation layer is a second inorganic insulating layer, and the second inorganic insulating layer comprises an aluminum oxynitride film, a zirconium oxynitride film,
  • the first passivation layer has a thickness of 50 nm to 600 nm; the second passivation layer has a thickness of 50 nm to 650 nm; and the third passivation layer has a thickness of 50 nm to 500 nm;
  • the thickness of the layer is 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • the passivation layer is five layers, including a first passivation layer, a second passivation layer, a third passivation layer, a fourth passivation layer, and a fifth passivation layer disposed in sequence;
  • the first passivation layer is adjacent to the thin film transistor;
  • the first passivation layer is a first inorganic insulating layer, and the first inorganic insulating layer comprises a silicon oxide film, an aluminum oxide film, a titanium oxide film, and oxynitride a silicon film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film;
  • the second passivation layer is a second An inorganic insulating layer, the second inorganic insulating layer comprises an aluminum oxyn
  • the first passivation layer has a thickness of 50 nm to 600 nm
  • the second passivation layer has a thickness of 50 nm to 650 nm
  • the third passivation layer has a thickness of 50 nm to 500 nm
  • the thickness of the layer is 0.5 ⁇ ! ⁇ 2.5 ⁇
  • the fifth passivation layer has a thickness of 20 nm to 450 nm.
  • the gate insulating layer is located between the active layer and the gate; the gate insulating layer includes at least one inorganic insulating film.
  • the gate insulating layer is a layer and is a first gate insulating layer; the first gate insulating layer is a silicon oxide film, a tantalum trioxide film, an aluminum oxide film, a titanium oxide film, a zirconia film.
  • yttria film barium titanate film, yttria film, aluminum oxynitride film, silicon oxynitride film, nitrogen A zirconia film, a ruthenium oxynitride film, a ruthenium oxynitride film, a ruthenium oxynitride film, a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film.
  • the first gate insulating layer is an insulating layer processed by an annealing process.
  • the first gate insulating layer has a thickness of 50 nm to 500 nm.
  • the gate insulating layer is two layers, including a first gate insulating layer and a second gate insulating layer; the first gate insulating layer is adjacent to the gate, and the second gate insulating layer is adjacent to the
  • the first gate insulating layer is an aluminum oxynitride film, a silicon oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a silicon nitride film, and a nitride film.
  • An aluminum thin film, a zirconium nitride thin film or a tantalum nitride thin film; the second gate insulating layer is a silicon oxide film, a tantalum trioxide film, an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, a titanic acid
  • the first gate insulating layer is an insulating layer processed by an annealing process
  • the second gate insulating layer is an insulating layer processed by an annealing process
  • the first gate insulating layer has a thickness of 50 nm to 600 nm; and the second gate insulating layer has a thickness of 50 nm to 650 nm.
  • the gate insulating layer is three layers, including a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer; the first gate insulating layer is adjacent to the gate, and the third The insulating layer is adjacent to the active layer, and the second gate insulating layer is located between the first gate insulating layer and the third gate insulating layer; the first gate insulating layer is an aluminum oxynitride film, a silicon oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film; the second gate insulating layer is nitrogen An aluminum oxide film, a silicon oxynitride film, a zirconium
  • the first gate insulating layer has a thickness of 50 nm to 600 nm; the second gate insulating layer has a thickness of 50 nm to 650 ⁇ ; and the third gate insulating layer has a thickness of 20 nm to 600 nm.
  • the gate and/or the source and drain are copper electrodes or copper alloy electrodes.
  • the present invention provides a method for fabricating an array substrate, comprising: fabricating a passivation layer In the step, the passivation layer includes at least one inorganic insulating film or an organic insulating film.
  • the passivation layer is a layer, which is a first passivation layer
  • the method for fabricating the passivation layer may include:
  • Step S11 forming a first passivation layer with an inorganic insulating material or an organic insulating material; and step S12, performing an annealing process on the first passivation layer.
  • the annealing process is: adding a nitrogen or air heating chamber to the PECVD apparatus to dehydrogenate the first passivation layer; wherein, the annealing chamber temperature is 200 ° C to 350 ° C, and the annealing time is 15min ⁇ 90min.
  • the passivation layer is two layers, including a first passivation layer and a second passivation layer; the first passivation layer is adjacent to the thin film transistor;
  • the method includes the following steps: Step S21: forming a first passivation layer with an inorganic insulating material;
  • Step S22 performing an annealing process on the first passivation layer
  • Step S23 forming a second passivation layer by using an inorganic insulating material or an organic insulating material; Step S24, performing an annealing process on the second passivation layer.
  • the annealing process is: adding a heating chamber of nitrogen or air to the PECVD apparatus, respectively performing a dehydrogenation process on the first passivation layer and the second passivation layer; wherein, the annealing chamber temperature is 200 ° C. 350 ° C, annealing time is 15min ⁇ 90min.
  • the passivation layer is three layers, including a first passivation layer, a second passivation layer, and a third passivation layer disposed in sequence; wherein the first passivation layer is close to the a thin film transistor; the method for fabricating the passivation layer includes:
  • Step S31 forming a first passivation layer with an inorganic insulating material
  • Step S32 forming a second passivation layer with an inorganic insulating material or an organic material
  • Step S33 forming a third passivation layer with an inorganic insulating material or an organic material.
  • the passivation layer is four layers, including a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer, which are sequentially disposed, wherein the first blunt layer The layer is adjacent to the thin film transistor; the method for fabricating the passivation layer includes:
  • Step S41 forming a first passivation layer with an inorganic insulating material
  • Step S42 forming a second passivation layer with an inorganic insulating material
  • Step S43 forming a third passivation layer with an inorganic insulating material
  • Step S44 forming a fourth passivation layer with an organic insulating material.
  • the passivation layer is five layers, including a first passivation layer, a second passivation layer, a third passivation layer, a fourth passivation layer, and a fifth passivation layer;
  • the first passivation layer is adjacent to the thin film transistor;
  • the method for fabricating the passivation layer includes:
  • Step S51 forming a first passivation layer with an inorganic insulating material
  • Step S52 forming a second passivation layer with an inorganic insulating material
  • Step S53 forming a third passivation layer with an inorganic insulating material
  • Step S54 forming a fourth passivation layer with an organic insulating material
  • Step S55 forming a fifth passivation layer with an inorganic insulating material.
  • the present invention also provides a display device comprising the above array substrate.
  • the array substrate provided by the embodiment of the invention, the manufacturing method thereof, and the display device, wherein the gate insulating layer and the passivation layer in the array substrate are combined with an annealing process and a layered structure to maximize the passivation layer
  • the hydrogen-containing groups in the external environment can effectively avoid the influence of hydrogen groups on the oxide semiconductor, maximize the stability of the entire TFT device, and improve the yield of the final product.
  • FIGS. 2A-2M are first to thirteenth views respectively showing an oxide thin film transistor array substrate in the prior art
  • FIG. 3 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a third array substrate according to an embodiment of the present invention.
  • FIG. 6 is another schematic diagram of a structure of a third array substrate according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for fabricating a three-array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic structural view of a fifth array substrate according to an embodiment of the present invention.
  • FIG. 9 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural view of an array substrate according to Embodiment 7 of the present invention.
  • 11 is a flowchart of a method for fabricating an array substrate according to Embodiment 7 of the present invention
  • 12 is a schematic structural view of an array substrate according to Embodiment 9 of the present invention
  • FIG. 13 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention. detailed description
  • the array substrate of the embodiment of the present invention includes, for example, a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in an array; each of the pixel units may include a thin film transistor as a switching element And pixel electrodes.
  • the gate of the thin film transistor of each pixel unit is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • the array substrate provided in this embodiment is that the gate layer of the thin film transistor is located on the bottom layer.
  • Array substrate structure (ie bottom gate type).
  • the array substrate includes a gate electrode 402 on the substrate 401, a gate insulating layer 403 and an active layer 404, a source/drain electrode layer 406, a pixel electrode layer 412, and a passivation layer respectively on the gate electrode 402.
  • the gate insulating layer 403 is located between the gate electrode 402 and the active layer 404; the passivation layer is located between the source/drain electrode layer 406 and the pixel electrode layer 412.
  • the source and drain electrode layer 406 includes patterned source, drain, and data lines (or power lines).
  • the passivation layer is located between the source/drain electrode layer 406 and the pixel electrode layer 412, the complex of hydrogen element and hydrogen in the passivation layer and the hydrogen element and hydrogen present in the external environment are easily passed through the source and drain electrodes.
  • the intervening channel structure penetrates into the active layer of the oxide semiconductor, which will have a certain negative impact on the performance of the oxide semiconductor, thereby affecting the performance of the entire device. Therefore, the present embodiment optimizes the structure, material, and fabrication process of the passivation layer to minimize the hydrogen element, the hydrogen complex in the passivation layer, and the complex pair of hydrogen and hydrogen from the external environment. The impact of the entire device, which in turn improves the stability and safety of the entire device.
  • the active layer 404 is an oxide semiconductor, and the gate and/or source/drain electrodes are copper, a copper alloy, or any one of aluminum, chromium, phase, titanium, tantalum, and manganese, and an alloy and a laminated structure of the above metals.
  • the source and drain electrodes include a source and a drain of a thin film transistor.
  • the passivation layer is a single layer structure including a first passivation layer 407.
  • the first passivation layer 407 may be an inorganic insulating layer, including a silicon dioxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a titanium oxide film, a zirconia film, a hafnium oxide film, a barium titanate film or A film layer of an inorganic insulating material such as a ruthenium oxide film.
  • the first passivation layer 407 made of an inorganic insulating material may have a thickness of 50 ⁇ to 500 ⁇ .
  • the thickness of the first passivation layer 407 is 50 nm to 500 nm, the effect of the hydrogen-containing group on the oxide semiconductor can be effectively avoided, and the preparation of the first passivation layer can be completed in a short time. That is to ensure production efficiency. If the thickness of the first passivation layer 407 is too thin, the effect of avoiding the influence of the hydrogen-containing group on the oxide semiconductor is not obtained; and if the thickness of the first passivation layer is too thick, a longer film formation time is required. (tact time), resulting in a decline in production efficiency.
  • the first passivation layer 407 may be an organic insulating layer, and includes a film layer of an organic insulating material such as a resin-based insulating film or an acryl-based insulating film.
  • the first passivation layer made of an organic insulating material may have a thickness of 0.5 ⁇ m! ⁇ 2.5 ⁇ .
  • the thickness of the first passivation layer 407 is 0.5 ⁇ !
  • the temperature is ⁇ 2.5 ⁇
  • the effect of the hydrogen-containing group on the oxide semiconductor can be effectively avoided, and the first passivation layer can be completed in a short time.
  • the first passivation layer 407 may be subjected to an annealing process (ie, the first passivation layer 407 is a passivation layer treated by an annealing process) to reduce hydrogen in the passivation layer.
  • an annealing process ie, the first passivation layer 407 is a passivation layer treated by an annealing process
  • the first passivation layer 407 can be made of a silicon dioxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a titanium oxide film, a zirconia film, a hafnium oxide film, or a titanic acid.
  • a film formed of an insulating material may be used.
  • a film formed of a resin-based insulating film or an acrylic material may be used.
  • the passivation layer can be prepared by using an inorganic material without considering the flexibility requirements of the device; since the organic material itself has good flexibility, If the device to be processed needs to emphasize flexibility, the passivation layer can be prepared using an organic material.
  • the structure of the gate insulating layer 403 in this embodiment may be one layer, two layers or three layers.
  • the first gate insulating layer is formed of a layer structure, it is referred to as a first gate insulating layer.
  • the first gate insulating layer is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film or a titanium oxide film.
  • the first gate insulating layer may have a thickness of 50 nm to 500 nm.
  • the first gate insulating layer may be made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film or a titanium oxide film, and may also be used in combination with the above substances.
  • the first gate insulating layer may be annealed (ie, the first gate insulating layer is an insulating layer treated by an annealing process) to reduce hydrogen in the gate insulating layer.
  • the first gate insulating layer is an insulating layer treated by an annealing process
  • the first gate insulating layer and the second gate insulating layer are included.
  • the first gate insulating layer is adjacent to the gate
  • the second gate insulating layer is adjacent to the active layer
  • the first gate insulating layer may be a silicon nitride film or a silicon oxynitride film
  • the second gate insulating layer may be a silicon oxide film Trioxide Tantalum film or silicon oxynitride film.
  • the first gate insulating layer may have a thickness of 50 nm to 600 nm
  • the second gate insulating layer may have a thickness of 50 nm to 650 nm.
  • the first gate insulating layer may be a thin film formed of a silicon nitride film or a silicon oxynitride material.
  • the second gate insulating layer may be a film formed of a silicon oxide film, a tantalum oxide film or an organic insulating material.
  • the first gate insulating layer may be annealed (ie, the first gate insulating layer is an insulating layer treated by an annealing process) to reduce the gate insulating layer.
  • the second gate insulating layer may be subjected to an annealing process. Badness produced.
  • the function of the second gate insulating layer is that the matching with the oxide semiconductor can be well achieved, thereby improving the performance of the device.
  • the material of the second gate insulating layer is mostly an oxide insulating layer, the ability to prevent diffusion of groups such as ⁇ + , ⁇ ⁇ is relatively poor, so when the first gate insulating layer is formed, it is preferably An annealing process is performed to reduce H + , Off and the like which may occur in the first gate insulating layer, and the stability of the device is improved.
  • the first gate insulating layer When the gate insulating layer is formed in a three-layer structure, the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer are included.
  • the first gate insulating layer is adjacent to the gate, and the third gate insulating layer is adjacent to the active layer.
  • the second gate insulating layer is located between the first gate insulating layer and the third gate insulating layer.
  • the first gate insulating layer may be an inorganic insulating film such as a silicon nitride film or a silicon oxynitride film; the second gate insulating layer may be an inorganic insulating film such as a silicon oxynitride film; and the third insulating insulating layer may be a silicon oxide film.
  • An inorganic insulating film such as an aluminum oxide film or a titanium oxide film.
  • the thickness of the first gate insulating layer may be 50 nm to 600 nm; the thickness of the second gate insulating layer may be 50 nm to 650 nm; and the thickness of the third gate insulating layer may be 20 nm to 600 nm.
  • the gate electrode may be copper or a copper alloy, or may be an electrode of Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo stacked structure, pure A1 and its alloy, Mo/Nd/Cu , Ti/Cu and other metals.
  • the use of copper or copper alloy as the gate has the effect of optimizing the patterning process, improving device performance, and reducing cost.
  • the first gate insulating layer may be made of a silicon nitride film or a silicon oxynitride film. film.
  • the second gate insulating layer may be formed of a film formed of another inorganic insulating material having the same or similar material properties as those of the above materials.
  • the third gate insulating layer may be formed of a silicon oxide film, an aluminum oxide film or a film formed of an oxygen-containing material.
  • the first gate insulating layer is made of an inorganic insulating material such as a silicon nitride film or a silicon oxynitride film. Since the material directly contacts the oxide semiconductor layer, the performance of the oxide semiconductor layer is lowered, but It is possible to better suppress the contact with the gate metal (especially when the copper and its alloy are used as the gate) to cause a problem, so that the first gate insulating layer is disposed close to the gate but away from the active layer.
  • an inorganic insulating material such as a silicon nitride film or a silicon oxynitride film. Since the material directly contacts the oxide semiconductor layer, the performance of the oxide semiconductor layer is lowered, but It is possible to better suppress the contact with the gate metal (especially when the copper and its alloy are used as the gate) to cause a problem, so that the first gate insulating layer is disposed close to the gate but away from the active layer.
  • the second gate insulating layer is disposed on the intermediate layer, and the second gate insulating layer made of an inorganic insulating material such as a silicon oxynitride film itself has relatively few H+, OH- groups, etc., and is simultaneously H+, OH- The group has a certain anti-penetration ability, which can well inhibit the diffusion of H+, OH- and the like to the oxide semiconductor layer, thereby achieving the purpose of improving device stability.
  • the third gate insulating layer is closely adhered to the oxide semiconductor, so that the matching with the oxide semiconductor can be better achieved, thereby improving the stability of the device.
  • the structure of the gate insulating layer is not limited, and may be one layer, two layers or three layers. The selection of the specific layer may be determined according to actual needs. .
  • a method of fabricating an array substrate will be described below with a single passivation layer and a single layer of gate insulating layer.
  • an example of the method includes the following steps.
  • Step S101 forming a gate metal film on the substrate.
  • a gate metal film is formed on the glass substrate 401.
  • the gate metal film is usually prepared by a method of measurement and sputtering, and the material thereof may be copper or an alloy thereof, and the thickness may be 200 nm to 350 nm to maintain the sheet resistance. At a relatively low level.
  • Step S102 patterning the gate metal film.
  • the gate metal film is patterned by wet etching to form gate lines and gate electrodes 402. Further, if necessary, common electrode lines can be simultaneously formed.
  • Step S103 forming a first gate insulating layer on the gate.
  • the gate insulating layer in this embodiment is a layer, and a silicon oxide film, silicon nitride, or nitrogen can be used.
  • a first gate insulating layer is formed of silicon oxide, aluminum oxide, titanium oxide or other inorganic insulating material.
  • the first gate insulating layer may have a thickness of 50 nm to 500 nm.
  • Step S104 performing an annealing process on the first gate insulating layer.
  • the annealing process can be optimized as: ⁇ dehydrogenating the first gate insulating layer with a high temperature annealing furnace, annealing, protecting with nitrogen, vacuum or a rare gas, the annealing temperature can be 250 ° C ⁇ 450 ° C, annealing The time can be 20 min ⁇ l 50min.
  • the annealing process can be further optimized as: adding a vacuum heating chamber to the PECVD apparatus, the gas pressure can be 1 (T 4 Pa ⁇ lPa, dehydrogenating the first gate insulating layer; the annealing chamber temperature can be 350 ° C ⁇ 480 ° C, annealing time can be 10min ⁇ 30min. Art, can shorten the process time, increase product yield, while reducing equipment capital investment.
  • Step S105 forming an oxide semiconductor active layer on the first gate insulating layer.
  • the oxide semiconductor may be a mixture of indium gallium oxide (IGZO), indium tin oxide oxidation (ITZO), indium oxide (IZO), and the like, and various ratios of the above substances.
  • IGZO indium gallium oxide
  • ITZO indium tin oxide oxidation
  • IZO indium oxide
  • Step S106 after the above-mentioned oxide semiconductor active layer is formed, an etch stop layer is formed thereon.
  • Step S107 forming a source/drain electrode layer of the TFT device on the substrate on which the above steps are completed.
  • Source and drain electrodes in the source/drain electrode layer 406 are respectively connected to both sides of the oxide semiconductor active layer 404, and are disposed opposite to each other.
  • Step S108 forming a first passivation layer on the substrate on which the above steps are completed.
  • the first passivation layer 407 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a titanium oxide film, a zirconia film, a hafnium oxide film, a barium titanate film or a hafnium oxide film. Insulation Materials.
  • the first passivation layer may have a thickness of 50 nm to 500 nm.
  • the first passivation layer 407 may be an organic insulating material such as a resin-based insulating film or an acryl-based insulating film.
  • the thickness of the first passivation layer 407 may be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • Step S109 performing an annealing process on the first passivation layer.
  • step S109 Since the oxide semiconductor active layer has been fabricated before step S109; in order to minimize the influence of the annealing process on the active layer, the temperature used in the annealing process in step S109 cannot be too large.
  • the annealing process can be: adding a heating chamber of nitrogen or air to the PECVD equipment, The first passivation layer is subjected to a dehydrogenation process; the annealing chamber temperature may be 200 ° C to 350 ° C, and the annealing time may be 15 min to 90 min.
  • Step S110 forming a pixel electrode layer on the substrate on which the above steps are completed.
  • the preparation steps of other film layers can be realized by conventional techniques, which are not the design points of the embodiment, and are not here. .
  • the gate insulating layer and the passivation layer are made of a specific material, which can reduce the influence of the gate insulating layer and the passivation layer and the complex of hydrogen and hydrogen doped in the external environment on the characteristics of the oxide semiconductor.
  • the gate metal in this embodiment may also be a commonly used Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo stacked structure electrode, pure A1 and its alloy, Metal such as Mo/Nd/Cu, Ti/Cu.
  • the gate of the thin film transistor in the array substrate provided in this embodiment is located above the active layer, that is, the top gate type array structure.
  • the TN type structure is taken as an example, and the passivation layer on the array substrate is located between the gate electrode and the pixel electrode layer.
  • the structure and manufacturing method of the passivation layer are the same as those of the passivation layer in the first embodiment, and are not described herein again.
  • the array substrate provided in this embodiment has an array substrate structure (ie, a bottom gate type) in which the gate of the thin film transistor is located on the bottom layer.
  • the array substrate provided in this embodiment includes: a gate electrode 402 on the substrate 401, a gate insulating layer 403 and an active layer 404, a source/drain electrode layer 406, a pixel electrode layer 412 and a passivation layer respectively on the gate.
  • the gate insulating layer 403 is located between the gate electrode 402 and the active layer 404; the passivation layer is between the source/drain electrode layer 406 and the pixel electrode layer 412.
  • the active layer 404 is an oxide semiconductor, and the gate and source/drain electrodes may be copper, a copper alloy, aluminum, an aluminum alloy, chromium, phase, titanium, tantalum or manganese, an alloy or a laminated structure of the above metals.
  • the passivation layer is a two-layer structure, including a first passivation layer 407 and a second passivation layer 408, the first passivation layer 407 is adjacent to the source and drain electrode layer 406, the second passivation layer 408 is adjacent to the pixel electrode layer 412;
  • the first passivation layer 407 As the first inorganic insulating layer, the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a tantalum trioxide film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film or a silicon oxynitride film.
  • the first passivation layer may have a thickness of 50 nm to 600 nm.
  • the second passivation layer 408 is a second inorganic insulating layer or a first organic insulating layer; the second inorganic insulating layer may include a silicon nitride film, a tantalum trioxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film. a barium titanate film or a ruthenium oxide film; the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film.
  • the thickness of the second passivation layer may be 50 nm to 500 nm; when the second passivation layer is an organic insulating layer, the thickness of the second passivation layer may be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • the first passivation layer and the second passivation layer are both passivation layers processed by an annealing process. Refer to Figure 6.
  • each of the above structural layers can effectively prevent the influence of the hydrogen-containing groups on the oxide semiconductor, and ensure that the preparation of the first passivation layer is completed in a short time, that is, the production efficiency is ensured. If the thickness is too thin, the effect of avoiding the influence of the hydrogen-containing group on the oxide semiconductor cannot be achieved; and if the thickness is too thick, a longer filming time (tact time) is required, resulting in a decrease in production efficiency. .
  • the first passivation layer 407 may be a thin film other than the inorganic insulating materials listed above.
  • the second passivation layer 408 may be formed of a film formed of the second inorganic insulating material listed in the above column.
  • the second passivation layer may be formed of a first organic insulating material such as a resin insulating film or an acrylic insulating film, or may be formed of another organic insulating material having the same or similar material properties as those of the above materials. film.
  • the material of the first passivation layer in this embodiment is preferably an oxide, and the oxide can be effectively in contact with the oxide semiconductor layer at the channel position;
  • the second passivation layer is
  • the nitride and the nitride are effective in preventing interference of a composite oxide semiconductor layer of hydrogen or hydrogen from the outside.
  • the first passivation layer and the second passivation layer are selected as different materials as possible.
  • the material may be structurally designed, and a passivation layer adjacent to the oxide semiconductor side is provided for oxygen enrichment treatment to increase oxygen content in the material.
  • the specific gravity of the amount and the passivation layer provided away from the oxide semiconductor layer have the property of blocking the penetration of external hydrogen atoms and water vapor into the film, thereby obtaining the desired technical effect.
  • the first passivation layer 407 may be a first inorganic insulating material such as a silicon oxide film, an aluminum oxide film, a tantalum trioxide or a silicon oxynitride film, and the materials themselves contain H+, OH- and the like. It has less anti-penetration ability to H+, OH- and other groups, which can effectively inhibit the diffusion of H+, OH- and other groups to the oxide semiconductor layer, thereby improving the stability of the device and avoiding the device.
  • a first inorganic insulating material such as a silicon oxide film, an aluminum oxide film, a tantalum trioxide or a silicon oxynitride film, and the materials themselves contain H+, OH- and the like. It has less anti-penetration ability to H+, OH- and other groups, which can effectively inhibit the diffusion of H+, OH- and other groups to the oxide semiconductor layer, thereby improving the stability of the device and avoiding the device.
  • a second inorganic insulating material such as silicon nitride, antimony trioxide or silicon oxynitride or a first organic insulating material such as a resin insulating film or an acrylic insulating film may be used.
  • the second passivation layer is in close contact with the pixel electrode layer, so that the adhesion to the pixel electrode layer can be better improved, and the stability of the device can be improved.
  • a method of fabricating an array substrate will be described below with two layers of passivation layers and a single layer of gate insulating layer. As shown in FIG. 7, an example of the method includes the following steps.
  • Step S201 forming a gate metal film on the substrate.
  • a gate metal thin film layer is formed on the glass substrate 401.
  • the gate metal thin film is usually prepared by a method of measurement and sputtering, and the material thereof may be selected from copper and its alloy, and the thickness is generally 200 nm-350 nm, and the sheet resistance is obtained. Keep at a relatively low level.
  • Step S202 patterning the gate metal film.
  • the gate metal film is patterned by wet etching to form gate lines and gate electrodes 402. Further, if necessary, common electrode lines can be simultaneously formed.
  • Step S203 forming a first gate insulating layer on the gate.
  • a first gate insulating layer may be formed on the gate layer by using a silicon nitride film or a silicon oxynitride film, and the first gate insulating layer may have a thickness of 50 nm to 600 nm.
  • Step S204 performing an annealing process on the first gate insulating layer.
  • an annealing process is performed to minimize the H+, OH- and the like which may be broken and diffused in the first gate insulating layer, thereby achieving the effect of improving device stability.
  • Step S205 forming an oxide semiconductor active layer on the first gate insulating layer, and patterning.
  • the oxide semiconductor may be an indium gallium oxide (IGZO), an indium tin oxide oxide (ITZO), an indium oxide (IZO), or the like, and a complex ratio of the above substances.
  • the main manufacturing methods include magnetron sputtering deposition (Sputter) and solution method.
  • Active layer oxide There are two types of etching methods commonly used in semiconductors, one is wet etching and the other is dry etching. Currently, wet etching is widely used, and etching precision can be controlled well.
  • the oxide semiconductor layer is patterned by etching. The following embodiments are identical to the above, and therefore will not be described again.
  • Step S206 after the above-mentioned oxide semiconductor active layer is formed, an etch stop layer is formed thereon.
  • Step S207 forming source and drain electrodes of the TFT device on the substrate on which the above steps are completed.
  • Step S208 forming a first passivation layer on the substrate on which the above steps are completed.
  • the first passivation layer 407 is a first inorganic insulating layer, and the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a tantalum trioxide film, a zirconia film, a hafnium oxide film, a barium titanate film, and hafnium oxide. a thin film or a silicon oxynitride film; the first passivation layer may have a thickness of 50 nm to 600 nm.
  • Step S209 performing an annealing process on the first passivation layer.
  • the annealing process may be: adding a nitrogen or air heating chamber to the PECVD apparatus to perform a dehydrogenation process on the first passivation layer; the annealing chamber temperature may be 200 ° C to 350 ° C, and the annealing time may be 15 min. 90min.
  • Step S210 forming a second passivation layer on the first passivation layer.
  • the second passivation layer 408 is a second inorganic insulating layer or a first organic insulating layer, and the second inorganic insulating layer may include a silicon nitride film, a tantalum trioxide film, a silicon oxynitride film, a zirconium oxide film, a hafnium oxide film. , barium titanate film or yttria film.
  • the second passivation layer may have a thickness of 50 nm to 500 nm.
  • the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film. The thickness of the second passivation layer made of an organic insulating film can be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • Step S211 performing an annealing process on the second passivation layer.
  • the annealing process may be: adding a nitrogen or air heating chamber to the PECVD apparatus to perform a dehydrogenation process on the second passivation layer; the annealing chamber temperature may be 200 ° C to 350 ° C, and the annealing time may be 15 min. 90min.
  • Step S212 forming a pixel electrode layer on the substrate on which the above steps are completed.
  • the preparation steps of other film layers can be realized by conventional techniques, but this is not the design point of the embodiment, and superfluous.
  • the gate insulating layer in this embodiment may employ a two-layer or three-layer structure as described in Embodiment 1, in addition to the single-layer structure.
  • Embodiment 4 The difference between this embodiment and the third embodiment is that the array substrate provided in this embodiment is an array substrate of a thin film transistor whose gate layer is located on the top layer, that is, a top gate array substrate.
  • the passivation layer includes a first passivation layer adjacent to the gate, the second passivation layer is adjacent to the pixel electrode layer, and the structure, material and fabrication of the passivation layer
  • the method is the same as the structure, the material and the manufacturing method of the passivation layer of the embodiment 3.
  • the process for forming each structural layer is the same as that of the third embodiment, and details are not described herein again.
  • the array substrate provided in this embodiment has an array substrate structure (ie, a bottom gate type) in which the gate layer of the thin film transistor is located on the bottom layer.
  • the array substrate provided in this embodiment includes: a gate electrode 402 on the substrate 401, a gate insulating layer 403 and an active layer 404 respectively on the gate electrode 402, a source/drain electrode layer 406, a pixel electrode layer 412, and a passivation layer.
  • the gate insulating layer 403 is located between the gate electrode 402 and the active layer 404; the passivation layer is located between the source and drain electrode layers and the pixel electrode layer.
  • the active layer 404 is an oxide semiconductor
  • the gate is copper or a copper alloy
  • the passivation layer has a three-layer structure including a first passivation layer 407, a second passivation layer 408, and a third passivation layer 409, the first blunt
  • the layer 407 is adjacent to the source and drain electrode layer 406, and the third passivation layer 409 is adjacent to the pixel electrode layer 412.
  • the second passivation layer 408 is located between the first passivation layer 407 and the third passivation layer 409.
  • the first passivation layer 407 is a first inorganic insulating layer including a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate film, or an oxide film.
  • An inorganic insulating material such as a germanium film; the first passivation layer may have a thickness of 50 mm to 600 mm.
  • the second passivation layer 408 is a second inorganic insulating layer or a first organic insulating layer, and the second inorganic insulating layer may include a silicon oxynitride film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride layer.
  • the inorganic insulating material such as a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film may be included, and the second organic insulating layer may include a resin-based insulating film or an acrylic insulating film.
  • the thickness of the second passivation layer may be 50 nm 650 650 nm; when the second passivation layer is an organic insulating layer, the thickness of the second passivation layer may be 0.5 ⁇ 2.5 ⁇ .
  • the third passivation layer 409 is an inorganic insulating layer, the third passivation layer The thickness of 409 may be 50 nm to 500 nm; when the third passivation layer 409 is an organic insulating layer, the thickness of the third passivation layer 408 may be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • the oxide inorganic insulating material applied to the first passivation layer 407 adjacent to the source/drain electrode layer 406 facilitates bonding with the oxide semiconductor active layer to enhance the stability of the device; the second blunt layer in the intermediate layer
  • the inorganic insulating material such as oxynitride used in the layer 408 has a relatively small group of ⁇ +, ⁇ -, etc., and has a certain absorption capacity for groups such as ⁇ +, ⁇ -, etc.
  • the containment of ⁇ +, ⁇ -, etc. groups diffuse into the oxide semiconductor layer to achieve the purpose of improving device stability and avoid device failure;
  • the third passivation layer 409 is used to prevent external hydrogen environment from being on the device. The effect is further to improve the stability of the device.
  • each of the above structural layers can effectively prevent the influence of the hydrogen-containing groups on the oxide semiconductor, and ensure that the preparation of the first passivation layer is completed in a short time, that is, the production efficiency is ensured. If the thickness is too thin, the effect of avoiding the influence of the hydrogen-containing group on the oxide semiconductor cannot be achieved; and if the thickness is too thick, a longer filming time (tact time) is required, resulting in a decrease in production efficiency. .
  • the first passivation layer may be a film formed of other inorganic insulating materials having the same or similar material properties as those of the above materials, in addition to the materials listed above.
  • the second passivation layer can be used in addition to the materials listed above, and in the present embodiment, the third passivation layer can be used in addition to the materials listed above.
  • the structure of the gate insulating layer in this embodiment is the same as that of the gate insulating layer in the first embodiment, and details are not described herein again.
  • a method of fabricating an array substrate will be described below with a three-layer passivation layer and a single-layer gate insulating layer. As shown in FIG. 9, an example of the method includes the following steps.
  • Step S301 forming a gate metal thin film layer on the substrate.
  • a gate metal thin film layer is formed on the glass substrate 401.
  • the gate metal thin film is usually prepared by a method of measurement and sputtering, and the material thereof may be copper or an alloy thereof, and the thickness thereof may generally be 200 nm to 350 nm, so that The sheet resistance is maintained at a relatively low level.
  • Step S302 patterning the gate layer.
  • the gate metal film is patterned by wet etching to form gate lines and gates. 402;
  • a common electrode line can be fabricated at the same time if necessary.
  • Step S303 forming a first gate insulating layer on the gate.
  • a first gate insulating layer may be formed on the gate layer by using a silicon nitride film or a silicon oxynitride film, and the first gate insulating layer may have a thickness of 50 nm to 600 nm.
  • Step S304 performing an annealing process on the first gate insulating layer.
  • an annealing process is performed to minimize the H+, OH- and the like which may occur in the first gate insulating layer, and the stability of the device is improved.
  • oxide semiconductors can be indium gallium oxide (IGZO), indium tin oxide oxidation
  • ITZO indium oxide
  • IZO indium oxide
  • Step S306 after the active layer oxide semiconductor described above is completed, an etch stop layer is formed thereon.
  • Step S307 forming source and drain electrodes of the TFT device on the substrate on which the above steps are completed.
  • Step S308 forming a first passivation layer on the substrate on which the above steps are completed.
  • Step S309 forming a second passivation layer on the first passivation layer.
  • Step S310 forming a third passivation layer on the second passivation layer.
  • the first passivation layer 407 is a first inorganic insulating layer
  • the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, and a titanium film.
  • An inorganic insulating material such as a cerium oxide film or a cerium oxide film; the first passivation layer may have a thickness of 50 nm to 600 nm.
  • the second passivation layer 408 may be a second inorganic insulating layer or a first organic insulating layer, and the second inorganic insulating layer may include a silicon oxynitride film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or oxynitride.
  • the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film; the third passivation layer 409 may be a third inorganic insulating layer or a second organic insulating layer;
  • the thickness of the second passivation layer may be 50 nm to 650 nm; when the second passivation layer is an organic insulating layer, the thickness of the second passivation layer may be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • the third passivation layer 409 is a third inorganic insulating layer or a second organic insulating layer, and the third inorganic insulating layer may include an inorganic insulating material such as a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film.
  • the second organic insulating layer may include a resin-based insulating film or an acryl-based insulating film.
  • the third passivation layer 409 When the third passivation layer 409 is an inorganic insulating layer, the third passivation layer 409 may have a thickness of 50 nm to 500 nm; when the third passivation layer 409 is an organic insulating layer, the The thickness of the three passivation layer 408 can be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • Step S311 forming a pixel electrode layer on the substrate on which the above steps are performed.
  • the manufacturing process steps of the other film layer structures can be realized by conventional technical means, which is not the design point of the embodiment, and is not here.
  • the gate insulating layer in this embodiment may employ a two-layer or three-layer structure as described in Embodiment 1, in addition to the single-layer structure.
  • the array substrate provided in this embodiment is an array substrate in which the gate layer of the thin film transistor is located on the top layer, that is, the top gate type array substrate.
  • the passivation layer includes a first passivation layer, a second passivation layer, and a third passivation layer, the first passivation layer is adjacent to the gate layer, and the third passivation layer is adjacent to the pixel electrode layer, The second passivation layer is between the first passivation layer and the third passivation layer.
  • the structure, material and manufacturing method of the passivation layer are the same as those of the structure, material and manufacturing method of the passivation layer of the fifth embodiment, and the process for forming each structural layer is the same as that of the fifth embodiment, and will not be further described herein.
  • the array substrate provided in this embodiment is an array substrate structure (ie, a bottom gate type) in which the gate layer of the thin film transistor is located on the bottom layer.
  • the array substrate provided in this embodiment includes: a gate electrode 402 on the substrate 401, a gate insulating layer 403 and an active layer 404 respectively on the gate electrode, and a source/drain electrode layer.
  • the gate insulating layer 403 is located at the gate 402 and the active layer
  • the passivation layer is between the source and drain electrode layers and the pixel electrode layer.
  • the active layer 404 is an oxide semiconductor
  • the gate is copper or a copper alloy
  • the passivation layer has a four-layer structure including a first passivation layer 407, a second passivation layer 408, a third passivation layer 409, and a fourth blunt
  • the first passivation layer 407 is adjacent to the source/drain electrode layer 406, and the fourth passivation layer 410 is adjacent to the pixel electrode layer.
  • the second passivation layer 408 and the third passivation layer 409 are located at the first passivation layer 407 and the fourth passivation layer
  • the first passivation layer 407 is a first inorganic insulating layer, and the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a titanium oxide, a silicon oxynitride film, a zirconia film, a hafnium oxide film, and a barium titanate.
  • the second passivation layer 408 is a second inorganic insulating layer, and the second inorganic insulating layer may include an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film;
  • the third passivation layer 409 is a third inorganic insulating layer, and the third inorganic insulating layer may include a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film;
  • the fourth passivation layer 410 is
  • the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film.
  • the thickness of the first passivation layer 407 may be 50 nm to 600 nm
  • the thickness of the second passivation layer 408 may be 50 nm to 650 ⁇
  • the thickness of the third passivation layer 409 may be 50 nm to 500 nm
  • the thickness of the layer can be 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • each of the above structural layers can effectively prevent the influence of the hydrogen-containing groups on the oxide semiconductor, and ensure that the preparation of the first passivation layer is completed in a short time, that is, the production efficiency is ensured. If the thickness is too thin, the effect of avoiding the influence of the hydrogen-containing group on the oxide semiconductor cannot be achieved; and if the thickness is too thick, a longer filming time (tact time) is required, resulting in a decrease in production efficiency. .
  • the first passivation layer may be a film formed of other inorganic insulating materials having the same or similar material properties as those of the above materials, in addition to the materials listed above.
  • the second passivation layer may be a film formed of another inorganic insulating material having the same or similar material properties as the above materials.
  • the third passivation layer may be formed of a film formed of another inorganic insulating material having the same or similar material properties as those of the above materials, in addition to the materials listed above.
  • the fourth passivation layer may be a film formed of another organic insulating material having the same or similar material properties as the above materials.
  • the first passivation layer is made of a silicon oxide film, an inorganic insulating material such as an aluminum oxide film, a tantalum trioxide or a silicon oxynitride film, and an inorganic insulating material such as a silicon oxide film is used in combination with the second passivation layer and
  • the third passivation layer is made of an inorganic insulating material such as a silicon nitride film, and has a relatively small group of H+, OH- and the like, and has a certain anti-penetration ability to a group such as H+, OH-, etc.
  • the paste can improve the adhesion to the pixel electrode layer and improve the stability of the device.
  • the structure of the gate insulating layer in this embodiment is the same as that of the gate insulating layer in Embodiment 1, in This will not be repeated here.
  • a method of fabricating an array substrate will be described below with a four-layer passivation layer and a single-layer gate insulating layer. As shown in FIG. 11, an example of the method includes the following steps.
  • Step S401 forming a gate metal thin film layer on the substrate.
  • a gate metal thin film layer is formed on the glass substrate 401.
  • the gate metal thin film is usually prepared by a method of measurement and sputtering, and the material thereof may be copper or an alloy thereof, and the thickness is generally 200 nm to 350 nm, so that the sheet resistance is obtained. Keep at a relatively low level.
  • Step S402 patterning the gate metal film.
  • the gate metal film is patterned by wet etching to form gate lines and gate electrodes 402; and, if necessary, common electrode lines can be simultaneously formed.
  • Step S403 forming a first gate insulating layer on the gate.
  • a first gate insulating layer may be formed on the gate layer by using a silicon nitride film or a silicon oxynitride film, and the first gate insulating layer may have a thickness of 50 nm to 600 nm.
  • Step S404 performing an annealing process on the first gate insulating layer.
  • an annealing process is performed to minimize the H+, OH- and the like which may occur in the first gate insulating layer, and the stability of the device is improved.
  • Step S405 an oxide semiconductor active layer 404 is formed on the first gate insulating layer and patterned.
  • oxide semiconductors can be indium gallium oxide (IGZO), indium tin oxide oxidation
  • ITZO indium oxide
  • IZO indium oxide
  • Step S406 after completing the active layer oxide semiconductor described above, an etch stop layer is formed thereon.
  • Step S407 forming source and drain electrodes of the TFT device on the substrate on which the above steps are completed.
  • Step S408 forming a first passivation layer on the substrate on which the above steps are completed.
  • the first passivation layer 407 is a first inorganic insulating layer
  • the first inorganic insulating layer includes a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, and a titanic acid.
  • a tantalum film, a hafnium oxide film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film; the first passivation layer may have a thickness of 50 nm to 600 nm.
  • Step S409 forming a second passivation layer on the first passivation layer.
  • the second passivation layer 408 is a second inorganic insulating layer including an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film; the thickness of the second passivation layer may be 50 650 nm
  • Step S410 forming a third passivation layer on the second passivation layer.
  • the third passivation layer is a third inorganic insulating layer, and the third inorganic insulating layer comprises a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film; the thickness of the third passivation layer may be 50 nm 500nm
  • Step S411 forming a fourth passivation layer on the third passivation layer.
  • the fourth passivation layer is a first organic insulating layer, and the first organic insulating layer includes a resin-based insulating film or an acryl-based insulating film; the fourth passivation layer may have a thickness of 0.5 ⁇ 2.5 ⁇ , step S412, A pixel electrode layer is formed on the substrate on which the above steps are made.
  • the manufacturing process steps of the other film layer structures can be realized by conventional technical means, which is not the design point of the embodiment, and is not here.
  • the gate insulating layer in this embodiment may employ a two-layer or three-layer structure as described in Embodiment 1, in addition to the single-layer structure.
  • the array substrate provided in this embodiment is an array substrate in which the gate layer of the thin film transistor is located on the top layer, that is, the top gate type array substrate.
  • the passivation layer includes a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer, the first passivation layer is adjacent to the gate, and the fourth passivation layer is adjacent to the pixel electrode a layer, the second passivation layer and the third passivation layer are located between the first passivation layer and the fourth passivation layer, specifically the structure, material and fabrication method of the passivation layer and the passivation layer of the seventh embodiment
  • the structure, the material and the manufacturing method are the same, and the process for forming each structural layer is the same as that of the seventh embodiment, and details are not described herein again.
  • the array substrate provided in this embodiment is an array substrate structure (ie, a bottom gate type) in which the gate layer of the thin film transistor is located on the bottom layer.
  • the array substrate provided in this embodiment includes: a gate electrode 402 on the substrate 401, a gate insulating layer 403 and an active layer 404, a source/drain electrode layer 406, a pixel electrode layer 412 and a passivation layer respectively on the gate electrode.
  • the gate insulating layer is between the gate electrode and the active layer; the passivation layer is between the source drain electrode layer and the pixel electrode layer.
  • the active layer 404 is an oxide semiconductor, the gate is copper or a copper alloy, and the passivation layer has a four-layer structure.
  • a first passivation layer 407, a second passivation layer 408, a third passivation layer 409, a fourth passivation layer 410, and a fifth passivation layer 411 are included.
  • the first passivation layer 407 is adjacent to the source/drain electrode layer 406, and the fifth passivation layer 411 is adjacent to the pixel electrode layer 412; the second passivation layer 408, the third passivation layer 409, and the fourth passivation layer 410 are located at the first Between the passivation layer and the fifth passivation layer 411.
  • the first passivation layer 407 is a first inorganic insulating layer, and the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a titanium oxide, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate film, a ruthenium oxide film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film; the second passivation layer 408 is a second inorganic insulating layer, and the second inorganic insulating layer may include aluminum oxynitride a thin film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film; the third passivation layer 409 is a third inorganic insulating layer, and the third
  • the fourth passivation layer is made of an organic insulating layer material such as a resin-based insulating film or an acryl-based insulating film, which can effectively increase the aperture ratio of the array substrate, reduce the coupling capacitance, and have a flattening effect of reducing the end difference.
  • the fifth passivation layer is made of an inorganic insulating layer material such as a silicon oxynitride film, a silicon oxide film or a silicon nitride film, which can strengthen the adhesion between the passivation layer and the pixel electrode layer and can effectively prevent the organic insulating layer material from working. The problem of failure occurred in the process.
  • the thickness of the first passivation layer may be 50 nm to 600 nm
  • the thickness of the second passivation layer may be 50 ⁇ to 650 nm
  • the thickness of the third passivation layer may be 50 ⁇ to 500 nm
  • the thickness of the fourth passivation layer may be 0.5 ⁇ ! ⁇ 2.5 ⁇
  • the fifth passivation layer may have a thickness of 20 nm to 450 nm.
  • each of the above structural layers can effectively prevent the influence of the hydrogen-containing groups on the oxide semiconductor, and ensure that the preparation of the first passivation layer is completed in a short time, that is, the production efficiency is ensured. If the thickness is too thin, the effect of avoiding the influence of the hydrogen-containing group on the oxide semiconductor cannot be achieved; and if the thickness is too thick, a longer filming time (tact time) is required, resulting in a decrease in production efficiency. .
  • the first passivation layer can be used in addition to the materials listed above.
  • the second passivation layer may be a film formed of another inorganic insulating material having the same or similar material properties as the above materials.
  • the third passivation layer may be formed of a film formed of another inorganic insulating material having the same or similar material properties as those of the above materials, in addition to the materials listed above.
  • the fourth passivation layer may be a film formed of another organic insulating material having the same or similar material properties as the above materials.
  • the fifth passivation layer may be a film formed of other inorganic insulating materials having the same or similar material properties as those of the above materials, in addition to the materials listed above.
  • the structure of the gate insulating layer in this embodiment is the same as that of the gate insulating layer in Embodiment 1, and will not be described again.
  • a method of fabricating an array substrate will be described below with five layers of passivation layers and a single layer of gate insulating layers. As shown in FIG. 13, an example of the method may include the following steps.
  • Step S501 forming a gate metal film on the substrate.
  • a gate metal thin film layer is formed on the glass substrate 401, and the gate metal thin film is usually prepared by a method of measurement and control sputtering.
  • the electrode material may be selected from copper and its alloy, and the thickness is generally 200 nm-350 nm, so that the sheet resistance is obtained. Keep at a relatively low level.
  • Step S502 patterning the gate metal film.
  • the gate layer is patterned by wet etching to form a gate line and a gate electrode 402. Further, if necessary, a common electrode line can be simultaneously formed.
  • Step S503 forming a first gate insulating layer on the gate.
  • a first gate insulating layer may be formed on the gate layer by using a silicon nitride film or a silicon oxynitride film, and the first gate insulating layer may have a thickness of 50 nm to 600 nm.
  • Step S504 performing an annealing process on the first gate insulating layer.
  • an annealing process is performed to minimize the H+, OH- and the like which may occur in the first gate insulating layer, and the stability of the device is improved.
  • Step S505 forming an active layer oxide semiconductor on the first gate insulating layer, and patterning.
  • the oxide semiconductor may be an indium gallium oxide (IGZO), an indium tin oxide oxide (ITZO), an indium oxide (IZO), or the like, and a complex ratio of the above substances.
  • Step S506 after the above-mentioned oxide semiconductor active layer is completed, an etch barrier layer is formed thereon.
  • Step S507 forming source and drain electrodes of the TFT device on the substrate on which the above steps are performed.
  • Step S508 forming a first passivation layer on the substrate on which the above steps are completed.
  • the first passivation layer is a first inorganic insulating layer
  • the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a titanium oxide, a silicon oxynitride film, a zirconia film, a hafnium oxide film, or a titanic acid.
  • the first passivation layer may have a thickness of 50 nm to 600 nm.
  • Step S509 forming a second passivation layer on the first passivation layer.
  • the second passivation layer is a second inorganic insulating layer including an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film.
  • the thickness of the second passivation layer may be from 50 nm to 650 nm.
  • Step S510 forming a third passivation layer on the second passivation layer.
  • the third passivation layer is a third inorganic insulating layer, and the third inorganic insulating layer comprises a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film; the thickness of the third passivation layer may be 50 nm to 500 nm.
  • Step S511 forming a fourth passivation layer on the third passivation layer.
  • the fourth passivation layer is a first organic insulating layer, and the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film; the fourth passivation layer may have a thickness of 0.5 ⁇ ! ⁇ 2.5 ⁇ .
  • Step S512 forming a fifth passivation layer on the fourth passivation layer.
  • the fifth passivation layer is a fourth inorganic insulating layer
  • the fourth inorganic insulating layer includes a silicon oxynitride film, a silicon oxide film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film, and an aluminum oxynitride film.
  • the fifth passivation layer may have a thickness of 20 ⁇ to 450 ⁇ .
  • Step S513 forming a pixel electrode layer on the substrate on which the above steps are performed.
  • the preparation steps of the other film layer structures can be realized by conventional technical means, which is not the design point of the embodiment, and is not here.
  • the gate insulating layer in this embodiment may employ a two-layer or three-layer structure as described in Embodiment 1, in addition to the single-layer structure.
  • the array substrate provided in this embodiment is an array substrate in which the gate layer of the thin film transistor is located on the top layer, that is, the top gate type array substrate.
  • the passivation layer includes a first passivation layer, a second passivation layer, a third passivation layer, a fourth passivation layer, and a fifth passivation layer, the first passivation layer being adjacent to the gate layer, the first The fifth passivation layer is adjacent to the pixel electrode layer, and the second passivation layer, the third passivation layer and the fourth passivation layer are located between the first passivation layer and the fifth passivation layer, specifically the structure of the passivation layer
  • the material and the manufacturing method are the same as the structure, the material and the manufacturing method of the passivation layer of the seventh embodiment.
  • the process for forming the structural layer is the same as that of the embodiment 9, and will not be described again.
  • the method for fabricating the array substrate is described below based on the case where the passivation layer of the five-layer structure in the ninth embodiment is combined with the gate insulating layer of the three-layer structure as an example, but the method is not limited to the above structure.
  • An example of the method includes the following steps.
  • Step S601 forming a gate metal thin film layer on the substrate.
  • a gate metal thin film layer is formed on a glass substrate.
  • the gate is mostly prepared by magnetron sputtering, and the electrode material can be selected according to different device structures and process requirements.
  • Commonly used gate metals are Mo, Mo-Al-Mo alloys, Mo/Al-Nd/Mo stacked electrodes, pure A1 and its alloys, Cu and its alloys, Mo/Nd/Cu, Ti/ Metals such as Cu have a thickness of 200 nm to 350 nm, which keeps the sheet resistance at a relatively low level.
  • Step S602 patterning the gate metal film.
  • the gate metal film is patterned by wet etching to form gate electrodes and common electrode lines.
  • a first gate insulating layer is formed on the gate by using a silicon nitride film or a silicon oxynitride film.
  • the first gate insulating layer may have a thickness of 50 nm to 300 nm.
  • Step S604 forming a second gate insulating layer by using a silicon oxynitride film on the first gate insulating layer.
  • Step S605 forming a third gate insulating layer by using silicon oxide, aluminum oxide or titanium oxide on the second gate insulating layer.
  • Step S606 forming an oxide semiconductor active layer on the third gate insulating layer, and patterning.
  • the oxide semiconductor may be indium gallium oxide (IGZO), indium tin oxide oxidation (ITZO), indium oxide (IZO), etc. Different proportions of the composition of the substance.
  • An etch stop layer is formed directly on the patterned oxide semiconductor layer, and the material is usually required to use inorganic insulating materials such as SiOx, SiNx, SiOxNy, A1203, TiOx, Y203, etc., to reduce the data line pattern.
  • the oxide semiconductor film is damaged, and the stability of the device can be effectively improved, and the influence of the external environment on the device can be avoided.
  • the ESL is patterned and usually dry etched.
  • a metal layer is deposited to form a data line and a power line electrode layer.
  • the metal layer is prepared by magnetron sputtering, and the material can be selected according to different device structures and process requirements.
  • the electrode metal that is usually used
  • Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo stacked structure electrode, Cu and titanium metal and its alloy, ITO electrode, Ti/Al/Ti, Mo/ITO, etc., thickness is generally 100 nm -350 nm, keeping its sheet resistance at a relatively low level.
  • the first passivation layer is a first inorganic insulating layer, and the first inorganic insulating layer may include a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate film, and oxidation.
  • the second passivation layer may be a second inorganic insulating layer, and the second inorganic insulating layer may include an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film or a hafnium oxynitride film, and the second passivation layer may have a thickness of 50 nm. ⁇ 650nm.
  • the third passivation layer is a third inorganic insulating layer, and the third inorganic insulating layer may include a silicon nitride film, an aluminum nitride film, a zirconium nitride film or a tantalum nitride film; the third passivation layer may have a thickness of 50 Nm ⁇ 500 ⁇ .
  • the fourth passivation layer is a first organic insulating layer, and the first organic insulating layer may include a resin-based insulating film or an acryl-based insulating film, and the fourth passivation layer may have a thickness of 0.5 ⁇ m! ⁇ 2.5 ⁇ .
  • the fifth passivation layer is a fourth inorganic insulating layer
  • the fourth inorganic insulating layer may include a silicon oxynitride film, a silicon oxide film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, and a nitrogen oxide film.
  • the ruthenium oxide film, the silicon nitride film, the aluminum nitride film, the zirconium nitride film or the tantalum nitride film may have a thickness of the second passivation layer of 20 nm to 450 nm.
  • a via etching process is performed after the passivation layer is formed to realize the wires and the connection to the pixel electrodes. After the above process is completed, deposition and patterning of the pixel electrodes are performed. As shown, after the via formation, a pixel electrode layer is formed, the material of which is now widely used in indium tin oxide (ITO), and patterned by wet etching.
  • ITO indium tin oxide
  • the method for fabricating the above array substrate is the same as the method for fabricating the gate insulating layer and the passivation layer.
  • the above embodiments and corresponding drawings are all based on the TN type to describe the structure of the array substrate provided by the present invention.
  • the pixel electrodes are generally located above the passivation layer.
  • the structure of the ADS type array substrate includes two transparent electrodes, and the two transparent electrodes are respectively located on the upper and lower sides of the passivation layer (for example, the transparent electrode under the passivation layer can be directly formed on the substrate), and is in passivated
  • a layer of transparent electrodes above the layer may be a pixel electrode or a common electrode.
  • ADS Advanced Super-Dimensional Field Switching
  • ADS or AD-SDS technology mainly forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. All the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeezing water ripple (ush Mura), etc. advantage.
  • the array substrate of the embodiment of the present invention and the manufacturing method thereof may be an array substrate applied to a liquid crystal display, such as a TN type array substrate, an ADS type array substrate, an IPS array substrate, or a VA type array substrate, or may be applied to Array substrate for OLED display, etc.
  • an embodiment of the present invention further provides a display device including the above array substrate.
  • the display device includes, but is not limited to, an electronic display device such as a liquid crystal panel, an OLED panel, a liquid crystal display, a liquid crystal television, a liquid crystal display, a tablet computer, or the like.
  • the display device, the array substrate and the manufacturing method thereof are provided in the embodiment of the invention.
  • the gate insulating layer and the passivation layer in the array substrate are combined with the annealing process and the layered structure to maximize the passivation layer.
  • the hydrogen-containing groups in the external environment can effectively avoid the influence of hydrogen groups on the oxide semiconductor, maximize the stability of the entire TFT device, and improve the yield of the final product.

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Abstract

提供一种显示装置、阵列基板及其制作方法。该阵列基板，包括基板（401）以及形成在基板（401）上的薄膜晶体管和像素电极，薄膜晶体管包括栅极（402）、栅极绝缘层（403）、有源层（404）、以及源极和漏极（406），而且在薄膜晶体管上方覆盖有钝化层（407）；薄膜晶体管的有源层为氧化物半导体；钝化层包括至少一层无机绝缘薄膜或有机绝缘薄膜。该阵列基板可有效避免氢基团对氧化物半导体的影响，提高整个TFT器件的稳定性，提高最终产品的良率。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
氧化物薄膜晶体管 ( Oxide TFT )是一类以金属氧化物半导体作为有源层 的薄膜晶体管 （TFT ) , 具有超薄、 低耗电等优势， 不仅可以用于液晶显示 面板的制造， 而且可以用于新一代有机发光显示面板 OLED ( Organic Light-Emitting Diode, 有机发光二极管） 。
参照图 1、 图 2A〜图 2M,对现有技术中的 Oxide TFT阵列基板的制造方 法进行说明。
图 1为现有的 Oxide TFT阵列基板的制造方法的流程框图，图 2A〜图 2M 为 Oxide TFT阵列基板的制造过程中的截面图。
S101\ 在基板上形成栅极金属薄膜。
如图 2A所示， 在基板 12上形成栅极金属薄膜 13。 在 TFT的制作过程 中， 栅极金属薄膜多为釆用磁控溅射的方法来制备， 其材料根据不同的器件 结构和工艺要求可以进行选择。基板 12可以是玻璃基板、石英基板等基于无 机材料的透明基板， 也可以是釆用有机柔性材料制作的透明基板。
S102\ 对栅极金属薄膜进行图形化， 形成栅线和栅极。
如图 2B所示， 通过湿法刻蚀的方式， 对栅极金属薄膜 13进行图形化， 得到栅线（图中未示出 ) 、 栅极 13a与公共电极线 13b。 也可以根据具体设 计不制作公共电极线。
S103，、 在栅极上方形成栅极绝缘层。
如图 2C所示， 在栅极图形化后， 通过 Pre-clean工艺 （成膜前清洗） 、 等离子体增强化学汽相淀积（PECVD )等工艺， 在带有栅极图形的基板上制 备栅极绝缘层 14。
S104'、 形成氧化物半导体薄膜。
如图 2D所示， 形成氧化物半导体薄膜 15。 氧化物 TFT制作最为关键的 环节就是氧化物半导体薄膜的制作。 现在广为使用的氧化物半导体包括铟镓 辞氧化物（IGZO ) , 铟镓锡氧化物（IGTO ) , 铟辞氧化物（IZO )等以及与 其相关的其他不同比例的配合物。 主要的制作方法包括磁控溅射沉积 ( Sputter ) 以及溶液法等。
S105'、 对氧化物半导体薄膜进行图形化， 形成 Oxide TFT的有源层。 如图 2E所示， 对氧化物半导体薄膜进行图形化得到有源层 15a的图案。 对于有源层氧化物半导体图形化工艺主要的刻蚀工艺有两种， 一种为湿法刻 蚀， 另一种为干法刻蚀， 但是釆用不同的方法将会对氧化物半导体层造成不 同的伤害。
S106'、 形成刻蚀阻挡层薄膜并图形化。
如图 2F所示， 形成刻蚀阻挡层薄膜（ Etch Stop Layer, ESL ) 16, 其目的 就是为了减少在后续数据线图形化的过程中对氧化物半导体形成的有源层造 成的伤害。 在刻蚀阻挡层薄膜形成之后， 进行图形化形成刻蚀阻挡层 16a, 如图 2G所示。
S107'、 形成源漏金属层并图形化形成源极、 漏极和数据线。
如图 2H所示， 若在 LCD的制作工艺之中， 首先， 沉积一层源漏金属层 17, 而后通过湿法刻蚀的方法对其进行图形化， 形成如图 21 中所示的源极 17b、 漏极 17a以及与源极 17b—体形成的数据线（图中未示出） 。
若在 OLED制作工艺中，该步骤中则是将源漏金属层图形化后形成源极、 漏极以及与源极一体形成或相连接的电源线。
S108'、 形成钝化层并进行过孔（Via hole )刻蚀。
如图 2J所示，在数据线或电源线图形化之后，在整个平面形成一层钝化 层 18。在钝化层形成之后进行过孔的刻蚀，形成过孔 1%,用以实现漏极 17a 与像素电极的连接， 如图 2K所示。 此外， 在进行刻蚀的过程中， 可以在源 极 17b上方也形成过孔， 用以连接源极 17b与信号接入端， 比如与源极 17b 异层制作的数据线或电源线。
S109\ 像素电极层的沉积及图形化。
如图 2L所示， 在 Via hole形成之后， 形成像素电极层 20, 其材料现在 通常釆用铟锡氧化物 （ITO ) ， 并通过湿法刻蚀的方法对其进行图形化， 形 成像素电极 20a和接触电极 20b , 如图 2M所示。 上述阵列基板的制作工艺中， 在制作钝化层的工艺中避免不了使钝化层 中掺杂着含氢的基团， 如 ΟΗ-, H+, 和吸附氢元素等。 这些含 H基团在器 件的制作过程以及器件在工作的状态中容易发生断裂， 随着时间的推移和环 境的变化， 很有可能扩散到氧化物半导体层中。 扩散出来的 ΟΗ-, H20, H+ 等物质将影响器件的稳定性，使氧化物薄膜晶体管器件的阈值电压（ Vth )发 生较大的漂移， 甚至会导致产品失效。 发明内容
本发明的实施例提供一种阵列基板及其制作方法、 显示装置， 以克服现 有的阵列基板中掺杂的氢基团容易破坏器件的稳定性， 导致影响产品良率的 缺陷。
本发明一方面提供一种阵列基板， 包括基板以及形成在所述基板上的薄 膜晶体管和像素电极， 所述薄膜晶体管包括栅极、 栅极绝缘层、 有源层、 以 及源极和漏极， 而且在所述薄膜晶体管上方覆盖有钝化层； 所述薄膜晶体管 的有源层为氧化物半导体； 所述钝化层包括至少一层无机绝缘薄膜或有机绝 缘薄膜。
对于该阵列基板， 例如， 所述钝化层为一层， 包括第一钝化层； 所述第 一钝化层为无机绝缘层或有机绝缘层； 所述无机绝缘层包括二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化 钽薄膜、 钛酸钡薄膜或氧化钕薄膜； 所述有机绝缘层包括树脂系绝缘膜或亚 克力系绝缘膜。
例如， 在所述第一钝化层为无机绝缘层时， 所述第一钝化层的厚度为 50 nm〜500nm; 在所述第一钝化层为有机绝缘层时， 所述第一钝化层的厚度为 0.5μπι~2.5μπι„
例如， 所述第一钝化层为经过退火工艺处理的钝化层。
对于该阵列基板， 例如， 所述钝化层为两层， 包括第一钝化层和第二钝 化层； 所述第一钝化层贴近所述薄膜晶体管； 所述第一钝化层为第一无机绝 缘层， 该第一无机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 三氧化二钇薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜或氮氧化硅薄膜； 所述 第二钝化层为第二无机绝缘层或第一有机绝缘层； 所述第二无机绝缘层包括 氮化硅薄膜、 三氧化二钇薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜或氧化钕薄膜； 所述第一有机绝缘层包括树脂系绝缘膜或亚克力 系绝缘膜。
例如， 所述第一钝化层的厚度为 50nm〜600nm。
例如， 在所述第二钝化层为无机绝缘层时， 所述第二钝化层的厚度为 50 nm~500nm;
例如， 在所述第二钝化层为有机绝缘层时， 所述第二钝化层的厚度为 0.5μπι~2.5μπι„
例如， 所述第一钝化层和所述第二钝化层均为经过退火工艺处理的钝化 层。
对于该阵列基板， 例如， 所述钝化层为三层， 包括依次设置的第一钝化 层、 第二钝化层和第三钝化层； 所述第一钝化层贴近所述薄膜晶体管； 所述 第一钝化层为第一无机绝缘层； 该第一无机绝缘层包括氧化硅薄膜、 氧化铝 薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜 或氧化钕薄膜； 所述第二钝化层为第二无机绝缘层或第一有机绝缘层； 所述 第二无机绝缘层包括氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化 钽薄膜或氮氧化钕薄膜； 所述第一有机绝缘层包括树脂系绝缘薄膜或亚克力 系绝缘薄膜； 所述第三钝化层为第三无机绝缘层或第二有机绝缘层； 所述第 三无机绝缘层包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所 述第二有机绝缘层包括树脂系绝缘薄膜或亚克力系绝缘薄膜。
例如， 所述第一钝化层的厚度为 50nm〜600nm; 在所述第二钝化层为无 机绝缘层时， 所述第二钝化层的厚度为 50nm〜650nm; 在所述第二钝化层为 有机绝缘层时， 所述第二钝化层的厚度为 0.5μη！〜 2.5μιη; 在所述第三钝化层 为无机绝缘层时， 所述第三钝化层的厚度为 50匪〜500匪； 在所述第三钝化 层为有机绝缘层时， 所述第二钝化层的厚度为 0.5μη！〜 2.5μιη。
对于该阵列基板， 例如， 所述钝化层为四层， 包括依次设置的第一钝化 层、 第二钝化层、 第三钝化层和第四钝化层； 所述第一钝化层贴近所述薄膜 晶体管； 所述第一钝化层为第一无机绝缘层， 该第一无机绝缘层包括氧化硅 薄膜、 氧化铝薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或 氮氧化钕薄膜； 所述第二钝化层为第二无机绝缘层， 该第二无机绝缘层包括 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 所述第三钝 化层为第三无机绝缘层， 该第三无机绝缘层包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第四钝化层为第一有机绝缘层， 该第一有机 绝缘层包括树脂系绝缘薄膜或亚克力系绝缘薄膜。
例如， 所述第一钝化层的厚度为 50nm〜600nm; 所述第二钝化层的厚度 为 50nm〜650nm; 所述第三钝化层的厚度为 50 nm〜500nm; 所述第四钝化层 的厚度为 0.5μη！〜 2.5μιη。
对于该阵列基板， 例如， 所述钝化层为五层， 包括依次设置的第一钝化 层、 第二钝化层、 第三钝化层、 第四钝化层和第五钝化层； 其中， 所述第一 钝化层贴近所述薄膜晶体管； 所述第一钝化层为第一无机绝缘层， 该第一无 机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化 锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆 薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 所述第二钝化层为第二无机绝缘层， 该第二无机绝缘层包括氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧 化钕薄膜； 所述第三钝化层为第三无机绝缘层， 该第三无机绝缘层包括氮化 硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第四钝化层为第一有 机绝缘层， 该第一有机绝缘层包括树脂系绝缘薄膜或亚克力系绝缘薄膜； 所 述第五钝化层为第四无机绝缘层， 该第四无机绝缘层包括氮氧化硅薄膜、 氧 化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝 薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝 薄膜、 氮化锆薄膜或氮化钽薄膜。
例如， 所述第一钝化层的厚度为 50nm〜600nm, 所述第二钝化层的厚度 为 50nm〜650nm; 所述第三钝化层的厚度为 50nm〜500nm; 所述第四钝化层 的厚度为 0.5μη！〜 2.5μιη; 所述第五钝化层的厚度为 20nm〜450nm。
对于该阵列基板， 例如， 所述栅极绝缘层位于所述有源层和所述栅极之 间； 所述栅极绝缘层包括至少一层无机绝缘薄膜。
例如， 所述栅极绝缘层为一层， 为第一栅极绝缘层； 所述第一栅极绝缘 层为氧化硅薄膜、 三氧化二钇薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化硅薄膜、 氮 氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜。
例如， 所述第一栅极绝缘层为经过退火工艺处理的绝缘层。
例如， 所述第一栅极绝缘层的厚度为 50 nm〜500nm。
例如，所述栅极绝缘层为两层， 包括第一栅极绝缘层和第二栅极绝缘层； 所述第一栅极绝缘层贴近栅极， 所述第二栅极绝缘层贴近所述有源层； 所述 第一栅极绝缘层为氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽 薄膜、 氮氧化钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄 膜或氮化钽薄膜； 所述第二栅极绝缘层为氧化硅薄膜、 三氧化二钇薄膜、 氧 化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄 膜、 氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化 钇薄膜或氮氧化钕薄膜。
例如， 所述第一栅极绝缘层为经过退火工艺处理的绝缘层； 所述第二栅 极绝缘层为经过退火工艺处理的绝缘层。
例如， 所述第一栅极绝缘层的厚度为 50nm-600nm; 所述第二栅极绝缘 层的厚度为 50nm-650nm。
例如， 所述栅极绝缘层为三层， 包括第一栅极绝缘层、 第二栅极绝缘层 和第三栅极绝缘层； 所述第一栅极绝缘层贴近栅极， 所述第三绝缘层贴近有 源层， 所述第二栅极绝缘层位于第一栅极绝缘层和第三栅极绝缘层中间； 所 述第一栅极绝缘层为氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化 钽薄膜、 氮氧化钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆 薄膜或氮化钽薄膜； 所述第二栅极绝缘层为氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜或者氮氧化钕薄膜； 所述第三 绝缘绝缘层为氧化硅薄膜、 三氧化二钇薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧 化锆薄膜、 氧化钽薄膜， 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化 硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜或者氮氧化钕薄膜。
例如， 所述第一栅极绝缘层的厚度为 50nm-600nm; 所述第二栅极绝缘 层的厚度为 50nm-650匪； 所述第三栅极绝缘层的厚度为 20nm-600nm。
例如， 所述栅极和 /或所述源极、 漏极为铜电极或铜合金电极。
再一方面， 本发明提供一种阵列基板的制作方法， 包括： 制作钝化层的 步骤， 所述钝化层包括至少一层无机绝缘薄膜或有机绝缘薄膜。
对于该制作方法， 例如， 所述钝化层为一层， 为第一钝化层， 所述钝化 层的制作方法可以包括：
步骤 S 11 , 釆用无机绝缘材料或有机绝缘材料形成第一钝化层； 步骤 S12, 对第一钝化层进行退火工艺处理。
例如， 所述退火工艺为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第一钝化层进行脱氢处理； 其中， 退火腔室温度为 200°C〜350°C , 退火时 间为 15min〜90min。
对于该制作方法， 例如， 所述钝化层为两层， 包括第一钝化层和第二钝 化层；所述第一钝化层靠近所述薄膜晶体管；所述钝化层制作方法可以包括： 步骤 S21、 釆用无机绝缘材料形成第一钝化层；
步骤 S22、 对第一钝化层进行退火工艺处理；
步骤 S23、 釆用无机绝缘材料或有机绝缘材料形成第二钝化层； 步骤 S24、 对第二钝化层进行退火工艺处理。
例如， 所述退火工艺为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第一钝化层和第二钝化层分别进行脱氢工艺； 其中， 退火腔室温度为 200 °C〜350°C , 退火时间为 15min〜90min。
对于该制作方法， 例如， 所述钝化层为三层， 包括依次设置的第一钝化 层、 第二钝化层和第三钝化层； 其中， 所述第一钝化层贴近所述薄膜晶体管； 所述钝化层制作方法包括：
步骤 S31、 釆用无机绝缘材料形成第一钝化层；
步骤 S32、 釆用无机绝缘材料或有机材料形成第二钝化层；
步骤 S33、 釆用无机绝缘材料或有机材料形成第三钝化层。
对于该制作方法， 例如， 所述钝化层为四层， 包括依次设置的第一钝化 层、 第二钝化层、 第三钝化层和第四钝化层， 其中所述第一钝化层贴近所述 薄膜晶体管； 所述钝化层制作方法包括：
步骤 S41、 釆用无机绝缘材料形成第一钝化层；
步骤 S42、 釆用无机绝缘材料形成第二钝化层；
步骤 S43、 釆用无机绝缘材料形成第三钝化层；
步骤 S44、 釆用有机绝缘材料形成第四钝化层。 对于该制作方法， 例如， 所述钝化层为五层， 包括依次设置的第一钝化 层、 第二钝化层、 第三钝化层、 第四钝化层和第五钝化层； 其中， 所述第一 钝化层贴近所述薄膜晶体管； 所述钝化层制作方法包括：
步骤 S51、 釆用无机绝缘材料形成第一钝化层；
步骤 S52、 釆用无机绝缘材料形成第二钝化层；
步骤 S53、 釆用无机绝缘材料形成第三钝化层；
步骤 S54、 釆用有机绝缘材料形成第四钝化层；
步骤 S55、 釆用无机绝缘材料形成第五钝化层。
再一方面， 本发明还提供一种显示装置， 包括上述的阵列基板。
本发明实施例提供的阵列基板及其制作方法、 显示装置， 该阵列基板中 的栅极绝缘层和钝化层通过釆用分层结构结合退火工艺、 分层结构可最大程 度的钝化层中以及外界环境中含氢的基团， 可有效避免氢基团对氧化物半导 体的影响， 最大程度地提高整个 TFT器件的稳定性， 提高最终产品的良率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中氧化物薄膜晶体管阵列基板制作方法的流程框图； 图 2A-2M分别为现有技术中制作氧化物薄膜晶体管阵列基板的第一至 第十三示意图；
图 3为本发明实施例一阵列基板结构示意图；
图 4为本发明实施例一阵列基板制作方法流程图；
图 5为本发明实施例三阵列基板结构示意图；
图 6为本发明实施例三阵列基板结构另一示意图；
图 Ί为本发明实施例三阵列基板制作方法流程图；
图 8为本发明实施例五阵列基板结构示意图；
图 9为本发明实施例五阵列基板制作方法流程图；
图 10为本发明实施例七阵列基板结构示意图；
图 11为本发明实施例七阵列基板制作方法流程图； 图 12为本发明实施例九阵列基板结构示意图；
图 13为本发明实施例九阵列基板制作方法流程图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
在后续实施例及其对应的附图中均以 TN (扭转向列 )型 LCD的阵列基 板为例， 来介绍本发明所提供的改进方案， 但本发明不限于此。
本发明实施例的阵列基板例如包括多条栅线和多条数据线， 这些栅线和 数据线彼此交叉由此限定了排列为阵列的像素单元； 每个像素单元可以包括 作为开关元件的薄膜晶体管和像素电极。 例如， 每个像素单元的薄膜晶体管 的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线电连接或一体 形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述主要针对单个 或多个像素单元进行， 但是其他像素单元可以相同地形成。
实施例一
如图 3所示， 本实施例提供的阵列基板为薄膜晶体管的栅极层位于底层 的阵列基板结构（即底栅型）。该阵列基板包括：位于基板 401上的栅极 402, 分别位于栅极 402上的栅极绝缘层 403和有源层 404、源漏电极层 406、像素 电极层 412和钝化层。 该栅极绝缘层 403位于栅极 402和有源层 404之间； 该钝化层位于源漏电极层 406和像素电极层 412之间。 源漏电极层 406包括 图形化的源极、漏极和数据线（或电源线 )。 由于钝化层位于源漏电极层 406 和像素电极层 412之间， 因此钝化层中的氢元素以及氢的复合物以及外界环 境中存在的氢元素以及氢的复合物容易通过源漏电极之间的沟道结构渗透到 氧化物半导体的有源层中， 这将对氧化物半导体性能造成一定的负面影响， 进而影响到整个器件的使用性能。 因此， 本实施例对钝化层的结构、 材质以 及制作工艺进行优化， 以最大程度地降低钝化层中的氢元素、 氢的复合物以 及来自外界环境中的氢元素以及氢的复合物对整个器件的影响， 进而提高整 个器件的稳定性和安全性。
有源层 404为氧化物半导体， 栅极和 /或源漏电极为铜、 铜合金或者铝、 铬、 相、 钛、 钕、 锰中的任一种及上述金属的合金和叠层结构。 所述源漏电 极包括薄膜晶体管的源极和漏极。
本实施例中钝化层为单层结构， 包括第一钝化层 407。该第一钝化层 407 可以为无机绝缘层， 包括二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化 铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜或氧化钕薄膜 等釆用无机绝缘材料的膜层。 该由无机绝缘材料制成的第一钝化层 407的厚 度可以为 50謹〜500謹。
当该第一钝化层 407的厚度为 50 nm〜500nm时，可以在有效避免含氢基 团对氧化物半导体的影响的同时， 保证在较短的时间内完成第一钝化层的制 备， 即保证生产效率。 如果第一钝化层 407的厚度太薄， 则起不到避免含氢 基团对氧化物半导体的影响的作用； 而如果第一钝化层的厚度过厚， 则需要 更长的成膜时间 （tact time ) , 造成生产效率下降。
另外， 该第一钝化层 407也可以为有机绝缘层， 包括树脂系绝缘膜、 亚 克力系绝缘膜等釆用有机绝缘材料的膜层。 该由有机绝缘材料制成的第一钝 化层的厚度可以为 0.5μη！〜 2.5μιη。
当该第一钝化层 407的厚度为 0.5μη！〜 2.5μιη时， 可以在有效避免含氢基 团对氧化物半导体的影响的同时， 保证在较短的时间内完成第一钝化层的制 备， 即保证生产效率。 如果第一钝化层的厚度太薄， 则起不到避免含氢基团 对氧化物半导体的影响的作用； 而如果第一钝化层的厚度过厚， 则需要更长 的成膜时间， 造成生产效率下降。
为了保证更好的器件特征， 本实施例中可以对第一钝化层 407进行退火 工艺处理 (即第一钝化层 407为经过退火工艺处理的钝化层 ) , 来降低钝化 层中氢元素及氢的复合物对氧化物半导体特征的影响， 进而达到了提升器件 稳定性的作用。
本实施例中， 第一钝化层 407除可以釆用二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸 其他无机绝缘材料形成的薄膜。 或者， 除可以釆用树脂系绝缘膜、 亚克力系 材料形成的薄膜。
在实际应用中， 由于无机材料成本较低， 且使用寿命较长， 若不考虑器 件柔性性能方面的需求， 该钝化层可釆用无机材料来制备； 由于有机材料自 身的柔性性能较好， 若待加工的器件需要强调柔性方面的因素， 该钝化层可 釆用有机材料来制备。
本实施例中的栅极绝缘层 403的结构可为一层、 两层或三层。 当第一栅 极绝缘层釆用一层结构时， 即将其称为第一栅极绝缘层。 该第一栅极绝缘层 为二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化铝薄膜或氧化钛薄膜。 该第一栅极绝缘层的厚度可以为 50 nm〜500nm。
当然， 本实施例中， 第一栅极绝缘层除可以釆用二氧化硅薄膜、 氮化硅 薄膜、 氮氧化硅薄膜、 氧化铝薄膜或氧化钛薄膜外， 还可以釆用与上述各物 质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
为了保证更好的器件特性， 在实施例中， 可以对第一栅极绝缘层进行退 火工艺 （即第一栅极绝缘层为经过退火工艺处理的绝缘层） ， 来降低栅极绝 缘层中氢元素及氢的复合物对氧化物半导体特性的影响。
当栅极绝缘层釆用两层结构时，包括第一栅极绝缘层和第二栅极绝缘层。 第一栅极绝缘层贴近栅极， 第二栅极绝缘层贴近有源层， 第一栅极绝缘层可 为氮化硅薄膜或氮氧化硅薄膜； 第二栅极绝缘层可为氧化硅薄膜、 三氧化二 钇薄膜或氮氧化硅薄膜。 该第一栅极绝缘层的厚度可为 50nm-600nm; 第二 栅极绝缘层的厚度可为 50nm-650nm。
当然， 本实施例中， 第一栅极绝缘层除可以釆用氮化硅薄膜或氮氧化硅 料形成的薄膜。 第二栅极绝缘层除可以釆用氧化硅薄膜、 三氧化二钇薄膜或 机绝缘材料形成的薄膜。
为了保证更好的器件特性， 在本实施例中， 可以对第一栅极绝缘层进行 退火工艺 （即第一栅极绝缘层为经过退火工艺处理的绝缘层） ， 来降低栅极 绝缘层中氢元素及氢的复合物对氧化物半导体特性的影响。 在本实施例中， 为了进一步实现更好的技术效果，可以对第二栅极绝缘层进行退火工艺处理。 产生的不良。 第二栅极绝缘层的作用是可以很好的实现与氧化物半导体的匹 配， 达到提高器件性能的作用。 由于第二栅极绝缘层的材料多为氧化物绝缘 层， 其对 Η+, ΟΗ·等基团的防扩散的能力比较差， 所以在制作完第一栅极绝 缘层时， 优选地对其进行退火工艺处理， 以降低第一栅极绝缘层中可能发生 断裂扩散的 H+, Off等基团， 进而达到了提升器件稳定性的作用。
当栅极绝缘层釆用三层结构时， 包括第一栅极绝缘层、 第二栅极绝缘层 和第三栅极绝缘层。 第一栅极绝缘层贴近栅极， 第三栅极绝缘层贴近有源层 第二栅极绝缘层位于第一栅极绝缘层和第三栅极绝缘层之间。 第一栅极绝缘 层可为氮化硅薄膜或氮氧化硅薄膜等无机绝缘薄膜； 第二栅极绝缘层可为氮 氧化硅薄膜等无机绝缘薄膜； 第三绝缘绝缘层可为氧化硅薄膜、 氧化铝薄膜 或氧化钛薄膜等无机绝缘薄膜。
第一栅极绝缘层的厚度可为 50nm-600nm; 第二栅极绝缘层的厚度可为 50nm-650nm; 第三栅极绝缘层的厚度可为 20nm-600nm。
本实施例中， 栅极可以为铜或铜合金， 还可以为 Mo、 Mo-Al-Mo合金、 Mo/Al-Nd/Mo叠成结构的电极、 纯 A1及其合金、 Mo/Nd/Cu, Ti/Cu等其他 金属。 当然， 使用铜或铜合金作为栅极， 具有优化构图工艺、提高器件性能、 降低成本等作用。
本实施例中，第一栅极绝缘层除可以釆用氮化硅薄膜或氮氧化硅薄膜夕卜， 薄膜。
本实施例中， 第二栅极绝缘层除可以釆用氮氧化硅薄膜外， 还可以釆用 与上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第三栅极绝缘层除可以釆用氧化硅薄膜、 氧化铝薄膜或氧 缘材料形成的薄膜。
本实施例中， 第一栅极绝缘层釆用氮化硅或氮氧化硅薄膜等无机绝缘材 料， 由于该材料直接与氧化物半导体层接触时会造成氧化物半导体层的性能 下降， 但它却可以较好地遏制与栅极金属（尤其是当釆用铜及其合金作为栅 极时）接触产生不良现象， 因此设置该第一栅极绝缘层紧贴栅极但远离有源 层。 将第二栅极绝缘层设置在中间层， 由于由氮氧化硅薄膜等无机绝缘材料 制成的第二栅极绝缘层自身含有的 H+, OH-等基团比较少， 同时对 H+, OH- 等基团具有一定的防渗透能力， 可以很好的遏制 H+, OH-等基团向氧化物半 导体层进行扩散， 达到了提高器件稳定性的目的。 同时， 为了最大程度的提 高器件的特性， 将第三栅极绝缘层与氧化物半导体紧贴， 可以较好地实现与 氧化物半导体的匹配， 达到提高器件稳定性的作用。
在本实施例中， 当钝化层釆用单层结构时，栅极绝缘层的结构不受限制， 可以为一层、 两层或三层结构， 具体分层的选择可根据实际需求而定。
下面以单层的钝化层和单层的栅极绝缘层来描述制作阵列基板的方法。 结合图 3和图 4, 该方法的示例包括如下步骤。
步骤 S101 , 在基板上形成栅极金属薄膜。
例如， 在玻璃基板 401上形成栅极金属薄膜， 栅极金属薄膜通常釆用测 控溅射的方法来制备，其材料可选用铜或其合金，厚度可以为 200nm-350nm, 以使其方块电阻保持在一个相对比较低的水平。
步骤 S102, 对栅极金属薄膜进行图形化。
通过湿法刻蚀方式， 对栅极金属薄膜进行图形化形成栅线和栅极 402; 此外， 如果需要， 还可以同时制作出公共电极线。
步骤 S103 , 在栅极上形成第一栅极绝缘层。
本实施例中的栅极绝缘层为一层， 可以釆用二氧化硅薄膜、 氮化硅、 氮 氧化硅、 氧化铝、 氧化钛或其他无机绝缘材料形成第一栅极绝缘层。 该第一 栅极绝缘层的厚度可以为 50 nm〜500nm。
步骤 S104, 对第一栅极绝缘层进行退火工艺处理。
例如， 该退火工艺可优化为： 釆用高温退火炉对第一栅极绝缘层进行脱 氢化，退火釆用氮气、真空或稀有气体进行保护，退火温度可以为 250°C〜450 °C , 退火时间可以为 20 min〜l 50min。
或者， 该退火工艺还可以优化为： 在 PECVD设备中加入真空的加热腔 室， 气压可以为 l(T4Pa〜lPa, 对第一栅极绝缘层进行脱氢工艺； 退火腔室温 度可以为 350°C〜480°C , 退火时间可以为 10min〜30min。 艺， 可以缩短工艺时间， 提高产品的产量， 同时降低设备的资金投入。
步骤 S105, 在第一栅极绝缘层上形成氧化物半导体有源层。
氧化物半导体可釆用铟镓辞氧化物（ IGZO ) ,铟锡辞氧化物氧化（ ITZO ), 铟辞氧化物 （IZO )等以及上述几种物质的不同比例的配合物。
步骤 S106, 在制作完上述的氧化物半导体有源层后， 在其上形成刻蚀阻 挡层。
步骤 S107, 在完成上述步骤的基板上形成 TFT器件的源漏电极层。 源 漏电极层 406中的源极和漏极分别与氧化物半导体有源层 404的两侧相连接， 且彼此相对设置。
步骤 S108, 在完成上述步骤的基板上形成第一钝化层。
该第一钝化层 407可以为二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜或氧化钕 薄膜等无机绝缘材料。 该第一钝化层的厚度可以为 50 nm〜500nm。
或者， 该第一钝化层 407可为树脂系绝缘膜、 亚克力系绝缘膜等有机绝 缘材料。 第一钝化层 407的厚度可以为 0.5μη！〜 2.5μιη。
步骤 S109, 对第一钝化层进行退火工艺处理。
由于在步骤 S109之前， 氧化物半导体有源层已经制作完毕； 为了尽量 减小退火工艺对有源层的影响， 因此步骤 S109 中的退火工艺所釆用的温度 不能太面。
退火工艺方法可为： 在 PECVD设备中加入氮气或空气的加热腔室， 对 第一钝化层进行脱氢工艺； 退火腔室温度可以为 200°C〜350°C , 退火时间可 以为 15min〜90min。
当然， 除了上述给出的退火工艺条件， 也可根据实际情况， 选择已有的 其他退火方式， 只需对第一钝化层进行脱氢处理即可。
步骤 S110, 在完成上述步骤的基板上形成像素电极层。
本实施例中除栅极绝缘层和钝化层釆用分层结构外， 其他膜层结构的制 备工艺步骤均可以通过常规技术手段来实现， 这些并非本实施例的设计点， 此处不赘。
本实施例中栅极绝缘层和钝化层选用特定材料， 可降低栅极绝缘层和钝 化层以及以外环境中掺杂的氢元素及氢的复合物对氧化物半导体特性的影 响。 本实施例中的栅极金属除了 Cu及其合金， 还可以为通常所釆用的 Mo、 Mo-Al-Mo合金、 Mo/Al-Nd/Mo叠成结构的电极、纯 A1及其合金、 Mo/Nd/Cu, Ti/Cu等金属。
实施例二
本实施例与实施例一存在的区别在于： 本实施例提供的阵列基板中的薄 膜晶体管的栅极位于有源层的上方，即顶栅型的阵列结构。本实施例仍以 TN 型结构为例， 阵列基板上的钝化层位于栅极和像素电极层之间。 具体该钝化 层的结构及制作方法与实施例一中钝化层的结构及制作方法相同， 在此不再 赘述。
实施例三
如图 5和 6所示， 本实施例提供的阵列基板具有薄膜晶体管的栅极位于 底层的阵列基板结构 （即底栅型） 。
本实施例提供的阵列基板包括： 位于基板 401上的栅极 402, 分别位于 栅极上的栅极绝缘层 403和有源层 404、 源漏电极层 406、 像素电极层 412 和钝化层。 该栅极绝缘层 403位于栅极 402和有源层 404之间； 该钝化层位 于源漏电极层 406和像素电极层 412之间。
有源层 404为氧化物半导体， 栅极和源漏电极可以为铜、 铜合金、 铝、 铝合金、 铬、 相、 钛、 钕或锰， 上述金属的合金或叠层结构。 该钝化层为两 层结构， 包括第一钝化层 407和第二钝化层 408, 该第一钝化层 407贴近源 漏电极层 406, 第二钝化层 408贴近像素电极层 412; 所述第一钝化层 407 为第一无机绝缘层， 该第一无机绝缘层可以包括氧化硅薄膜、 氧化铝薄膜、 三氧化二钇薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜或氮 氧化硅薄膜其中， 第一钝化层的厚度可以为 50nm〜600nm。
第二钝化层 408为第二无机绝缘层或第一有机绝缘层； 该第二无机绝缘 层可以包括氮化硅薄膜、 三氧化二钇薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧 化钽薄膜、 钛酸钡薄膜或氧化钕薄膜； 第一有机绝缘层可以包括树脂系绝缘 膜或亚克力系绝缘膜。
当第二钝化层为无机绝缘层时，第二钝化层的厚度可以为 50 nm〜500nm; 当第二钝化层为有机绝缘层时，所述第二钝化层的厚度可以为 0.5μη！〜 2.5μιη。 第一钝化层和所述第二钝化层均为经过退火工艺处理的钝化层。 参考图 6。
上述各结构层的厚度， 可以在有效避免含氢基团对氧化物半导体的影响 的同时， 保证在较短的时间内完成第一钝化层的制备， 即保证生产效率。 如 果设置的厚度太薄， 则起不到避免含氢基团对氧化物半导体的影响的作用； 而如果设置的厚度过厚， 则需要更长的成膜时间（tact time ) , 造成生产效率 下降。
本实施例中， 第一钝化层 407除可以釆用上述列举的无机绝缘材料外， 薄膜。
本实施例中， 第二钝化层 408除可以釆用上述列列举的第二无机绝缘材 形成的薄膜。 或者， 该第二钝化层除可以釆用树脂系绝缘膜或亚克力系绝缘 膜等第一有机绝缘材料外， 还可以釆用与上述各物质的材料特性相同或相近 的其他有机绝缘材料形成的薄膜。
需要说明的是， 本实施例中的第一钝化层的材料较优选择氧化物， 该氧 化物可较好地与沟道位置处的氧化物半导体层进行有效接触； 第二钝化层则 优选氮化物， 氮化物可有效防止来自外界的氢元素或氢的复合物氧化物半导 体层的干扰。
在实际材料的选择时， 尽可能将第一钝化层和第二钝化层选择不同的材 料。 当第一钝化层和第二钝化层使用同一种材料时， 可以对材料进行结构设 计， 设置贴近氧化物半导体一侧的钝化层进行富氧处理， 提高该物质中氧含 量的比重， 且设置远离氧化物半导体层的钝化层具有阻挡外界氢原子及水汽 对薄膜渗透的性能， 由此得到需要的技术效果。
本实施例中， 第一钝化层 407可以釆用氧化硅薄膜、 氧化铝薄膜、 三氧 化二钇或氮氧化硅薄膜等第一无机绝缘材料， 这些材料自身含有的 H+, OH- 等基团比较少， 同时对 H+, OH-等基团具有一定的防渗透能力， 可以很好的 遏制 H+, OH-等基团向氧化物半导体层进行扩散， 达到了提高器件稳定性的 目的， 避免器件失效； 为了最大程度的提高器件的特性， 可以将氮化硅、 三 氧化二钇、 氮氧化硅等第二无机绝缘材料或树脂系绝缘膜或亚克力系绝缘膜 等第一有机绝缘材料制成的第二钝化层与像素电极层紧贴， 这样可以较好地 提高与像素电极层的附着力， 达到提高器件稳定性的作用。
下面以两层的钝化层和单层的栅极绝缘层来描述制作阵列基板的方法。 如图 7所示， 该方法的示例包括如下步骤。
步骤 S201 , 在基板上形成栅极金属薄膜。
例如， 在玻璃基板 401上形成栅极金属薄膜层， 栅极金属薄膜通常釆用 测控溅射的方法来制备， 其材料可选用铜及其合金， 厚度一般釆用 200nm-350nm, 令其方块电阻保持在一个相对比较低的水平。
步骤 S202, 对栅极金属薄膜进行图形化。
通过湿法刻蚀方式， 对栅极金属薄膜进行图形化形成栅线和栅极 402; 此外， 如果需要， 还可以同时制作出公共电极线。
步骤 S203, 在栅极上形成第一栅极绝缘层。
例如，在栅极层上釆用氮化硅薄膜或氮氧化硅薄膜形成第一栅极绝缘层， 该第一栅极绝缘层的厚度可以为 50nm-600nm。
步骤 S204: 对第一栅极绝缘层进行退火工艺处理。
在完成第一栅极绝缘层后实施退火工艺， 以最大程度降低第一栅极绝缘 层中可能发生断裂扩散的 H+, OH-等基团 , 进而达到了提升器件稳定性的作 用。
步骤 S205, 在第一栅极绝缘层上形成氧化物半导体有源层， 并图形化。 通常， 氧化物半导体可釆用铟镓辞氧化物（IGZO ) ， 铟锡辞氧化物氧化 ( ITZO ) , 铟辞氧化物 （IZO )等以及上述几种物质的不同比例的配合物。 主要的制作方法包括磁控溅射沉积（Sputter ) 以及溶液法等。 有源层氧化物 半导体通常釆用的刻蚀方法有两种， 一种为湿法刻蚀， 另一种为干法刻蚀； 现在广泛使用的是湿法刻蚀， 可以艮好的控制刻蚀精度。 通过刻蚀的方法对 氧化物半导体层进行图形化。 以下各个实施例与此相同， 因此不再赘述。
步骤 S206, 在制作完上述的氧化物半导体有源层后， 在其上形成刻蚀阻 挡层。
步骤 S207, 在完成上述步骤的基板上形成 TFT器件的源漏电极。
步骤 S208, 在完成上述步骤的基板上形成第一钝化层。
第一钝化层 407为第一无机绝缘层， 该第一无机绝缘层可以包括氧化硅 薄膜、 氧化铝薄膜、 三氧化二钇薄膜、 氧化锆薄膜、 氧化钽薄膜， 钛酸钡薄 膜、 氧化钕薄膜或氮氧化硅薄膜； 该第一钝化层的厚度可以为 50nm〜600nm。
步骤 S209, 对第一钝化层进行退火工艺处理。
退火工艺方法可以为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第一钝化层进行脱氢工艺； 退火腔室温度可以为 200°C〜350°C , 退火时间 可以为 15min〜90min。
步骤 S210, 在第一钝化层上形成第二钝化层。
第二钝化层 408为第二无机绝缘层或第一有机绝缘层， 该第二无机绝缘 层可以包括氮化硅薄膜、 三氧化二钇薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧 化钽薄膜， 钛酸钡薄膜或氧化钕薄膜。 该第二钝化层的厚度可以为 50 nm〜500nm。 该第一有机绝缘层可以包括树脂系绝缘膜或亚克力系绝缘膜。 由有机绝缘层薄膜制成的第二钝化层的厚度可以为 0.5μη！〜 2.5μιη。
步骤 S211 , 对第二钝化层进行退火工艺处理。
退火工艺方法可以为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第二钝化层进行脱氢工艺； 退火腔室温度可以为 200°C〜350°C , 退火时间 可以为 15min〜90min。
步骤 S212, 在完成上述步骤的基板上形成像素电极层。
本实施例中除栅极绝缘层和钝化层釆用分层结构外， 其他膜层结构的制 备工艺步骤均可以通过常规技术手段来实现,但是这并非本实施例的设计点， 此处不赘。 本实施例中的栅极绝缘层除了釆用单层结构之外， 还可以釆用如 实施例 1中所描述的两层或三层结构。
实施例四 本实施例与实施例三存在的区别在于： 本实施例提供的阵列基板为薄膜 晶体管的栅极层位于顶层的阵列基板， 即顶栅型阵列基板。 该钝化层包括第 一钝化层和第二钝化层， 所述第一钝化层贴近栅极， 所述第二钝化层贴近像 素电极层， 该钝化层的结构、 材料及制作方法与实施例 3钝化层的结构、 材 料及制作方法相同， 形成各结构层的工艺方法与实施例三相同， 在此不再赘 述。
实施例五
如图 8所示， 本实施例提供的阵列基板具有为薄膜晶体管的栅极层位于 底层的阵列基板结构 （即底栅型） 。 本实施例提供的阵列基板包括： 位于基 板 401上的栅极 402, 分别位于栅极 402上的栅极绝缘层 403和有源层 404、 源漏电极层 406、像素电极层 412和钝化层。该栅极绝缘层 403位于栅极 402 和有源层 404之间； 该钝化层位于源漏电极层和像素电极层之间。
有源层 404为氧化物半导体，栅极为铜或铜合金，该钝化层为三层结构， 包括第一钝化层 407、 第二钝化层 408和第三钝化层 409, 第一钝化层 407 贴近源漏电极层 406, 第三钝化层 409贴近像素电极层 412; 第二钝化层 408 位于第一钝化层 407和第三钝化层 409之间。
第一钝化层 407为第一无机绝缘层，该第一无机绝缘层包括氧化硅薄膜， 氧化铝薄膜， 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄 膜或氧化钕薄膜等无机绝缘材料； 所述第一钝化层的厚度可以为 50謹〜600謹。
第二钝化层 408为第二无机绝缘层或第一有机绝缘层， 该第二无机绝缘 层可以包括氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或 氮氧化钕薄膜等无机绝缘材料， 该第一有机绝缘层可以包括树脂系绝缘薄膜 或亚克力系绝缘薄膜； 该第三钝化层 409为第三无机绝缘层或第二有机绝缘 层， 该第三无机绝缘层可以包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮 化钽薄膜等无机绝缘材料， 第二有机绝缘层可以包括树脂系绝缘薄膜或亚克 力系绝缘薄膜。
在第二钝化层 408 为无机绝缘层时， 第二钝化层的厚度可以为 50nm〜650nm; 在第二钝化层为有机绝缘层时， 所述第二钝化层的厚度可以 为 0.5μηι〜2.5μηι。 在所述第三钝化层 409为无机绝缘层时， 所述第三钝化层 409的厚度可以为 50 nm〜500nm; 在所述第三钝化层 409为有机绝缘层时， 所述第三钝化层 408的厚度可以为 0.5μη！〜 2.5μιη。
贴近源漏电极层 406的第一钝化层 407所釆用的氧化物无机绝缘材料有 利于与氧化物半导体有源层之间的贴合， 增强器件的稳定性； 处于中间层的 第二钝化层 408 所釆用的氮氧化合物等无机绝缘材料， 由于其自身含有的 Η+, ΟΗ-等基团比较少， 同时对 Η+, ΟΗ-等基团具有一定的吸收能力， 可以 很好的遏制 Η+, ΟΗ-等基团向氧化物半导体层进行扩散， 达到了提高器件稳 定性的目的， 避免器件失效； 第三钝化层 409所釆用的材料可防止外界氢环 境对器件的影响， 进一步起到提高器件稳定性的作用。
上述各结构层的厚度， 可以在有效避免含氢基团对氧化物半导体的影响 的同时， 保证在较短的时间内完成第一钝化层的制备， 即保证生产效率。 如 果设置的厚度太薄， 则起不到避免含氢基团对氧化物半导体的影响的作用； 而如果设置的厚度过厚， 则需要更长的成膜时间（tact time ) , 造成生产效率 下降。
本实施例中， 第一钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第二钝化层除可以釆用上述列举的材料外， 还可以釆用与 本实施例中， 第三钝化层除可以釆用上述列举的材料外， 还可以釆用与 本实施例中栅极绝缘层的结构与实施例一中栅极绝缘层的结构相同， 在 此不再赘述。
下面以三层的钝化层和单层的栅极绝缘层来描述制作阵列基板的方法。 如图 9所示， 该方法的示例包括如下步骤。
步骤 S301 , 在基板上形成栅极金属薄膜层。
例如， 在玻璃基板 401上形成栅极金属薄膜层， 该栅极金属薄膜通常釆 用测控溅射的方法来制备， 其材料可选用铜或其合金， 厚度一般可釆用 200nm-350nm, 令其方块电阻保持在一个相对比较低的水平。
步骤 S302, 对栅极层进行图形化。
例如， 通过湿法刻蚀方式， 对栅极金属薄膜进行图形化形成栅线和栅极 402; 此外， 如果需要， 还可以同时制作出公共电极线。
步骤 S303 , 在栅极上形成第一栅极绝缘层。
例如，在栅极层上釆用氮化硅薄膜或氮氧化硅薄膜形成第一栅极绝缘层， 该第一栅极绝缘层的厚度可以为 50nm-600nm。
步骤 S304: 对第一栅极绝缘层进行退火工艺处理。
在完成第一栅极绝缘层后实施退火工艺， 以最大程度降低第一栅极绝缘 层中可能发生断裂扩散的 H+, OH-等基团， 进而达到了提升器件稳定性的作 用。
步骤 S305, 在第一栅极绝缘层上形成氧化物半导体有源层， 并图形化。 通常， 氧化物半导体可釆用铟镓辞氧化物（IGZO ) ， 铟锡辞氧化物氧化
( ITZO ) , 铟辞氧化物 （IZO )等以及上述几种物质的不同比例的配合物。
步骤 S306, 在完成上述的有源层氧化物半导体后， 在其上形成刻蚀阻挡 层。
步骤 S307, 在完成上述步骤的基板上形成 TFT器件的源漏电极。
步骤 S308, 在完成上述步骤的基板上形成第一钝化层。
步骤 S309, 在第一钝化层上形成第二钝化层。
步骤 S310, 在第二钝化层上形成第三钝化层。
上述步骤中， 第一钝化层 407为第一无机绝缘层， 该第一无机绝缘层可 以包括氧化硅薄膜， 氧化铝薄膜， 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧 化钽薄膜、 钛酸钡薄膜或氧化钕薄膜等无机绝缘材料； 所述第一钝化层的厚 度可以为 50nm〜600nm。 第二钝化层 408可以为第二无机绝缘层或第一有机 绝缘层， 该第二无机绝缘层可以包括氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化 锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜等无机绝缘材料， 该第一有机绝缘层 可以包括树脂系绝缘薄膜或亚克力系绝缘薄膜； 该第三钝化层 409可以为第 三无机绝缘层或第二有机绝缘层； 在第二钝化层 408为无机绝缘层时， 第二 钝化层的厚度可以为 50nm〜650nm; 在第二钝化层为有机绝缘层时， 所述第 二钝化层的厚度可以为 0.5μη！〜 2.5μιη。
第三钝化层 409为第三无机绝缘层或第二有机绝缘层， 第三无机绝缘层 可以包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜等无机绝缘材 料， 第二有机绝缘层可以包括树脂系绝缘薄膜或亚克力系绝缘薄膜。 在所述第三钝化层 409为无机绝缘层时， 所述第三钝化层 409的厚度可 以为 50 nm〜500nm; 在所述第三钝化层 409为有机绝缘层时， 所述第三钝化 层 408的厚度可以为 0.5μη！〜 2.5μιη。
步骤 S311 , 在制作好上述步骤的基板上形成像素电极层。
本实施例中除栅极绝缘层和钝化层釆用分层结构外， 其他膜层结构的制 备工艺步骤均可以通过常规技术手段来实现， 并非本实施例的设计点， 此处 不赘。 本实施例中的栅极绝缘层除了釆用单层结构之外， 还可以釆用如实施 例 1中所描述的两层或三层结构。
实施例六
本实施例与实施例五存在的区别在于： 本实施例提供的阵列基板为薄膜 晶体管的栅极层位于顶层的阵列基板， 即顶栅型阵列基板。 该钝化层包括第 一钝化层、 第二钝化层和第三钝化层， 所述第一钝化层贴近栅极层， 所述第 三钝化层贴近像素电极层， 所述第二钝化层位于第一钝化层和第三钝化层之 间。 该钝化层的结构、 材料及制作方法与实施例五钝化层的结构、 材料及制 作方法相同， 且具体形成各结构层的工艺方法与实施例五相同， 在此不再赘 述。
实施例七
如图 10所示，本实施例提供的阵列基板为薄膜晶体管的栅极层位于底层 的阵列基板结构 (即底栅型 )。本实施例提供的阵列基板包括： 位于基板 401 上的栅极 402,分别位于栅极上的栅极绝缘层 403和有源层 404、源漏电极层
406、 像素电极层 412和钝化层。 该栅极绝缘层 403位于栅极 402和有源层
404之间； 该钝化层位于源漏电极层和像素电极层之间。
有源层 404为氧化物半导体，栅极为铜或铜合金，该钝化层为四层结构， 包括第一钝化层 407、 第二钝化层 408、 第三钝化层 409和第四钝化层 410, 第一钝化 407层贴近源漏电极层 406, 所述第四钝化层 410贴近像素电极层
412; 第二钝化层 408和第三钝化层 409位于第一钝化层 407和第四钝化层
410之间。
所述第一钝化层 407为第一无机绝缘层， 该第一无机绝缘层可以包括氧 化硅薄膜， 氧化铝薄膜、 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或 氮氧化钕薄膜； 所述第二钝化层 408为第二无机绝缘层， 该第二无机绝缘层 可以包括氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 所 述第三钝化层 409为第三无机绝缘层， 该第三无机绝缘层可以包括氮化硅薄 膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第四钝化层 410为第一有 机绝缘层，该第一有机绝缘层可以包括树脂系绝缘薄膜或亚克力系绝缘薄膜。
第一钝化层 407的厚度可以为 50nm〜600nm, 第二钝化层 408的厚度可 以为 50nm〜650匪； 所述第三钝化层 409的厚度可以为 50 nm〜500nm; 第四 钝化层的厚度可以为 0.5μη！〜 2.5μιη。
上述各结构层的厚度， 可以在有效避免含氢基团对氧化物半导体的影响 的同时， 保证在较短的时间内完成第一钝化层的制备， 即保证生产效率。 如 果设置的厚度太薄， 则起不到避免含氢基团对氧化物半导体的影响的作用； 而如果设置的厚度过厚， 则需要更长的成膜时间（tact time ) , 造成生产效率 下降。
本实施例中， 第一钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第二钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第三钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第四钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他有机绝缘材料形成的薄膜。
本实施例中， 第一钝化层釆用氧化硅薄膜， 氧化铝薄膜、 三氧化二钇或 氮氧化硅薄膜等无机绝缘材料， 结合第二钝化层釆用氧化硅薄膜等无机绝缘 材料以及第三钝化层釆用氮化硅薄膜等无机绝缘材料， 由于其自身含有的 H+, OH-等基团比较少， 同时对 H+, OH-等基团具有一定的防渗透能力， 可 以很好的遏制 H+, OH-等基团向氧化物半导体层进行扩散， 达到了提高器件 稳定性的目的， 避免器件失效； 为了最大程度的提高器件的特性， 将第四钝 化层与像素电极层紧贴， 这样可以较好地提高与像素电极层的附着力， 达到 提高器件稳定性的作用。
本实施例中栅极绝缘层的结构与实施例 1中栅极绝缘层的结构相同， 在 此不再赘述。
下面以四层的钝化层和单层的栅极绝缘层来描述制作阵列基板的方法。 如图 11所示， 该方法的示例包括如下步骤。
步骤 S401 , 在基板上形成栅极金属薄膜层。
例如， 在玻璃基板 401上形成栅极金属薄膜层， 栅极金属薄膜通常釆用 测控溅射的方法来制备， 其材料可选用铜或其合金， 厚度一般釆用 200nm-350nm, 令其方块电阻保持在一个相对比较低的水平。
步骤 S402, 对栅极金属薄膜进行图形化。
例如， 通过湿法刻蚀方式， 对栅极金属薄膜进行图形化形成栅线和栅极 402; 此外， 如果需要， 还可以同时制作出公共电极线。
步骤 S403 , 在栅极上形成第一栅极绝缘层。
例如，在栅极层上釆用氮化硅薄膜或氮氧化硅薄膜形成第一栅极绝缘层， 该第一栅极绝缘层的厚度可以为 50nm-600nm。
步骤 S404: 对第一栅极绝缘层进行退火工艺处理。
在完成第一栅极绝缘层后实施退火工艺， 以最大程度降低第一栅极绝缘 层中可能发生断裂扩散的 H+, OH-等基团， 进而达到了提升器件稳定性的作 用。
步骤 S405, 在第一栅极绝缘层上形成氧化物半导体有源层 404, 并图形 化。
通常， 氧化物半导体可釆用铟镓辞氧化物（IGZO ) ， 铟锡辞氧化物氧化
( ITZO ) , 铟辞氧化物 （IZO )等以及上述几种物质的不同比例的配合物。
步骤 S406, 在完成上述的有源层氧化物半导体后， 在其上形成刻蚀阻挡 层。
步骤 S407, 在完成上述步骤的基板上形成 TFT器件的源漏电极。
步骤 S408, 在完成上述步骤的基板上形成第一钝化层。
例如， 所述第一钝化层 407为第一无机绝缘层， 该第一无机绝缘层包括 氧化硅薄膜， 氧化铝薄膜、 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄 膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄 膜或氮氧化钕薄膜； 第一钝化层的厚度可以为 50nm〜600nm。
步骤 S409, 在第一钝化层上形成第二钝化层。 例如， 第二钝化层 408为第二无机绝缘层， 该第二无机绝缘层包括氮氧 化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 第二钝化层的厚 度可以为 50 650nm
步骤 S410, 在第二钝化层上形成第三钝化层。
例如， 第三钝化层为第三无机绝缘层， 该第三无机绝缘层包括氮化硅薄 膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 第三钝化层的厚度可以为 50 nm 500nm
步骤 S411 , 在第三钝化层上形成第四钝化层。
例如， 第四钝化层为第一有机绝缘层， 该第一有机绝缘层包括树脂系绝 缘薄膜或亚克力系绝缘薄膜； 所述第四钝化层的厚度可以为 0.5μη 2.5μιη 步骤 S412, 在制作好上述步骤的基板上形成像素电极层。
本实施例中除栅极绝缘层和钝化层釆用分层结构外， 其他膜层结构的制 备工艺步骤均可以通过常规技术手段来实现， 并非本实施例的设计点， 此处 不赘。 本实施例中的栅极绝缘层除了釆用单层结构之外， 还可以釆用如实施 例 1中所描述的两层或三层结构。
实施例八
本实施例与实施例七存在的区别在于： 本实施例提供的阵列基板为薄膜 晶体管的栅极层位于顶层的阵列基板， 即顶栅型阵列基板。 该钝化层包括第 一钝化层、 第二钝化层、 第三钝化层和第四钝化层， 所述第一钝化层贴近栅 极， 所述第四钝化层贴近像素电极层， 所述第二钝化层和第三钝化层位于第 一钝化层和第四钝化层之间， 具体该钝化层的结构、 材料及制作方法与实施 例七钝化层的结构、 材料及制作方法相同， 具体形成各结构层的工艺方法与 实施例七相同， 在此不再赘述。
实施例九
如图 12所示，本实施例提供的阵列基板为薄膜晶体管的栅极层位于底层 的阵列基板结构 (即底栅型 )。本实施例提供的阵列基板包括： 位于基板 401 上的栅极 402,分别位于栅极上的栅极绝缘层 403和有源层 404、源漏电极层 406、像素电极层 412和钝化层。 该栅极绝缘层位于栅极和有源层之间； 该钝 化层位于源漏电极层和像素电极层之间。
有源层 404为氧化物半导体，栅极为铜或铜合金，该钝化层为四层结构， 包括第一钝化层 407、 第二钝化层 408、 第三钝化层 409、 第四钝化层 410和 第五钝化层 411。
第一钝化层 407贴近源漏电极层 406, 第五钝化层 411贴近像素电极层 412; 所述第二钝化层 408、 第三钝化层 409和第四钝化层 410位于第一钝化 层和第五钝化层 411之间。
第一钝化层 407为第一无机绝缘层， 该第一无机绝缘层可以包括氧化硅 薄膜、 氧化铝薄膜、 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛 酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮 氧化钕薄膜； 所述第二钝化层 408为第二无机绝缘层， 该第二无机绝缘层可 以包括氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 所述 第三钝化层 409为第三无机绝缘层，该第三无机绝缘层可以包括氮化硅薄膜、 氮化铝薄膜、氮化锆薄膜或氮化钽薄膜；第四钝化层 410为第一有机绝缘层， 该第一有机绝缘层可以包括树脂系绝缘薄膜或亚克力系绝缘薄膜； 第五钝化 层 411为第四无机绝缘层， 该第四无机绝缘层可以包括氮氧化硅薄膜、 氧化 硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄 膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄 膜、 氮化锆薄膜或氮化钽薄膜。 第四钝化层釆用树脂系绝缘薄膜或亚克力系 绝缘薄膜等有机绝缘层材料，可有效增加阵列基板的开口率， 降低耦合电容, 同时具有降低端差的平坦化作用。 第五钝化层釆用氮氧化硅薄膜、 氧化硅薄 膜或氮化硅薄膜等无机绝缘层材料， 可加强钝化层与像素电极层之间的附着 力以及可有效防止有机绝缘层材料在工作过程中发生失效的问题。
第一钝化层的厚度可以为 50nm〜600nm , 第二钝化层的厚度可以为 50匪〜 650nm; 第三钝化层的厚度可以为 50 匪〜 500nm; 第四钝化层的厚度 可以为 0.5μη！〜 2.5μιη; 第五钝化层的厚度可以为 20nm〜450nm。
上述各结构层的厚度， 可以在有效避免含氢基团对氧化物半导体的影响 的同时， 保证在较短的时间内完成第一钝化层的制备， 即保证生产效率。 如 果设置的厚度太薄， 则起不到避免含氢基团对氧化物半导体的影响的作用； 而如果设置的厚度过厚， 则需要更长的成膜时间（tact time ) , 造成生产效率 下降。
本实施例中， 第一钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第二钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第三钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中， 第四钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他有机绝缘材料形成的薄膜。
本实施例中， 第五钝化层除可以釆用上述列举的材料外， 还可以釆用与 上述各物质的材料特性相同或相近的其他无机绝缘材料形成的薄膜。
本实施例中栅极绝缘层的结构与实施例 1中栅极绝缘层的结构相同， 在 此不再赘述。
下面以五层的钝化层和单层的栅极绝缘层来描述制作阵列基板的方法。 如图 13所示， 该方法的示例可以包括如下步骤。
步骤 S501 , 在基板上形成栅极金属薄膜。
例如， 在玻璃基板 401上形成栅极金属薄膜层， 栅极金属薄膜通常釆用 测控溅射的方法来制备， 电极材料可选用铜及其合金， 厚度一般釆用 200nm-350nm, 令其方块电阻保持在一个相对比较低的水平。
步骤 S502, 对栅极金属薄膜进行图形化。
例如， 通过湿法刻蚀方式， 对栅极层进行图形化形成栅线和栅极 402; 此外， 如果需要， 还可以同时制作出公共电极线。
步骤 S503 , 在栅极上形成第一栅极绝缘层。
例如，在栅极层上釆用氮化硅薄膜或氮氧化硅薄膜形成第一栅极绝缘层， 该第一栅极绝缘层的厚度可以为 50nm-600nm。
步骤 S504: 对第一栅极绝缘层进行退火工艺处理。
在完成第一栅极绝缘层后实施退火工艺， 以最大程度降低第一栅极绝缘 层中可能发生断裂扩散的 H+, OH-等基团， 进而达到了提升器件稳定性的作 用。
步骤 S505, 在第一栅极绝缘层上形成有源层氧化物半导体， 并图形化。 通常， 氧化物半导体可釆用铟镓辞氧化物（IGZO ) ， 铟锡辞氧化物氧化 ( ITZO ) , 铟辞氧化物 （IZO )等以及上述几种物质的不同比例的配合物。 步骤 S506, 在完成上述的氧化物半导体有源层后， 在其上形成刻蚀阻挡 层。
步骤 S507, 在制作好上述步骤的基板上形成 TFT器件的源漏电极。 步骤 S508, 在完成上述步骤的基板上形成第一钝化层。
例如， 所述第一钝化层为第一无机绝缘层， 该第一无机绝缘层可以包括 氧化硅薄膜、 氧化铝薄膜、 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄 膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄 膜或氮氧化钕薄膜； 第一钝化层的厚度可以为 50nm〜600nm。
步骤 S509, 在第一钝化层上形成第二钝化层。
例如， 第二钝化层为第二无机绝缘层， 该第二无机绝缘层包括氮氧化铝 薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜。 第二钝化层的厚度可 以为 50nm〜650nm。
步骤 S510, 在第二钝化层上形成第三钝化层。
例如， 第三钝化层为第三无机绝缘层， 该第三无机绝缘层包括氮化硅薄 膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 第三钝化层的厚度可以为 50 nm〜500nm。
步骤 S511 , 在第三钝化层上形成第四钝化层。
第四钝化层为第一有机绝缘层， 该第一有机绝缘层可以包括树脂系绝缘 薄膜或亚克力系绝缘薄膜； 所述第四钝化层的厚度可以为 0.5μη！〜 2.5μιη。
步骤 S512, 在第四钝化层上形成第五钝化层。
例如， 第五钝化层为第四无机绝缘层， 该第四无机绝缘层包括氮氧化硅 薄膜、 氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜。 所述第五钝化层的厚度可以为 20匪〜 450謹。
步骤 S513 , 在制作好上述步骤的基板上形成像素电极层。
本实施例中除栅极绝缘层和钝化层釆用分层结构外， 其他膜层结构的制 备工艺步骤均可以通过常规技术手段来实现， 并非本实施例的设计点， 此处 不赘。 本实施例中的栅极绝缘层除了釆用单层结构之外， 还可以釆用如实施 例 1中所描述的两层或三层结构。 实施例十
本实施例与实施例九存在的区别在于： 本实施例提供的阵列基板为薄膜 晶体管的栅极层位于顶层的阵列基板， 即顶栅型阵列基板。 该钝化层包括第 一钝化层、 第二钝化层、 第三钝化层、 第四钝化层和第五钝化层， 所述第一 钝化层贴近栅极层， 所述第五钝化层贴近像素电极层， 所述第二钝化层、 第 三钝化层和第四钝化层位于第一钝化层和第五钝化层之间， 具体该钝化层的 结构、 材料及制作方法与实施例七钝化层的结构、 材料及制作方法相同， 具 体形成各结构层的工艺方法与实施例九相同， 在此不再赘述。
实施例十一
下面基于实施例九中五层结构的钝化层同时结合三层结构的栅极绝缘层 为例来表述阵列基板的制作方法， 但是该方法不限于上述结构。 该方法的示 例包括如下步骤。
步骤 S601 , 在基板上形成栅极金属薄膜层。
例如， 在玻璃基板上形成栅极金属薄膜层。 在 TFT的制作过程中， 栅极 多为釆用磁控溅射的方法来制备， 电极材料根据不同的器件结构和工艺要求 可以进行选择。通常被釆用的栅极金属有 Mo, Mo-Al-Mo合金， Mo/Al-Nd/Mo 叠成结构的电极， 纯 A1及其合金， Cu及其合金， Mo/Nd/Cu, Ti/Cu等金属， 厚度一般釆用 200 nm-350 nm, 令其方块电阻保持在一个相对比较低的水平。
步骤 S602, 对栅极金属薄膜进行图形化。
例如， 通过湿法刻蚀的方式， 对栅极金属薄膜进行图形化， 形成栅极和 公共电极线。
步骤 S603,在栅极上釆用氮化硅薄膜或氮氧化硅薄膜形成第一栅极绝缘 层。 该第一栅极绝缘层的厚度可以为 50nm-300nm。
步骤 S604, 在第一栅极绝缘层上釆用氮氧化硅薄膜形成第二栅极绝缘 层。
步骤 S605, 在第二栅极绝缘层上釆用氧化硅、 氧化铝或氧化钛形成第三 栅极绝缘层。
步骤 S606, 在第三栅极绝缘层上形成氧化物半导体有源层， 并图形化。 形成有源层氧化物半导体层， 氧化物半导体可以为铟镓辞氧化物 ( IGZO ) , 铟锡辞氧化物氧化 ( ITZO ) , 铟辞氧化物（IZO )等以及上述几 种物质组成的不同比例的配合物。
5607、 形成刻蚀阻挡层， 并图形化。
在图形化的氧化物半导体层上直接形成刻蚀阻挡层（Etch Stop Layer, ESL ) , 其材料通常需用如 SiOx、 SiNx, SiOxNy, A1203、 TiOx、 Y203等 无机绝缘材料， 减少在数据线图形化的过程中， 对氧化物半导体薄膜造成伤 害，同时可以有效地改善器件的稳定性，避免外界环境对器件的影响。对 ESL 进行图形化， 通常釆用干法刻蚀的方法。
5608、 形成数据线。
S606和 S607工艺过程之后， 形成数据线。 首先， 沉积一层金属层， 形 成数据线和电源线电极层。 该金属层多釆用磁控溅射的方法来制备， 其材料 根据不同的器件结构和工艺要求可以进行选择。 通常被釆用的电极金属有
Mo, Mo-Al-Mo合金， Mo/Al-Nd/Mo叠成结构的电极、 Cu以及金属钛及其 合金， ITO电极， Ti/Al/Ti, Mo/ITO等， 厚度一般釆用 100 nm-350 nm, 令其 方块电阻保持在一个相对比较低的水平。 在金属电极层形成后， 对其进行图 形化工艺。 通过釆用湿法刻蚀的方法对其进行图形化。
5609、 在完成上述步骤的基础上形成第一钝化层。 第一钝化层为第一无 机绝缘层， 该第一无机绝缘层可以包括氧化硅薄膜、 氧化铝薄膜、 氧化钛、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧 化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜； 第一钝化层的厚 度可以为 50匪〜 600nm。
5610、在第一钝化层上形成第二钝化层。第二钝化层为第二无机绝缘层， 该第二无机绝缘层可以包括氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或 氮氧化钕薄膜， 第二钝化层的厚度可以为 50nm〜650nm。
5611、在第二钝化层上形成第三钝化层。第三钝化层为第三无机绝缘层， 该第三无机绝缘层可以包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽 薄膜； 第三钝化层的厚度可以为 50 nm〜500匪。
5612、在第三钝化层上形成第四钝化层。第四钝化层为第一有机绝缘层， 该第一有机绝缘层可以包括树脂系绝缘薄膜或亚克力系绝缘薄膜， 第四钝化 层的厚度可以为 0.5μη！〜 2.5μιη。
S613、在第四钝化层上形成第五钝化层。第五钝化层为第四无机绝缘层， 该第四无机绝缘层可以包括氮氧化硅薄膜、 氧化硅薄膜、 氧化锆薄膜、 氧化 钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化 钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄 膜， 第五钝化层的厚度可以为 20nm〜450nm。
S614、 过孔（Via hole )刻蚀以及像素电极的沉积及图形化。
在钝化层形成之后进行过孔的刻蚀工艺， 用以实现各导线以及与像素电 极的连接。在上述工艺完成之后， 进行像素电极的沉积及图形化。如图所示， 在过孔形成之后，形成像素电极层，其材料现在广为釆用铟锡氧化物（ ITO ) , 并通过湿法刻蚀的方法对其进行图形化。
上述阵列基板的制作方法除了栅极绝缘层和钝化层的制作方法之外， 其 上述实施例及对应的附图都是以 TN型为例来介绍本发明所提供的阵列 基板结构。 在 TN型阵列基板的结构中， 像素电极一般都是位于钝化层的上 方。 在 ADS 型阵列基板的结构中包含两层透明电极， 且这两层透明电极分 别位于钝化层的上下两侧 (例如位于钝化层下方的透明电极可以直接制作在 基板上） ， 位于钝化层上方的一层透明电极可以是像素电极， 也可以是公共 电极。
高级超维场转换 ( ADvanced Super Dimension Switch, ADS或 AD-SDS ) 技术主要通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状 电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所 有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效 率。 高级超维场转换技术可以提高 TFT-LCD产品的画面品质， 具有高分辨 率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波紋（ ush Mura ) 等优点。
本发明实施例的各种阵列基板及其制作方法， 可以为应用于液晶显示的 阵列基板， 如 TN型阵列基板、 ADS型阵列基板、 IPS阵列基板、 或 VA型 阵列基板， 也可以为应用于 OLED显示的阵列基板等。
另外， 本发明实施例还提供一种显示装置， 包括上述的阵列基板。 该显 示装置包括但不限于液晶面板、 OLED面板、 液晶显示器、 液晶电视、 液晶 显示屏、 平板电脑等电子显示设备。 本发明实施例提供的显示装置、 阵列基板及其制作方法， 该阵列基板中 的栅极绝缘层和钝化层通过釆用分层结构结合退火工艺、 分层结构可最大程 度的钝化层中以及外界环境中含氢的基团， 可有效避免氢基团对氧化物半导 体的影响， 最大程度地提高整个 TFT器件的稳定性， 提高最终产品的良率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板， 包括基板以及形成在所述基板上的薄膜晶体管和像素 电极， 所述薄膜晶体管包括栅极、 栅极绝缘层、 有源层、 以及源极和漏极， 而且在所述薄膜晶体管上方覆盖有钝化层； 其中， 所述薄膜晶体管的有源层 为氧化物半导体； 所述钝化层包括至少一层无机绝缘薄膜或有机绝缘薄膜。
2、 如权利要求 1所述的阵列基板， 其中， 所述钝化层为一层， 包括第一 钝化层； 所述第一钝化层为无机绝缘层或有机绝缘层；
所述无机绝缘层包括二氧化硅薄膜、 氮化硅薄膜、 氮氧化硅薄膜、 氧化 铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜； 所述有机绝缘层包括树脂系绝缘膜或亚克力系绝缘膜。
3、如权利要求 2所述的阵列基板， 其中， 在所述第一钝化层为无机绝缘 层时， 所述第一钝化层的厚度为 50 nm〜500nm;
在所述第一钝化层为有机绝缘层时， 所述第一钝化层的厚度为 0.5μπι〜2.5μηι。
4、如权利要求 2或 3所述的阵列基板， 其中， 所述第一钝化层为经过退 火工艺处理的钝化层。
5、 如权利要求 1所述的阵列基板， 其中， 所述钝化层为两层， 包括第一 钝化层和第二钝化层； 其中， 所述第一钝化层贴近所述薄膜晶体管；
所述第一钝化层为第一无机绝缘层，该第一无机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 三氧化二钇薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧 化钕薄膜或氮氧化硅薄膜；
所述第二钝化层为第二无机绝缘层或第一有机绝缘层； 所述第二无机绝 缘层包括氮化硅薄膜、 三氧化二钇薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化 钽薄膜、 钛酸钡薄膜或氧化钕薄膜； 所述第一有机绝缘层包括树脂系绝缘膜 或亚克力系绝缘膜。
6、 如权利要求 5 所述的阵列基板， 其中， 所述第一钝化层的厚度为 50nm〜600nm。
7、如权利要求 5所述的阵列基板， 其中， 在所述第二钝化层为无机绝缘 层时， 所述第二钝化层的厚度为 50 nm〜500nm; 在所述第二钝化层为有机绝缘层时， 所述第二钝化层的厚度为
0.5μπι~2.5μπι„
8、如权利要求 5至 7中任一项所述的阵列基板， 其中， 所述第一钝化层 和所述第二钝化层均为经过退火工艺处理的钝化层。
9、 如权利要求 1所述的阵列基板， 其中， 所述钝化层为三层， 包括依次 设置的第一钝化层、 第二钝化层和第三钝化层； 其中， 所述第一钝化层贴近 所述薄膜晶体管；
所述第一钝化层为第一无机绝缘层；该第一无机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸 钡薄膜或氧化钕薄膜；
所述第二钝化层为第二无机绝缘层或第一有机绝缘层； 所述第二无机绝 缘层包括氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮 氧化钕薄膜；所述第一有机绝缘层包括树脂系绝缘薄膜或亚克力系绝缘薄膜； 所述第三钝化层为第三无机绝缘层或第二有机绝缘层； 所述第三无机绝 缘层包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第二有 机绝缘层包括树脂系绝缘薄膜或亚克力系绝缘薄膜。
10、 如权利要求 9 所述的阵列基板， 其中， 所述第一钝化层的厚度为 50nm~600nm;
在所述第二钝化层为无机绝缘层时， 所述第二钝化层的厚度为 50nm〜650nm; 在所述第二钝化层为有机绝缘层时， 所述第二钝化层的厚度 为 0.5μπι~2.5μπι;
在所述第三钝化层为无机绝缘层时， 所述第三钝化层的厚度为 50 nm〜500nm; 在所述第三钝化层为有机绝缘层时， 所述第三钝化层的厚度为 0.5μπι~2.5μπι„
11、 如权利要求 1所述的阵列基板， 其中， 所述钝化层为四层， 包括依 次设置的第一钝化层、 第二钝化层、 第三钝化层和第四钝化层； 其中， 所述 第一钝化层贴近所述薄膜晶体管；
所述第一钝化层为第一无机绝缘层，该第一无机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸 钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧 化钕薄膜；
所述第二钝化层为第二无机绝缘层， 该第二无机绝缘层包括氮氧化铝薄 膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜；
所述第三钝化层为第三无机绝缘层，该第三无机绝缘层包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜；
所述第四钝化层为第一有机绝缘层， 该第一有机绝缘层包括树脂系绝缘 薄膜或亚克力系绝缘薄膜。
12、 如权利要求 11 所述的阵列基板， 其中， 所述第一钝化层的厚度为 50nm〜600nm; 所述第二钝化层的厚度为 50nm〜650nm; 所述第三钝化层的厚 度为 50 nm〜500匪； 所述第四钝化层的厚度为 0.5μη！〜 2.5μιη。
13、 如权利要求 1所述的阵列基板， 其中， 所述钝化层为五层， 包括依 次设置的第一钝化层、第二钝化层、第三钝化层、 第四钝化层和第五钝化层； 其中， 所述第一钝化层贴近所述薄膜晶体管；
所述第一钝化层为第一无机绝缘层，该第一无机绝缘层包括氧化硅薄膜、 氧化铝薄膜、 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸 钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧 化钕薄膜；
所述第二钝化层为第二无机绝缘层， 该第二无机绝缘层包括氮氧化铝薄 膜、 氮氧化锆薄膜、 氮氧化钽薄膜或氮氧化钕薄膜；
所述第三钝化层为第三无机绝缘层，该第三无机绝缘层包括氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜；
所述第四钝化层为第一有机绝缘层， 该第一有机绝缘层包括树脂系绝缘 薄膜或亚克力系绝缘薄膜；
所述第五钝化层为第四无机绝缘层， 该第四无机绝缘层包括氮氧化硅薄 膜、 氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮 氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜。
14、 如权利要求 13 所述的阵列基板， 其中， 所述第一钝化层的厚度为 50nm〜600nm,所述第二钝化层的厚度为 50nm〜650nm; 所述第三钝化层的厚 度为 50nm〜500nm; 所述第四钝化层的厚度为 0.5μη！〜 2.5μιη; 所述第五钝化 层的厚度为 20nm〜450nm。
15、 如权利要求 1-14任一所述的阵列基板， 其中， 所述栅极绝缘层位于 所述有源层和所述栅极之间； 所述栅极绝缘层包括至少一层无机绝缘薄膜。
16、 如权利要求 15所述的阵列基板， 其中， 所述栅极绝缘层为一层， 为 第一栅极绝缘层； 所述第一栅极绝缘层为氧化硅薄膜、 三氧化二钇薄膜、 氧 化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄 膜、 氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化 钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄 膜。
17、如权利要求 16所述的阵列基板， 其中， 所述第一栅极绝缘层为经过 退火工艺处理的绝缘层。
18、如权利要求 15所述的阵列基板， 其中， 所述第一栅极绝缘层的厚度 为 50 nm~500nm„
19、 如权利要求 15所述的阵列基板， 其中， 所述栅极绝缘层为两层， 包 括第一栅极绝缘层和第二栅极绝缘层； 所述第一栅极绝缘层贴近栅极， 所述 第二栅极绝缘层贴近所述有源层；
所述第一栅极绝缘层为氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第二栅极绝缘层为氧化硅薄膜、 三氧化二钇 薄膜、 氧化铝薄膜、 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜或氮氧化钕薄膜。
20、如权利要求 19所述的阵列基板， 其中， 所述第一栅极绝缘层为经过 退火工艺处理的绝缘层；所述第二栅极绝缘层为经过退火工艺处理的绝缘层。
21、如权利要求 19所述的阵列基板， 其中， 所述第一栅极绝缘层的厚度 为 50nm-600nm; 所述第二栅极绝缘层的厚度为 50nm-650nm。
22、 如权利要求 15所述的阵列基板， 其中， 所述栅极绝缘层为三层， 包 括第一栅极绝缘层、 第二栅极绝缘层和第三栅极绝缘层； 所述第一栅极绝缘 层贴近栅极， 所述第三绝缘层贴近有源层， 所述第二栅极绝缘层位于第一栅 极绝缘层和第三栅极绝缘层中间； 其中， 所述第一栅极绝缘层为氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜或氮化钽薄膜； 所述第二栅极绝缘层为氮氧化铝薄膜、 氮氧化硅 薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜或者氮氧化钕薄膜； 所 述第三绝缘绝缘层为氧化硅薄膜、 三氧化二钇薄膜、 氧化铝薄膜、 氧化钛薄 膜、 氧化锆薄膜、 氧化钽薄膜， 钛酸钡薄膜、 氧化钕薄膜、 氮氧化铝薄膜、 氮氧化硅薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钇薄膜或者氮氧化钕 薄膜。
23、如权利要求 22所述的阵列基板， 其中， 所述第一栅极绝缘层的厚度 为 50nm-600nm; 所述第二栅极绝缘层的厚度为 50nm-650nm; 所述第三栅极 绝缘层的厚度为 20nm-600nm。
24、 如权利要求 1-23任一所述的阵列基板， 其中， 所述栅极和 /或所述 源极、 漏极为铜电极或铜合金电极。
25、 一种如权利要求 1-24任一项所述的阵列基板的制作方法， 包括： 制作钝化层的步骤， 所述钝化层包括至少一层无机绝缘薄膜或有机绝缘 薄膜。
26、 如权利要求 25所述的阵列基板的制作方法， 其中，
所述钝化层为一层， 为第一钝化层， 所述钝化层的制作方法具体包括： 步骤 S 11 , 釆用无机绝缘材料或有机绝缘材料形成第一钝化层； 步骤 S12, 对第一钝化层进行退火工艺处理。
27、如权利要求 26所述的阵列基板的制作方法，其中，所述退火工艺为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第一钝化层进行脱氢 处理； 其中， 退火腔室温度为 200 °C〜350 °C , 退火时间为 15min〜90min。
28、 如权利要求 25所述的阵列基板的制作方法， 其中，
所述钝化层为两层， 包括第一钝化层和第二钝化层； 所述第一钝化层靠 近所述薄膜晶体管；
所述钝化层制作方法包括：
步骤 S21、 釆用无机绝缘材料形成第一钝化层；
步骤 S22、 对第一钝化层进行退火工艺处理；
步骤 S23、 釆用无机绝缘材料或有机绝缘材料形成第二钝化层； 步骤 S24、 对第二钝化层进行退火工艺处理。
29、如权利要求 28所述的阵列基板的制作方法，其中，所述退火工艺为： 在 PECVD设备中加入氮气或空气的加热腔室， 对第一钝化层和第二钝 化层分别进行脱氢工艺； 其中， 退火腔室温度为 200°C〜350°C , 退火时间为 15min〜90min。
30、如权利要求 25所述的阵列基板的制作方法， 其中， 所述钝化层为三 层， 包括依次设置的第一钝化层、 第二钝化层和第三钝化层； 其中， 所述第 一钝化层贴近所述薄膜晶体管；
所述钝化层制作方法包括：
步骤 S31、 釆用无机绝缘材料形成第一钝化层；
步骤 S32、 釆用无机绝缘材料或有机材料形成第二钝化层；
步骤 S33、 釆用无机绝缘材料或有机材料形成第三钝化层。
31、如权利要求 25所述的阵列基板的制作方法， 其中， 所述钝化层为四 层， 包括依次设置的第一钝化层、 第二钝化层、 第三钝化层和第四钝化层， 其中所述第一钝化层贴近所述薄膜晶体管；
所述钝化层制作方法包括：
步骤 S41、 釆用无机绝缘材料形成第一钝化层；
步骤 S42、 釆用无机绝缘材料形成第二钝化层；
步骤 S43、 釆用无机绝缘材料形成第三钝化层；
步骤 S44、 釆用有机绝缘材料形成第四钝化层。
32、如权利要求 25所述的阵列基板的制作方法， 其中， 所述钝化层为五 层， 包括依次设置的第一钝化层、 第二钝化层、 第三钝化层、 第四钝化层和 第五钝化层； 其中， 所述第一钝化层贴近所述薄膜晶体管；
所述钝化层制作方法包括：
步骤 S51、 釆用无机绝缘材料形成第一钝化层；
步骤 S52、 釆用无机绝缘材料形成第二钝化层；
步骤 S53、 釆用无机绝缘材料形成第三钝化层；
步骤 S54、 釆用有机绝缘材料形成第四钝化层；
步骤 S55、 釆用无机绝缘材料形成第五钝化层。
33、 一种显示装置， 包括权利要求 1-24任一项所述的阵列基板。
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